mirror of
https://github.com/kr239/68030tk.git
synced 2024-06-15 19:29:41 +00:00
1205 lines
27 KiB
Plaintext
1205 lines
27 KiB
Plaintext
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
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#$ DATE Mon Jun 09 10:27:24 2014
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#$ MODULE 68030_tk
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#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 SIZE_0_ RW_000 A_30_ \
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# DS_030 A_29_ UDS_000 A_28_ LDS_000 A_27_ A0 A_26_ nEXP_SPACE A_25_ BERR A_24_ BG_030 A_23_ \
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# BG_000 A_22_ BGACK_030 A_21_ BGACK_000 A_20_ CLK_030 A_19_ CLK_000 A_18_ CLK_OSZI A_17_ \
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# CLK_DIV_OUT A_16_ CLK_EXP IPL_030_1_ FPU_CS IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC \
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# FC_0_ AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
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# AMIGA_BUS_ENABLE_LOW CIIN
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#$ NODES 71 inst_BGACK_030_INTreg inst_avec_expreg inst_VMA_INTreg \
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# inst_AMIGA_BUS_ENABLE_INTreg inst_CLK_OUT_NEreg inst_AS_030_000_SYNC \
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# inst_BGACK_030_INT_D inst_AS_000_DMA inst_VPA_D inst_CLK_OUT_PRE_50_D \
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# inst_CLK_OUT_PRE inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_OUT_PRE_50 \
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# inst_CLK_OUT_PRE_25 inst_CLK_000_D2 inst_CLK_000_D3 inst_CLK_000_NE \
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# inst_CLK_OUT_PRE_D CLK_000_P_SYNC_9_ CLK_000_N_SYNC_11_ inst_AS_000_INT \
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# SM_AMIGA_7_ SM_AMIGA_6_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_4_ inst_RW_000_INT \
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# inst_DSACK1_INT inst_CLK_030_H inst_RW_000_DMA BG_000DFFSHreg inst_LDS_000_INT \
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# inst_DS_000_ENABLE inst_UDS_000_INT inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ \
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# inst_A0_DMA CLK_000_N_SYNC_0_ CLK_OUT_INTreg CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ \
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# CLK_000_N_SYNC_3_ IPL_030DFFSH_0_reg CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ \
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# IPL_030DFFSH_1_reg CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ IPL_030DFFSH_2_reg \
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# CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_P_SYNC_0_ \
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# CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ \
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# CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ \
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# SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ RESETDFFRHreg cpu_est_0_ cpu_est_1_ cpu_est_2_ \
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# cpu_est_3_reg
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.model bus68030
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.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
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BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \
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A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \
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A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \
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A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
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inst_avec_expreg.BLIF inst_VMA_INTreg.BLIF inst_AMIGA_BUS_ENABLE_INTreg.BLIF \
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inst_CLK_OUT_NEreg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
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inst_AS_000_DMA.BLIF inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF \
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inst_CLK_OUT_PRE.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
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inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF inst_CLK_000_D2.BLIF \
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inst_CLK_000_D3.BLIF inst_CLK_000_NE.BLIF inst_CLK_OUT_PRE_D.BLIF \
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CLK_000_P_SYNC_9_.BLIF CLK_000_N_SYNC_11_.BLIF inst_AS_000_INT.BLIF \
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SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \
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SM_AMIGA_4_.BLIF inst_RW_000_INT.BLIF inst_DSACK1_INT.BLIF inst_CLK_030_H.BLIF \
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inst_RW_000_DMA.BLIF BG_000DFFSHreg.BLIF inst_LDS_000_INT.BLIF \
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inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF inst_DS_000_DMA.BLIF \
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SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF CLK_000_N_SYNC_0_.BLIF \
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CLK_OUT_INTreg.BLIF CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF \
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CLK_000_N_SYNC_3_.BLIF IPL_030DFFSH_0_reg.BLIF CLK_000_N_SYNC_4_.BLIF \
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CLK_000_N_SYNC_5_.BLIF IPL_030DFFSH_1_reg.BLIF CLK_000_N_SYNC_6_.BLIF \
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CLK_000_N_SYNC_7_.BLIF IPL_030DFFSH_2_reg.BLIF CLK_000_N_SYNC_8_.BLIF \
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CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF CLK_000_P_SYNC_0_.BLIF \
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CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.BLIF \
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CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF \
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CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF SM_AMIGA_5_.BLIF \
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SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF RESETDFFRHreg.BLIF cpu_est_0_.BLIF \
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cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF AS_030.PIN.BLIF \
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AS_000.PIN.BLIF RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF \
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LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF \
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DTACK.PIN.BLIF RW.PIN.BLIF
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.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \
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AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
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CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \
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cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C \
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cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_7_.D \
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SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \
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SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \
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SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \
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SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \
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SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_000_P_SYNC_2_.D \
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CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_2_.AR CLK_000_P_SYNC_3_.D \
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CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_3_.AR CLK_000_P_SYNC_4_.D \
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CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_4_.AR CLK_000_P_SYNC_5_.D \
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CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_5_.AR CLK_000_P_SYNC_6_.D \
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CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_6_.AR CLK_000_P_SYNC_7_.D \
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CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_7_.AR CLK_000_P_SYNC_8_.D \
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CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_8_.AR CLK_000_P_SYNC_9_.D \
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CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_9_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C \
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SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D \
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IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \
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IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \
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IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP CLK_000_N_SYNC_0_.D \
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CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_0_.AR CLK_000_N_SYNC_1_.D \
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CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_1_.AR CLK_000_N_SYNC_2_.D \
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CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_2_.AR CLK_000_N_SYNC_3_.D \
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CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_3_.AR CLK_000_N_SYNC_4_.D \
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CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_4_.AR CLK_000_N_SYNC_5_.D \
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CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_5_.AR CLK_000_N_SYNC_6_.D \
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CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_6_.AR CLK_000_N_SYNC_7_.D \
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CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_7_.AR CLK_000_N_SYNC_8_.D \
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CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_8_.AR CLK_000_N_SYNC_9_.D \
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CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_9_.AR CLK_000_N_SYNC_10_.D \
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CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_10_.AR CLK_000_N_SYNC_11_.D \
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CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_11_.AR CLK_000_P_SYNC_0_.D \
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CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_0_.AR CLK_000_P_SYNC_1_.D \
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CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_1_.AR inst_VMA_INTreg.C inst_VMA_INTreg.AP \
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inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \
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inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR \
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inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \
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BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_LDS_000_INT.D \
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inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_AS_000_INT.D inst_AS_000_INT.C \
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inst_AS_000_INT.AP inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \
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inst_DS_000_ENABLE.AR inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP \
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inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_RW_000_INT.D \
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inst_RW_000_INT.C inst_RW_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C \
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inst_A0_DMA.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_RW_000_DMA.D \
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inst_RW_000_DMA.C inst_RW_000_DMA.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \
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inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \
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inst_AMIGA_BUS_ENABLE_INTreg.D inst_AMIGA_BUS_ENABLE_INTreg.C \
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inst_AMIGA_BUS_ENABLE_INTreg.AP inst_CLK_OUT_NEreg.D inst_CLK_OUT_NEreg.C \
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inst_CLK_OUT_NEreg.AR inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \
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inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D3.D \
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inst_CLK_000_D3.C inst_CLK_000_D3.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
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CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP \
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inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP \
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inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR \
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inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_D.AR \
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inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D \
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inst_VPA_D.C inst_VPA_D.AP inst_avec_expreg.D inst_avec_expreg.C \
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inst_avec_expreg.AR inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_000_NE.AR \
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inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \
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RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \
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DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ AS_030.OE AS_000.OE \
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RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE \
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DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE inst_VMA_INTreg.D.X1 \
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inst_VMA_INTreg.D.X2
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.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
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cpu_est_3_reg.BLIF cpu_est_1_.D
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110-- 1
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-01-- 1
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0-1-- 1
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1--00 1
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1--11 1
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11110 0
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11101 0
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-0010 0
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-0001 0
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0-0-- 0
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.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
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cpu_est_3_reg.BLIF cpu_est_2_.D
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100-- 1
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--11- 1
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0--1- 1
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11--1 1
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--100 0
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110-0 0
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-010- 0
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0--0- 0
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.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
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cpu_est_3_reg.BLIF cpu_est_3_reg.D
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11-0- 1
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1-00- 1
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--0-1 1
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0---1 1
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---01 1
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1-11- 0
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-01-0 0
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0---0 0
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---10 0
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.names nEXP_SPACE.BLIF inst_avec_expreg.BLIF inst_AS_030_000_SYNC.BLIF \
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inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_0_.BLIF \
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SM_AMIGA_7_.D
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----01- 1
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---1-1- 1
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--1--1- 1
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0----1- 1
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-1----1 1
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10001-- 0
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1-001-0 0
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-0---0- 0
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-----00 0
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.names nEXP_SPACE.BLIF inst_avec_expreg.BLIF inst_AS_030_000_SYNC.BLIF \
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inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF \
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SM_AMIGA_6_.D
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1-0011- 1
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-0---01 1
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-1---0- 0
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----01- 0
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---1-1- 0
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--1--1- 0
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0----1- 0
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-----00 0
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.names inst_avec_expreg.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_6_.BLIF \
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SM_AMIGA_5_.BLIF SM_AMIGA_5_.D
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1-1- 1
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-0-1 1
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-10- 0
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01-- 0
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--00 0
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0--0 0
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.names inst_avec_expreg.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_4_.BLIF \
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SM_AMIGA_5_.BLIF SM_AMIGA_4_.D
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0-1- 1
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-1-1 1
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-00- 0
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10-- 0
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--00 0
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1--0 0
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.names inst_avec_expreg.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF \
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inst_CLK_000_NE.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF cpu_est_1_.BLIF \
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cpu_est_3_reg.BLIF DTACK.PIN.BLIF SM_AMIGA_3_.D
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--0--1-0- 1
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--0--11-- 1
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-10--1--- 1
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1---1---- 1
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---0-1--- 1
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--1--1--1 1
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-0010-01- 0
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0001--01- 0
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--110---0 0
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0-11----0 0
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----00--- 0
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0----0--- 0
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.names inst_avec_expreg.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF \
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inst_CLK_000_NE.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF cpu_est_1_.BLIF \
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cpu_est_3_reg.BLIF DTACK.PIN.BLIF SM_AMIGA_2_.D
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-0011-01- 1
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--111---0 1
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0----1--- 1
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--0--0-0- 0
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1-0----0- 0
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--0--01-- 0
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1-0---1-- 0
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-10--0--- 0
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110------ 0
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----00--- 0
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---0-0--- 0
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1---0---- 0
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1--0----- 0
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--1--0--1 0
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1-1-----1 0
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.names inst_avec_expreg.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF \
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SM_AMIGA_2_.BLIF SM_AMIGA_1_.D
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-01- 1
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1--1 1
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0-0- 0
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01-- 0
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--00 0
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-1-0 0
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.names inst_avec_expreg.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF \
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SM_AMIGA_0_.BLIF SM_AMIGA_0_.D
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-110 1
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0--1 1
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1--1 0
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--00 0
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-0-0 0
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.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
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LDS_000.PIN.BLIF SIZE_DMA_0_.D
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--1- 1
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-1-- 1
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1--- 1
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---1 1
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0000 0
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.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
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LDS_000.PIN.BLIF SIZE_DMA_1_.D
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--00 1
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--11 1
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-1-- 1
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1--- 1
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0010 0
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0001 0
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.names IPL_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
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IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_0_reg.D
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110- 1
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--11 1
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-0-1 1
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010- 0
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--10 0
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-0-0 0
|
|
.names IPL_1_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
|
|
IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_1_reg.D
|
|
110- 1
|
|
--11 1
|
|
-0-1 1
|
|
010- 0
|
|
--10 0
|
|
-0-0 0
|
|
.names IPL_2_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
|
|
IPL_030DFFSH_2_reg.BLIF IPL_030DFFSH_2_reg.D
|
|
110- 1
|
|
--11 1
|
|
-0-1 1
|
|
010- 0
|
|
--10 0
|
|
-0-0 0
|
|
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF \
|
|
inst_CLK_000_D3.BLIF CLK_000_N_SYNC_0_.D
|
|
0111 1
|
|
--0- 0
|
|
-0-- 0
|
|
1--- 0
|
|
---0 0
|
|
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF \
|
|
inst_CLK_000_D3.BLIF CLK_000_P_SYNC_0_.D
|
|
1000 1
|
|
--1- 0
|
|
-1-- 0
|
|
0--- 0
|
|
---1 0
|
|
.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \
|
|
inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D
|
|
1-10 1
|
|
11-- 1
|
|
-00- 0
|
|
0--- 0
|
|
-0-1 0
|
|
.names FC_1_.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF A_19_.BLIF A_18_.BLIF \
|
|
A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
|
|
inst_AS_030_000_SYNC.BLIF SM_AMIGA_7_.BLIF AS_030.PIN.BLIF \
|
|
inst_AS_030_000_SYNC.D
|
|
1-100101-1-- 1
|
|
---------10- 1
|
|
--------01-- 1
|
|
-0-------1-- 1
|
|
-----------1 1
|
|
-1-----01-10 0
|
|
-1----1-1-10 0
|
|
-1---0--1-10 0
|
|
-1--1---1-10 0
|
|
-1-1----1-10 0
|
|
-10-----1-10 0
|
|
01------1-10 0
|
|
---------0-0 0
|
|
.names nEXP_SPACE.BLIF BG_030.BLIF CLK_000.BLIF SM_AMIGA_7_.BLIF \
|
|
BG_000DFFSHreg.BLIF AS_030.PIN.BLIF BG_000DFFSHreg.D
|
|
---01- 1
|
|
--0-1- 1
|
|
0---1- 1
|
|
----10 1
|
|
-1---- 1
|
|
1011-1 0
|
|
-0--0- 0
|
|
.names inst_LDS_000_INT.BLIF DS_030.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \
|
|
A0.PIN.BLIF inst_LDS_000_INT.D
|
|
-0100 1
|
|
11--- 1
|
|
01--- 0
|
|
-0-1- 0
|
|
-00-- 0
|
|
-0--1 0
|
|
.names inst_avec_expreg.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \
|
|
AS_030.PIN.BLIF inst_AS_000_INT.D
|
|
-10- 1
|
|
01-- 1
|
|
--01 1
|
|
0--1 1
|
|
1-1- 0
|
|
-0-0 0
|
|
.names inst_avec_expreg.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF \
|
|
inst_DS_000_ENABLE.BLIF AS_030.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D
|
|
---10- 1
|
|
1-1--- 1
|
|
11---1 1
|
|
-00-1- 0
|
|
-000-- 0
|
|
--0-10 0
|
|
0---1- 0
|
|
--00-0 0
|
|
0--0-- 0
|
|
.names inst_CLK_OUT_NEreg.BLIF inst_CLK_000_D1.BLIF SM_AMIGA_1_.BLIF \
|
|
inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D
|
|
--01- 1
|
|
-0-1- 1
|
|
1--1- 1
|
|
--0-1 1
|
|
-0--1 1
|
|
1---1 1
|
|
011-- 0
|
|
---00 0
|
|
.names inst_UDS_000_INT.BLIF DS_030.PIN.BLIF A0.PIN.BLIF inst_UDS_000_INT.D
|
|
11- 1
|
|
-01 1
|
|
01- 0
|
|
-00 0
|
|
.names inst_avec_expreg.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF \
|
|
inst_RW_000_INT.BLIF RW.PIN.BLIF inst_RW_000_INT.D
|
|
--01- 1
|
|
0--1- 1
|
|
1-1-1 1
|
|
-1--- 1
|
|
101-0 0
|
|
-000- 0
|
|
00-0- 0
|
|
.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
|
|
LDS_000.PIN.BLIF inst_A0_DMA.D
|
|
0010 1
|
|
--0- 0
|
|
-1-- 0
|
|
1--- 0
|
|
---1 0
|
|
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
inst_CLK_030_H.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
|
|
inst_CLK_030_H.D
|
|
1100-00- 1
|
|
1100-0-0 1
|
|
--0-100- 1
|
|
--0-10-0 1
|
|
-0--1--- 1
|
|
-1---1-- 0
|
|
-11----- 0
|
|
-1----11 0
|
|
---10--- 0
|
|
-0--0--- 0
|
|
0---0--- 0
|
|
.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_RW_000_DMA.BLIF \
|
|
AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
|
|
inst_RW_000_DMA.D
|
|
1-1---- 1
|
|
0---1-- 1
|
|
---1--- 1
|
|
-1----- 1
|
|
-----11 1
|
|
00-000- 0
|
|
1000-0- 0
|
|
00-00-0 0
|
|
1000--0 0
|
|
.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \
|
|
UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_DS_000_DMA.D
|
|
0-11----- 1
|
|
---01-0-- 1
|
|
1---1-0-- 1
|
|
--1---1-- 1
|
|
-----1--- 1
|
|
-1------- 1
|
|
-------11 1
|
|
0001-0-0- 0
|
|
-0-00000- 0
|
|
10--0000- 0
|
|
0001-0--0 0
|
|
-0-0000-0 0
|
|
10--000-0 0
|
|
-00--010- 0
|
|
-00--01-0 0
|
|
.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_AS_000_DMA.D
|
|
1-1--- 1
|
|
---1-- 1
|
|
-1---- 1
|
|
----11 1
|
|
-0000- 0
|
|
00-00- 0
|
|
-000-0 0
|
|
00-0-0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF \
|
|
inst_AMIGA_BUS_ENABLE_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
|
|
inst_BGACK_030_INT_D.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF \
|
|
inst_CLK_000_NE.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \
|
|
AS_030.PIN.BLIF inst_AMIGA_BUS_ENABLE_INTreg.D
|
|
-1----0-100- 1
|
|
-1---1--100- 1
|
|
-1-1----100- 1
|
|
01------100- 1
|
|
-11-------1- 1
|
|
-11-----0--- 1
|
|
-1-----1-1-1 1
|
|
-11------1-- 1
|
|
-1------11-1 1
|
|
-1--0------- 1
|
|
-1--------11 1
|
|
1--0101-100- 0
|
|
--0-1--00-0- 0
|
|
--0-1---000- 0
|
|
--0-1-----10 0
|
|
--0-1----1-0 0
|
|
-0---------- 0
|
|
.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE_D.BLIF inst_CLK_OUT_NEreg.D
|
|
01 1
|
|
1- 0
|
|
-0 0
|
|
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
|
|
0 1
|
|
1 0
|
|
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
|
|
1 1
|
|
0 0
|
|
.names BERR
|
|
0
|
|
.names BG_000DFFSHreg.BLIF BG_000
|
|
1 1
|
|
0 0
|
|
.names inst_BGACK_030_INTreg.BLIF BGACK_030
|
|
1 1
|
|
0 0
|
|
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
|
|
1 1
|
|
0 0
|
|
.names CLK_OUT_INTreg.BLIF CLK_EXP
|
|
1 1
|
|
0 0
|
|
.names FC_1_.BLIF BGACK_000.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
|
|
FC_0_.BLIF AS_030.PIN.BLIF FPU_CS
|
|
------0- 1
|
|
-----1-- 1
|
|
----0--- 1
|
|
---1---- 1
|
|
--1----- 1
|
|
-0------ 1
|
|
0------- 1
|
|
-------1 1
|
|
11001010 0
|
|
.names AVEC
|
|
1
|
|
.names inst_avec_expreg.BLIF AVEC_EXP
|
|
1 1
|
|
0 0
|
|
.names cpu_est_3_reg.BLIF E
|
|
1 1
|
|
0 0
|
|
.names inst_VMA_INTreg.BLIF VMA
|
|
1 1
|
|
0 0
|
|
.names RESETDFFRHreg.BLIF RESET
|
|
1 1
|
|
0 0
|
|
.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF AMIGA_BUS_ENABLE
|
|
1 1
|
|
0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF RW.PIN.BLIF \
|
|
AMIGA_BUS_DATA_DIR
|
|
0001 1
|
|
-1-0 1
|
|
1--1 0
|
|
--11 0
|
|
-0-0 0
|
|
-1-1 0
|
|
.names inst_CLK_OUT_NEreg.BLIF AMIGA_BUS_ENABLE_LOW
|
|
1 1
|
|
0 0
|
|
.names A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF CIIN
|
|
1111 1
|
|
--0- 0
|
|
-0-- 0
|
|
0--- 0
|
|
---0 0
|
|
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
|
|
1 1
|
|
0 0
|
|
.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
|
|
1 1
|
|
0 0
|
|
.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_est_0_.D
|
|
10 1
|
|
01 1
|
|
00 0
|
|
11 0
|
|
.names CLK_OSZI.BLIF cpu_est_0_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF cpu_est_0_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF cpu_est_1_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF cpu_est_1_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF cpu_est_2_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF cpu_est_2_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF cpu_est_3_reg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF cpu_est_3_reg.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_7_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_7_.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_6_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_5_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_4_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_3_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_2_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_1_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_0_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_2_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_3_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_4_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_5_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_6_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_7_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_8_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_8_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_9_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SIZE_DMA_0_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SIZE_DMA_0_.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SIZE_DMA_1_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SIZE_DMA_1_.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF IPL_030DFFSH_0_reg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF IPL_030DFFSH_1_reg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF IPL_030DFFSH_2_reg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_0_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_N_SYNC_0_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_1_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_N_SYNC_1_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_2_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_N_SYNC_2_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
|
|
1 1
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.names CLK_OSZI.BLIF CLK_000_N_SYNC_3_.C
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.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
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.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
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.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C
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.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
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.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C
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|
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.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
|
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1 1
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|
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.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C
|
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1 1
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|
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0 1
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1 0
|
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.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
|
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1 1
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|
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|
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1 1
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|
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|
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0 1
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1 0
|
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.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
|
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1 1
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|
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.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C
|
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1 1
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|
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.names RST.BLIF CLK_000_N_SYNC_10_.AR
|
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0 1
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1 0
|
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.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
|
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1 1
|
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0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C
|
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1 1
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0 0
|
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.names RST.BLIF CLK_000_N_SYNC_11_.AR
|
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0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C
|
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1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_0_.AR
|
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0 1
|
|
1 0
|
|
.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_000_P_SYNC_1_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_VMA_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_VMA_INTreg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.AP
|
|
0 1
|
|
1 0
|
|
.names inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_OUT_PRE_50.BLIF \
|
|
inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
|
|
010 1
|
|
-01 1
|
|
1-1 1
|
|
011 0
|
|
-00 0
|
|
1-0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_25.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_OUT_PRE_25.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_AS_030_000_SYNC.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF BG_000DFFSHreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF BG_000DFFSHreg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_LDS_000_INT.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_AS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_AS_000_INT.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_DS_000_ENABLE.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_DSACK1_INT.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_DSACK1_INT.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_UDS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_UDS_000_INT.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_RW_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_RW_000_INT.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_A0_DMA.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_A0_DMA.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_CLK_030_H.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_RW_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_RW_000_DMA.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_DS_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_DS_000_DMA.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_AS_000_DMA.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_AMIGA_BUS_ENABLE_INTreg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_NEreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_OUT_NEreg.AR
|
|
0 1
|
|
1 0
|
|
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_D2.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_000_D2.AP
|
|
0 1
|
|
1 0
|
|
.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_OUT_PRE.AR
|
|
0 1
|
|
1 0
|
|
.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_D3.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_000_D3.AP
|
|
0 1
|
|
1 0
|
|
.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_OUT_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF CLK_OUT_INTreg.AR
|
|
0 1
|
|
1 0
|
|
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_D1.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_000_D1.AP
|
|
0 1
|
|
1 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_BGACK_030_INT_D.AP
|
|
0 1
|
|
1 0
|
|
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50_D.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50_D.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_OUT_PRE_50_D.AR
|
|
0 1
|
|
1 0
|
|
.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE_D.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_OUT_PRE_D.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000.BLIF inst_CLK_000_D0.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_D0.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_000_D0.AP
|
|
0 1
|
|
1 0
|
|
.names VPA.BLIF inst_VPA_D.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_VPA_D.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_VPA_D.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_000_P_SYNC_9_.BLIF inst_avec_expreg.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_avec_expreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_avec_expreg.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_NE.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_000_NE.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_OUT_PRE_50.AR
|
|
0 1
|
|
1 0
|
|
.names RESETDFFRHreg.D
|
|
1
|
|
.names CLK_OSZI.BLIF RESETDFFRHreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF RESETDFFRHreg.AR
|
|
0 1
|
|
1 0
|
|
.names SIZE_DMA_1_.BLIF SIZE_1_
|
|
1 1
|
|
0 0
|
|
.names inst_AS_000_DMA.BLIF AS_030
|
|
1 1
|
|
0 0
|
|
.names inst_AS_000_INT.BLIF AS_000
|
|
1 1
|
|
0 0
|
|
.names inst_RW_000_INT.BLIF RW_000
|
|
1 1
|
|
0 0
|
|
.names inst_DS_000_DMA.BLIF DS_030
|
|
1 1
|
|
0 0
|
|
.names inst_DS_000_ENABLE.BLIF inst_UDS_000_INT.BLIF UDS_000
|
|
0- 1
|
|
-1 1
|
|
10 0
|
|
.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF LDS_000
|
|
1- 1
|
|
-0 1
|
|
01 0
|
|
.names inst_A0_DMA.BLIF A0
|
|
1 1
|
|
0 0
|
|
.names inst_DSACK1_INT.BLIF DSACK1
|
|
1 1
|
|
0 0
|
|
.names DSACK1.PIN.BLIF DTACK
|
|
1 1
|
|
0 0
|
|
.names inst_RW_000_DMA.BLIF RW
|
|
1 1
|
|
0 0
|
|
.names SIZE_DMA_0_.BLIF SIZE_0_
|
|
1 1
|
|
0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
AS_030.OE
|
|
000 1
|
|
-1- 0
|
|
1-- 0
|
|
--1 0
|
|
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
|
|
1 1
|
|
0 0
|
|
.names inst_BGACK_030_INTreg.BLIF RW_000.OE
|
|
1 1
|
|
0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
DS_030.OE
|
|
000 1
|
|
-1- 0
|
|
1-- 0
|
|
--1 0
|
|
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
|
|
1 1
|
|
0 0
|
|
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
|
|
1 1
|
|
0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
SIZE_0_.OE
|
|
000 1
|
|
-1- 0
|
|
1-- 0
|
|
--1 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
SIZE_1_.OE
|
|
000 1
|
|
-1- 0
|
|
1-- 0
|
|
--1 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF A0.OE
|
|
000 1
|
|
-1- 0
|
|
1-- 0
|
|
--1 0
|
|
.names nEXP_SPACE.BLIF DSACK1.OE
|
|
1 1
|
|
0 0
|
|
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
DTACK.OE
|
|
000 1
|
|
-1- 0
|
|
1-- 0
|
|
--1 0
|
|
.names inst_BGACK_030_INTreg.BLIF RW.OE
|
|
0 1
|
|
1 0
|
|
.names FC_1_.BLIF BGACK_000.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
|
|
FC_0_.BLIF AS_030.PIN.BLIF BERR.OE
|
|
11001010 1
|
|
------0- 0
|
|
-----1-- 0
|
|
----0--- 0
|
|
---1---- 0
|
|
--1----- 0
|
|
-0------ 0
|
|
0------- 0
|
|
-------1 0
|
|
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
|
|
A_25_.BLIF A_24_.BLIF CIIN.OE
|
|
00000000 1
|
|
------1- 0
|
|
-----1-- 0
|
|
----1--- 0
|
|
---1---- 0
|
|
--1----- 0
|
|
-1------ 0
|
|
1------- 0
|
|
-------1 0
|
|
.names inst_VMA_INTreg.BLIF inst_CLK_000_D0.BLIF inst_VMA_INTreg.D.X1
|
|
10 1
|
|
0- 0
|
|
-1 0
|
|
.names inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \
|
|
inst_AS_000_INT.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
|
|
cpu_est_3_reg.BLIF inst_VMA_INTreg.D.X2
|
|
10--10-- 1
|
|
1-1----- 1
|
|
--110110 1
|
|
-10----- 0
|
|
0--0---- 0
|
|
0---1--- 0
|
|
--0-0--- 0
|
|
--0--1-- 0
|
|
0----0-- 0
|
|
0-----0- 0
|
|
0------1 0
|
|
.end
|