68030tk/Logic/BUS68030.bl1

#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Mon Jun 09 10:27:24 2014
#$ MODULE bus68030
#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 SIZE_0_ RW_000 A_30_ \
#  DS_030 A_29_ UDS_000 A_28_ LDS_000 A_27_ A0 A_26_ nEXP_SPACE A_25_ BERR A_24_ BG_030 A_23_ \
#  BG_000 A_22_ BGACK_030 A_21_ BGACK_000 A_20_ CLK_030 A_19_ CLK_000 A_18_ CLK_OSZI A_17_ \
#  CLK_DIV_OUT A_16_ CLK_EXP IPL_030_1_ FPU_CS IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC \
#  FC_0_ AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
#  AMIGA_BUS_ENABLE_LOW CIIN
#$ NODES 425 amiga_bus_enable_int_0_un3_n a_c_16__n amiga_bus_enable_int_0_un1_n \
#  amiga_bus_enable_int_0_un0_n a_c_17__n bg_000_0_un3_n bg_000_0_un1_n a_c_18__n \
#  bg_000_0_un0_n inst_BGACK_030_INTreg lds_000_int_0_un3_n vcc_n_n a_c_19__n \
#  lds_000_int_0_un1_n inst_avec_expreg lds_000_int_0_un0_n inst_VMA_INTreg a_c_20__n \
#  ds_000_enable_0_un3_n inst_AMIGA_BUS_ENABLE_INTreg ds_000_enable_0_un1_n \
#  inst_CLK_OUT_NEreg a_c_21__n ds_000_enable_0_un0_n inst_AS_030_000_SYNC \
#  uds_000_int_0_un3_n inst_BGACK_030_INT_D a_c_22__n uds_000_int_0_un1_n \
#  inst_AS_000_DMA uds_000_int_0_un0_n inst_VPA_D a_c_23__n inst_CLK_OUT_PRE_50_D \
#  inst_CLK_OUT_PRE a_c_24__n inst_CLK_000_D0 inst_CLK_000_D1 a_c_25__n \
#  inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 a_c_26__n inst_CLK_000_D2 inst_CLK_000_D3 \
#  a_c_27__n inst_CLK_000_NE gnd_n_n a_c_28__n inst_CLK_OUT_PRE_D CLK_000_P_SYNC_9_ \
#  a_c_29__n CLK_000_N_SYNC_11_ inst_AS_000_INT a_c_30__n SM_AMIGA_7_ SM_AMIGA_6_ \
#  a_c_31__n SM_AMIGA_1_ SM_AMIGA_0_ A0_c SM_AMIGA_4_ inst_RW_000_INT nEXP_SPACE_c \
#  inst_DSACK1_INT state_machine_un3_clk_out_pre_50_n BG_030_c inst_CLK_030_H \
#  inst_RW_000_DMA BG_000DFFSHreg un1_LDS_000_INT inst_LDS_000_INT inst_DS_000_ENABLE \
#  BGACK_000_c un1_UDS_000_INT inst_UDS_000_INT CLK_030_c CLK_000_c inst_DS_000_DMA \
#  SIZE_DMA_0_ CLK_OSZI_c SIZE_DMA_1_ inst_A0_DMA CLK_000_N_SYNC_0_ CLK_OUT_INTreg \
#  CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ IPL_030DFFSH_0_reg \
#  CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ IPL_030DFFSH_1_reg CLK_000_N_SYNC_6_ \
#  CLK_000_N_SYNC_7_ IPL_030DFFSH_2_reg CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ \
#  ipl_c_0__n CLK_000_N_SYNC_10_ CLK_000_P_SYNC_0_ ipl_c_1__n CLK_000_P_SYNC_1_ \
#  CLK_000_P_SYNC_2_ ipl_c_2__n CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ DSACK1_c \
#  CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ DTACK_c CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ \
#  un1_SM_AMIGA_0_sqmuxa_1 un1_as_030 un19_fpu_cs state_machine_un10_bg_030_n \
#  SM_AMIGA_5_ SM_AMIGA_3_ RST_c SM_AMIGA_2_ RESETDFFRHreg RW_c fc_c_0__n fc_c_1__n \
#  AMIGA_BUS_DATA_DIR_c SM_AMIGA_0_sqmuxa_i DS_000_ENABLE_0_sqmuxa_i \
#  un1_SM_AMIGA_0_sqmuxa_1_i state_machine_un10_clk_000_ne_i_n \
#  state_machine_un4_clk_000_ne_i_n CLK_OUT_PRE_25_0 \
#  state_machine_un6_clk_000_ne_i_n N_97_i sm_amiga_ns_0_4__n N_99_i N_98_i \
#  sm_amiga_ns_0_5__n N_86_i state_machine_un6_clk_000_p_sync_i_n \
#  state_machine_un6_bgack_000_0_n N_167_i cpu_est_0_ N_166_i cpu_est_1_ \
#  AMIGA_BUS_DATA_DIR_c_0 cpu_est_2_ N_162_i cpu_est_3_reg N_161_i cpu_estse N_152_i \
#  state_machine_un10_clk_000_d0_i_n state_machine_un5_clk_000_d0_i_n \
#  state_machine_un12_clk_000_d0_0_n N_198 cpu_est_ns_0_1__n N_207 N_156_i \
#  SM_AMIGA_0_sqmuxa N_155_i N_89 N_163_i N_90 state_machine_un5_clk_000_d0_1_i_n \
#  state_machine_un8_bg_030_n state_machine_un10_clk_000_d0_2_i_n N_91 N_159_i N_92 \
#  N_160_i N_87 cpu_est_ns_0_2__n N_94 state_machine_un10_bgack_030_int_0_n N_95 \
#  state_machine_ds_000_dma_3_0_n N_96 state_machine_size_dma_4_0_0__n N_100 \
#  state_machine_size_dma_4_0_1__n N_101 CLK_030_H_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \
#  CLK_030_H_1_sqmuxa_i N_85 state_machine_clk_030_h_2_f1_0_n DSACK1_INT_0_sqmuxa \
#  un3_dtack_i AS_030_000_SYNC_0_sqmuxa state_machine_un5_bgack_030_int_d_i_n \
#  un1_bgack_030_int_d AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \
#  state_machine_un3_bgack_030_int_d_n AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \
#  AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 \
#  AMIGA_BUS_ENABLE_INT_3_sqmuxa state_machine_rw_000_int_3_0_n N_84 N_66_0 \
#  AMIGA_BUS_ENABLE_INT_2_sqmuxa N_91_i N_93 N_93_i N_66 state_machine_rw_000_int_3_n \
#  AS_030_000_SYNC_i un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa N_84_0 \
#  AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \
#  AS_030_000_SYNC_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i AS_000_INT_1_sqmuxa \
#  state_machine_un3_bgack_030_int_d_i_n state_machine_un8_bgack_030_int_n \
#  un1_bgack_030_int_d_0 N_167_1 N_87_0 state_machine_un10_bgack_030_int_n N_85_0 \
#  CLK_030_H_1_sqmuxa AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i AS_000_DMA_1_sqmuxa N_92_i \
#  DS_000_DMA_1_sqmuxa DS_000_DMA_1_sqmuxa_1 N_100_i \
#  state_machine_un24_bgack_030_int_n N_101_i state_machine_clk_030_h_2_n \
#  sm_amiga_ns_0_6__n state_machine_clk_030_h_2_f1_n N_95_i \
#  state_machine_un31_bgack_030_int_n N_96_i state_machine_ds_000_dma_3_n \
#  sm_amiga_ns_0_3__n cpu_est_ns_2__n N_94_i N_160 sm_amiga_ns_0_2__n N_159 \
#  sm_amiga_ns_0_0__n state_machine_un10_clk_000_d0_2_n BG_030_c_i \
#  state_machine_un5_clk_000_d0_1_n state_machine_un8_bg_030_i_n N_163 \
#  state_machine_un10_bg_030_0_n N_155 LDS_000_INT_i N_156 un1_LDS_000_INT_0 \
#  cpu_est_ns_1__n UDS_000_INT_i state_machine_un12_clk_000_d0_n un1_UDS_000_INT_0 \
#  state_machine_un6_clk_000_p_sync_n state_machine_un7_ds_030_i_n \
#  state_machine_un10_clk_000_d0_n A0_c_i state_machine_un5_clk_000_d0_n \
#  size_c_i_1__n N_161 un1_bgack_030_int_d_0_1 state_machine_un10_clk_000_ne_1_n \
#  N_84_0_1 N_162 N_84_0_2 state_machine_un5_clk_000_d0_2_n un3_dtack_i_1 N_166 \
#  cpu_est_ns_0_1_2__n N_167 N_198_1 DSACK1_INT_1_sqmuxa N_198_2 \
#  state_machine_un6_bgack_000_n N_207_1 DS_000_ENABLE_0_sqmuxa N_207_2 \
#  state_machine_un10_clk_000_ne_n N_207_3 N_86 N_207_4 \
#  state_machine_un6_clk_000_ne_n N_207_5 N_98 N_207_6 N_99 \
#  state_machine_un7_ds_030_i_1_n N_97 state_machine_un8_bg_030_1_n \
#  state_machine_un4_clk_000_ne_n state_machine_un8_bg_030_2_n un19_fpu_cs_i \
#  DSACK1_INT_0_sqmuxa_1 DTACK_i AS_030_000_SYNC_0_sqmuxa_1_0 avec_exp_i \
#  AS_030_000_SYNC_0_sqmuxa_2 CLK_000_NE_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 VPA_D_i \
#  cpu_est_ns_0_1_1__n VMA_INT_i cpu_est_ns_0_2_1__n AS_030_i \
#  state_machine_un10_clk_000_d0_1_n a_i_19__n state_machine_un10_clk_000_d0_2_0_n \
#  DSACK1_INT_0_sqmuxa_i state_machine_un10_clk_000_d0_3_n a_i_16__n \
#  state_machine_clk_000_n_sync_2_1_0__n a_i_18__n \
#  state_machine_clk_000_n_sync_2_2_0__n nEXP_SPACE_i \
#  state_machine_clk_000_p_sync_3_1_0__n RW_i N_167_1_0 CLK_000_D3_i un19_fpu_cs_1 \
#  CLK_000_D2_i un19_fpu_cs_2 CLK_000_D0_i un19_fpu_cs_3 cpu_est_i_3__n un19_fpu_cs_4 \
#  cpu_est_i_0__n un19_fpu_cs_5 cpu_est_i_1__n un19_fpu_cs_6 \
#  state_machine_un10_clk_000_ne_1_i_n DS_000_ENABLE_0_sqmuxa_1 CLK_000_D1_i \
#  state_machine_un10_clk_000_ne_1_0_n state_machine_un5_clk_000_d0_2_i_0_n \
#  dsack1_int_0_un3_n cpu_est_i_2__n dsack1_int_0_un1_n DS_000_DMA_1_sqmuxa_1_i \
#  dsack1_int_0_un0_n state_machine_un8_bgack_030_int_i_n bgack_030_int_0_un3_n \
#  CLK_030_i bgack_030_int_0_un1_n UDS_000_i bgack_030_int_0_un0_n LDS_000_i \
#  cpu_estse_0_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_0_un1_n RW_000_i \
#  cpu_estse_0_un0_n state_machine_un24_bgack_030_int_i_n vma_int_0_un3_n \
#  AS_000_DMA_i vma_int_0_un1_n BGACK_030_INT_i vma_int_0_un0_n AS_000_i \
#  ipl_030_0_0__un3_n N_90_i ipl_030_0_0__un1_n BGACK_030_INT_D_i ipl_030_0_0__un0_n \
#  N_89_i ipl_030_0_1__un3_n AS_030_000_SYNC_0_sqmuxa_i ipl_030_0_1__un1_n \
#  sm_amiga_i_7__n ipl_030_0_1__un0_n CLK_OUT_NE_i ipl_030_0_2__un3_n sm_amiga_i_0__n \
#  ipl_030_0_2__un1_n sm_amiga_i_1__n ipl_030_0_2__un0_n a_i_30__n cpu_estse_2_un3_n \
#  a_i_31__n cpu_estse_2_un1_n a_i_28__n cpu_estse_2_un0_n a_i_29__n \
#  as_000_dma_0_un3_n a_i_26__n as_000_dma_0_un1_n a_i_27__n as_000_dma_0_un0_n \
#  a_i_24__n ds_000_dma_0_un3_n a_i_25__n ds_000_dma_0_un1_n RST_i ds_000_dma_0_un0_n \
#  rw_000_dma_0_un3_n CLK_OUT_PRE_i rw_000_dma_0_un1_n CLK_OUT_PRE_50_D_i \
#  rw_000_dma_0_un0_n AS_030_c clk_030_h_0_un3_n clk_030_h_0_un1_n AS_000_c \
#  clk_030_h_0_un0_n cpu_estse_1_un3_n RW_000_c cpu_estse_1_un1_n cpu_estse_1_un0_n \
#  DS_030_c rw_000_int_0_un3_n rw_000_int_0_un1_n UDS_000_c rw_000_int_0_un0_n \
#  as_000_int_0_un3_n LDS_000_c as_000_int_0_un1_n as_000_int_0_un0_n size_c_0__n \
#  as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n size_c_1__n \
#  as_030_000_sync_0_un0_n
.model bus68030
.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \
A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \
A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \
A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF \
AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF \
DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF amiga_bus_enable_int_0_un3_n.BLIF \
a_c_16__n.BLIF amiga_bus_enable_int_0_un1_n.BLIF \
amiga_bus_enable_int_0_un0_n.BLIF a_c_17__n.BLIF bg_000_0_un3_n.BLIF \
bg_000_0_un1_n.BLIF a_c_18__n.BLIF bg_000_0_un0_n.BLIF \
inst_BGACK_030_INTreg.BLIF lds_000_int_0_un3_n.BLIF vcc_n_n.BLIF \
a_c_19__n.BLIF lds_000_int_0_un1_n.BLIF inst_avec_expreg.BLIF \
lds_000_int_0_un0_n.BLIF inst_VMA_INTreg.BLIF a_c_20__n.BLIF \
ds_000_enable_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_INTreg.BLIF \
ds_000_enable_0_un1_n.BLIF inst_CLK_OUT_NEreg.BLIF a_c_21__n.BLIF \
ds_000_enable_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF uds_000_int_0_un3_n.BLIF \
inst_BGACK_030_INT_D.BLIF a_c_22__n.BLIF uds_000_int_0_un1_n.BLIF \
inst_AS_000_DMA.BLIF uds_000_int_0_un0_n.BLIF inst_VPA_D.BLIF a_c_23__n.BLIF \
inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_OUT_PRE.BLIF a_c_24__n.BLIF \
inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF a_c_25__n.BLIF \
inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF a_c_26__n.BLIF \
inst_CLK_000_D2.BLIF inst_CLK_000_D3.BLIF a_c_27__n.BLIF inst_CLK_000_NE.BLIF \
gnd_n_n.BLIF a_c_28__n.BLIF inst_CLK_OUT_PRE_D.BLIF CLK_000_P_SYNC_9_.BLIF \
a_c_29__n.BLIF CLK_000_N_SYNC_11_.BLIF inst_AS_000_INT.BLIF a_c_30__n.BLIF \
SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF a_c_31__n.BLIF SM_AMIGA_1_.BLIF \
SM_AMIGA_0_.BLIF A0_c.BLIF SM_AMIGA_4_.BLIF inst_RW_000_INT.BLIF \
nEXP_SPACE_c.BLIF inst_DSACK1_INT.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \
BG_030_c.BLIF inst_CLK_030_H.BLIF inst_RW_000_DMA.BLIF BG_000DFFSHreg.BLIF \
un1_LDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF \
BGACK_000_c.BLIF un1_UDS_000_INT.BLIF inst_UDS_000_INT.BLIF CLK_030_c.BLIF \
CLK_000_c.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF CLK_OSZI_c.BLIF \
SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF CLK_000_N_SYNC_0_.BLIF CLK_OUT_INTreg.BLIF \
CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF \
IPL_030DFFSH_0_reg.BLIF CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF \
IPL_030DFFSH_1_reg.BLIF CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF \
IPL_030DFFSH_2_reg.BLIF CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF \
ipl_c_0__n.BLIF CLK_000_N_SYNC_10_.BLIF CLK_000_P_SYNC_0_.BLIF ipl_c_1__n.BLIF \
CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF ipl_c_2__n.BLIF \
CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF DSACK1_c.BLIF \
CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF DTACK_c.BLIF \
CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \
un1_as_030.BLIF un19_fpu_cs.BLIF state_machine_un10_bg_030_n.BLIF \
SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF RST_c.BLIF SM_AMIGA_2_.BLIF \
RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF \
AMIGA_BUS_DATA_DIR_c.BLIF SM_AMIGA_0_sqmuxa_i.BLIF \
DS_000_ENABLE_0_sqmuxa_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_i.BLIF \
state_machine_un10_clk_000_ne_i_n.BLIF state_machine_un4_clk_000_ne_i_n.BLIF \
CLK_OUT_PRE_25_0.BLIF state_machine_un6_clk_000_ne_i_n.BLIF N_97_i.BLIF \
sm_amiga_ns_0_4__n.BLIF N_99_i.BLIF N_98_i.BLIF sm_amiga_ns_0_5__n.BLIF \
N_86_i.BLIF state_machine_un6_clk_000_p_sync_i_n.BLIF \
state_machine_un6_bgack_000_0_n.BLIF N_167_i.BLIF cpu_est_0_.BLIF N_166_i.BLIF \
cpu_est_1_.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_2_.BLIF N_162_i.BLIF \
cpu_est_3_reg.BLIF N_161_i.BLIF cpu_estse.BLIF N_152_i.BLIF \
state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un5_clk_000_d0_i_n.BLIF \
state_machine_un12_clk_000_d0_0_n.BLIF N_198.BLIF cpu_est_ns_0_1__n.BLIF \
N_207.BLIF N_156_i.BLIF SM_AMIGA_0_sqmuxa.BLIF N_155_i.BLIF N_89.BLIF \
N_163_i.BLIF N_90.BLIF state_machine_un5_clk_000_d0_1_i_n.BLIF \
state_machine_un8_bg_030_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \
N_91.BLIF N_159_i.BLIF N_92.BLIF N_160_i.BLIF N_87.BLIF cpu_est_ns_0_2__n.BLIF \
N_94.BLIF state_machine_un10_bgack_030_int_0_n.BLIF N_95.BLIF \
state_machine_ds_000_dma_3_0_n.BLIF N_96.BLIF \
state_machine_size_dma_4_0_0__n.BLIF N_100.BLIF \
state_machine_size_dma_4_0_1__n.BLIF N_101.BLIF CLK_030_H_i.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_030_H_1_sqmuxa_i.BLIF N_85.BLIF \
state_machine_clk_030_h_2_f1_0_n.BLIF DSACK1_INT_0_sqmuxa.BLIF \
un3_dtack_i.BLIF AS_030_000_SYNC_0_sqmuxa.BLIF \
state_machine_un5_bgack_030_int_d_i_n.BLIF un1_bgack_030_int_d.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \
state_machine_un3_bgack_030_int_d_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \
AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF state_machine_rw_000_int_3_0_n.BLIF \
N_84.BLIF N_66_0.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF N_91_i.BLIF N_93.BLIF \
N_93_i.BLIF N_66.BLIF state_machine_rw_000_int_3_n.BLIF AS_030_000_SYNC_i.BLIF \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF N_84_0.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \
AS_030_000_SYNC_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF \
AS_000_INT_1_sqmuxa.BLIF state_machine_un3_bgack_030_int_d_i_n.BLIF \
state_machine_un8_bgack_030_int_n.BLIF un1_bgack_030_int_d_0.BLIF N_167_1.BLIF \
N_87_0.BLIF state_machine_un10_bgack_030_int_n.BLIF N_85_0.BLIF \
CLK_030_H_1_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i.BLIF \
AS_000_DMA_1_sqmuxa.BLIF N_92_i.BLIF DS_000_DMA_1_sqmuxa.BLIF \
DS_000_DMA_1_sqmuxa_1.BLIF N_100_i.BLIF \
state_machine_un24_bgack_030_int_n.BLIF N_101_i.BLIF \
state_machine_clk_030_h_2_n.BLIF sm_amiga_ns_0_6__n.BLIF \
state_machine_clk_030_h_2_f1_n.BLIF N_95_i.BLIF \
state_machine_un31_bgack_030_int_n.BLIF N_96_i.BLIF \
state_machine_ds_000_dma_3_n.BLIF sm_amiga_ns_0_3__n.BLIF cpu_est_ns_2__n.BLIF \
N_94_i.BLIF N_160.BLIF sm_amiga_ns_0_2__n.BLIF N_159.BLIF \
sm_amiga_ns_0_0__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF BG_030_c_i.BLIF \
state_machine_un5_clk_000_d0_1_n.BLIF state_machine_un8_bg_030_i_n.BLIF \
N_163.BLIF state_machine_un10_bg_030_0_n.BLIF N_155.BLIF LDS_000_INT_i.BLIF \
N_156.BLIF un1_LDS_000_INT_0.BLIF cpu_est_ns_1__n.BLIF UDS_000_INT_i.BLIF \
state_machine_un12_clk_000_d0_n.BLIF un1_UDS_000_INT_0.BLIF \
state_machine_un6_clk_000_p_sync_n.BLIF state_machine_un7_ds_030_i_n.BLIF \
state_machine_un10_clk_000_d0_n.BLIF A0_c_i.BLIF \
state_machine_un5_clk_000_d0_n.BLIF size_c_i_1__n.BLIF N_161.BLIF \
un1_bgack_030_int_d_0_1.BLIF state_machine_un10_clk_000_ne_1_n.BLIF \
N_84_0_1.BLIF N_162.BLIF N_84_0_2.BLIF state_machine_un5_clk_000_d0_2_n.BLIF \
un3_dtack_i_1.BLIF N_166.BLIF cpu_est_ns_0_1_2__n.BLIF N_167.BLIF N_198_1.BLIF \
DSACK1_INT_1_sqmuxa.BLIF N_198_2.BLIF state_machine_un6_bgack_000_n.BLIF \
N_207_1.BLIF DS_000_ENABLE_0_sqmuxa.BLIF N_207_2.BLIF \
state_machine_un10_clk_000_ne_n.BLIF N_207_3.BLIF N_86.BLIF N_207_4.BLIF \
state_machine_un6_clk_000_ne_n.BLIF N_207_5.BLIF N_98.BLIF N_207_6.BLIF \
N_99.BLIF state_machine_un7_ds_030_i_1_n.BLIF N_97.BLIF \
state_machine_un8_bg_030_1_n.BLIF state_machine_un4_clk_000_ne_n.BLIF \
state_machine_un8_bg_030_2_n.BLIF un19_fpu_cs_i.BLIF \
DSACK1_INT_0_sqmuxa_1.BLIF DTACK_i.BLIF AS_030_000_SYNC_0_sqmuxa_1_0.BLIF \
avec_exp_i.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF CLK_000_NE_i.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0.BLIF VPA_D_i.BLIF cpu_est_ns_0_1_1__n.BLIF \
VMA_INT_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_030_i.BLIF \
state_machine_un10_clk_000_d0_1_n.BLIF a_i_19__n.BLIF \
state_machine_un10_clk_000_d0_2_0_n.BLIF DSACK1_INT_0_sqmuxa_i.BLIF \
state_machine_un10_clk_000_d0_3_n.BLIF a_i_16__n.BLIF \
state_machine_clk_000_n_sync_2_1_0__n.BLIF a_i_18__n.BLIF \
state_machine_clk_000_n_sync_2_2_0__n.BLIF nEXP_SPACE_i.BLIF \
state_machine_clk_000_p_sync_3_1_0__n.BLIF RW_i.BLIF N_167_1_0.BLIF \
CLK_000_D3_i.BLIF un19_fpu_cs_1.BLIF CLK_000_D2_i.BLIF un19_fpu_cs_2.BLIF \
CLK_000_D0_i.BLIF un19_fpu_cs_3.BLIF cpu_est_i_3__n.BLIF un19_fpu_cs_4.BLIF \
cpu_est_i_0__n.BLIF un19_fpu_cs_5.BLIF cpu_est_i_1__n.BLIF un19_fpu_cs_6.BLIF \
state_machine_un10_clk_000_ne_1_i_n.BLIF DS_000_ENABLE_0_sqmuxa_1.BLIF \
CLK_000_D1_i.BLIF state_machine_un10_clk_000_ne_1_0_n.BLIF \
state_machine_un5_clk_000_d0_2_i_0_n.BLIF dsack1_int_0_un3_n.BLIF \
cpu_est_i_2__n.BLIF dsack1_int_0_un1_n.BLIF DS_000_DMA_1_sqmuxa_1_i.BLIF \
dsack1_int_0_un0_n.BLIF state_machine_un8_bgack_030_int_i_n.BLIF \
bgack_030_int_0_un3_n.BLIF CLK_030_i.BLIF bgack_030_int_0_un1_n.BLIF \
UDS_000_i.BLIF bgack_030_int_0_un0_n.BLIF LDS_000_i.BLIF \
cpu_estse_0_un3_n.BLIF state_machine_un31_bgack_030_int_i_n.BLIF \
cpu_estse_0_un1_n.BLIF RW_000_i.BLIF cpu_estse_0_un0_n.BLIF \
state_machine_un24_bgack_030_int_i_n.BLIF vma_int_0_un3_n.BLIF \
AS_000_DMA_i.BLIF vma_int_0_un1_n.BLIF BGACK_030_INT_i.BLIF \
vma_int_0_un0_n.BLIF AS_000_i.BLIF ipl_030_0_0__un3_n.BLIF N_90_i.BLIF \
ipl_030_0_0__un1_n.BLIF BGACK_030_INT_D_i.BLIF ipl_030_0_0__un0_n.BLIF \
N_89_i.BLIF ipl_030_0_1__un3_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF \
ipl_030_0_1__un1_n.BLIF sm_amiga_i_7__n.BLIF ipl_030_0_1__un0_n.BLIF \
CLK_OUT_NE_i.BLIF ipl_030_0_2__un3_n.BLIF sm_amiga_i_0__n.BLIF \
ipl_030_0_2__un1_n.BLIF sm_amiga_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF \
a_i_30__n.BLIF cpu_estse_2_un3_n.BLIF a_i_31__n.BLIF cpu_estse_2_un1_n.BLIF \
a_i_28__n.BLIF cpu_estse_2_un0_n.BLIF a_i_29__n.BLIF as_000_dma_0_un3_n.BLIF \
a_i_26__n.BLIF as_000_dma_0_un1_n.BLIF a_i_27__n.BLIF as_000_dma_0_un0_n.BLIF \
a_i_24__n.BLIF ds_000_dma_0_un3_n.BLIF a_i_25__n.BLIF ds_000_dma_0_un1_n.BLIF \
RST_i.BLIF ds_000_dma_0_un0_n.BLIF rw_000_dma_0_un3_n.BLIF CLK_OUT_PRE_i.BLIF \
rw_000_dma_0_un1_n.BLIF CLK_OUT_PRE_50_D_i.BLIF rw_000_dma_0_un0_n.BLIF \
AS_030_c.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un1_n.BLIF AS_000_c.BLIF \
clk_030_h_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF RW_000_c.BLIF \
cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF DS_030_c.BLIF \
rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF UDS_000_c.BLIF \
rw_000_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF LDS_000_c.BLIF \
as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF size_c_0__n.BLIF \
as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF size_c_1__n.BLIF \
as_030_000_sync_0_un0_n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \
DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF
.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \
AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \
cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C \
cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_7_.D \
SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \
SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \
SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \
SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \
SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_000_P_SYNC_2_.D \
CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_2_.AR CLK_000_P_SYNC_3_.D \
CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_3_.AR CLK_000_P_SYNC_4_.D \
CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_4_.AR CLK_000_P_SYNC_5_.D \
CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_5_.AR CLK_000_P_SYNC_6_.D \
CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_6_.AR CLK_000_P_SYNC_7_.D \
CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_7_.AR CLK_000_P_SYNC_8_.D \
CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_8_.AR CLK_000_P_SYNC_9_.D \
CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_9_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C \
SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D \
IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \
IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \
IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP CLK_000_N_SYNC_0_.D \
CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_0_.AR CLK_000_N_SYNC_1_.D \
CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_1_.AR CLK_000_N_SYNC_2_.D \
CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_2_.AR CLK_000_N_SYNC_3_.D \
CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_3_.AR CLK_000_N_SYNC_4_.D \
CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_4_.AR CLK_000_N_SYNC_5_.D \
CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_5_.AR CLK_000_N_SYNC_6_.D \
CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_6_.AR CLK_000_N_SYNC_7_.D \
CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_7_.AR CLK_000_N_SYNC_8_.D \
CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_8_.AR CLK_000_N_SYNC_9_.D \
CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_9_.AR CLK_000_N_SYNC_10_.D \
CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_10_.AR CLK_000_N_SYNC_11_.D \
CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_11_.AR CLK_000_P_SYNC_0_.D \
CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_0_.AR CLK_000_P_SYNC_1_.D \
CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_1_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C \
inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \
inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \
inst_CLK_OUT_PRE_25.AR inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
inst_AS_030_000_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \
inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_AS_000_INT.D \
inst_AS_000_INT.C inst_AS_000_INT.AP inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \
inst_DS_000_ENABLE.AR inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP \
inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_RW_000_INT.D \
inst_RW_000_INT.C inst_RW_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C \
inst_A0_DMA.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_RW_000_DMA.D \
inst_RW_000_DMA.C inst_RW_000_DMA.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \
inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \
inst_AMIGA_BUS_ENABLE_INTreg.D inst_AMIGA_BUS_ENABLE_INTreg.C \
inst_AMIGA_BUS_ENABLE_INTreg.AP inst_CLK_OUT_NEreg.D inst_CLK_OUT_NEreg.C \
inst_CLK_OUT_NEreg.AR inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \
inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D3.D \
inst_CLK_000_D3.C inst_CLK_000_D3.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP \
inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP \
inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR \
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_D.AR \
inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D \
inst_VPA_D.C inst_VPA_D.AP inst_avec_expreg.D inst_avec_expreg.C \
inst_avec_expreg.AR inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_000_NE.AR \
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \
RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \
DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ amiga_bus_enable_int_0_un3_n \
a_c_16__n amiga_bus_enable_int_0_un1_n amiga_bus_enable_int_0_un0_n a_c_17__n \
bg_000_0_un3_n bg_000_0_un1_n a_c_18__n bg_000_0_un0_n lds_000_int_0_un3_n \
vcc_n_n a_c_19__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_20__n \
ds_000_enable_0_un3_n ds_000_enable_0_un1_n a_c_21__n ds_000_enable_0_un0_n \
uds_000_int_0_un3_n a_c_22__n uds_000_int_0_un1_n uds_000_int_0_un0_n \
a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n gnd_n_n a_c_28__n a_c_29__n \
a_c_30__n a_c_31__n A0_c nEXP_SPACE_c state_machine_un3_clk_out_pre_50_n \
BG_030_c un1_LDS_000_INT BGACK_000_c un1_UDS_000_INT CLK_030_c CLK_000_c \
CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c DTACK_c \
un1_SM_AMIGA_0_sqmuxa_1 un1_as_030 un19_fpu_cs state_machine_un10_bg_030_n \
RST_c RW_c fc_c_0__n fc_c_1__n AMIGA_BUS_DATA_DIR_c SM_AMIGA_0_sqmuxa_i \
DS_000_ENABLE_0_sqmuxa_i un1_SM_AMIGA_0_sqmuxa_1_i \
state_machine_un10_clk_000_ne_i_n state_machine_un4_clk_000_ne_i_n \
state_machine_un6_clk_000_ne_i_n N_97_i sm_amiga_ns_0_4__n N_99_i N_98_i \
sm_amiga_ns_0_5__n N_86_i state_machine_un6_clk_000_p_sync_i_n \
state_machine_un6_bgack_000_0_n N_167_i N_166_i AMIGA_BUS_DATA_DIR_c_0 N_162_i \
N_161_i N_152_i state_machine_un10_clk_000_d0_i_n \
state_machine_un5_clk_000_d0_i_n state_machine_un12_clk_000_d0_0_n N_198 \
cpu_est_ns_0_1__n N_207 N_156_i SM_AMIGA_0_sqmuxa N_155_i N_89 N_163_i N_90 \
state_machine_un5_clk_000_d0_1_i_n state_machine_un8_bg_030_n \
state_machine_un10_clk_000_d0_2_i_n N_91 N_159_i N_92 N_160_i N_87 \
cpu_est_ns_0_2__n N_94 state_machine_un10_bgack_030_int_0_n N_95 \
state_machine_ds_000_dma_3_0_n N_96 state_machine_size_dma_4_0_0__n N_100 \
state_machine_size_dma_4_0_1__n N_101 CLK_030_H_i \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_030_H_1_sqmuxa_i N_85 \
state_machine_clk_030_h_2_f1_0_n DSACK1_INT_0_sqmuxa un3_dtack_i \
AS_030_000_SYNC_0_sqmuxa state_machine_un5_bgack_030_int_d_i_n \
un1_bgack_030_int_d AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \
state_machine_un3_bgack_030_int_d_n AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 \
AMIGA_BUS_ENABLE_INT_3_sqmuxa state_machine_rw_000_int_3_0_n N_84 N_66_0 \
AMIGA_BUS_ENABLE_INT_2_sqmuxa N_91_i N_93 N_93_i N_66 \
state_machine_rw_000_int_3_n AS_030_000_SYNC_i \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa N_84_0 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 \
AMIGA_BUS_ENABLE_INT_3_sqmuxa_i AS_030_000_SYNC_0_sqmuxa_1 \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i AS_000_INT_1_sqmuxa \
state_machine_un3_bgack_030_int_d_i_n state_machine_un8_bgack_030_int_n \
un1_bgack_030_int_d_0 N_167_1 N_87_0 state_machine_un10_bgack_030_int_n N_85_0 \
CLK_030_H_1_sqmuxa AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i AS_000_DMA_1_sqmuxa \
N_92_i DS_000_DMA_1_sqmuxa DS_000_DMA_1_sqmuxa_1 N_100_i \
state_machine_un24_bgack_030_int_n N_101_i state_machine_clk_030_h_2_n \
sm_amiga_ns_0_6__n state_machine_clk_030_h_2_f1_n N_95_i \
state_machine_un31_bgack_030_int_n N_96_i state_machine_ds_000_dma_3_n \
sm_amiga_ns_0_3__n cpu_est_ns_2__n N_94_i N_160 sm_amiga_ns_0_2__n N_159 \
sm_amiga_ns_0_0__n state_machine_un10_clk_000_d0_2_n BG_030_c_i \
state_machine_un5_clk_000_d0_1_n state_machine_un8_bg_030_i_n N_163 \
state_machine_un10_bg_030_0_n N_155 LDS_000_INT_i N_156 un1_LDS_000_INT_0 \
cpu_est_ns_1__n UDS_000_INT_i state_machine_un12_clk_000_d0_n \
un1_UDS_000_INT_0 state_machine_un6_clk_000_p_sync_n \
state_machine_un7_ds_030_i_n state_machine_un10_clk_000_d0_n A0_c_i \
state_machine_un5_clk_000_d0_n size_c_i_1__n N_161 un1_bgack_030_int_d_0_1 \
state_machine_un10_clk_000_ne_1_n N_84_0_1 N_162 N_84_0_2 \
state_machine_un5_clk_000_d0_2_n un3_dtack_i_1 N_166 cpu_est_ns_0_1_2__n N_167 \
N_198_1 DSACK1_INT_1_sqmuxa N_198_2 state_machine_un6_bgack_000_n N_207_1 \
DS_000_ENABLE_0_sqmuxa N_207_2 state_machine_un10_clk_000_ne_n N_207_3 N_86 \
N_207_4 state_machine_un6_clk_000_ne_n N_207_5 N_98 N_207_6 N_99 \
state_machine_un7_ds_030_i_1_n N_97 state_machine_un8_bg_030_1_n \
state_machine_un4_clk_000_ne_n state_machine_un8_bg_030_2_n un19_fpu_cs_i \
DSACK1_INT_0_sqmuxa_1 DTACK_i AS_030_000_SYNC_0_sqmuxa_1_0 avec_exp_i \
AS_030_000_SYNC_0_sqmuxa_2 CLK_000_NE_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0 \
VPA_D_i cpu_est_ns_0_1_1__n VMA_INT_i cpu_est_ns_0_2_1__n AS_030_i \
state_machine_un10_clk_000_d0_1_n a_i_19__n \
state_machine_un10_clk_000_d0_2_0_n DSACK1_INT_0_sqmuxa_i \
state_machine_un10_clk_000_d0_3_n a_i_16__n \
state_machine_clk_000_n_sync_2_1_0__n a_i_18__n \
state_machine_clk_000_n_sync_2_2_0__n nEXP_SPACE_i \
state_machine_clk_000_p_sync_3_1_0__n RW_i N_167_1_0 CLK_000_D3_i \
un19_fpu_cs_1 CLK_000_D2_i un19_fpu_cs_2 CLK_000_D0_i un19_fpu_cs_3 \
cpu_est_i_3__n un19_fpu_cs_4 cpu_est_i_0__n un19_fpu_cs_5 cpu_est_i_1__n \
un19_fpu_cs_6 state_machine_un10_clk_000_ne_1_i_n DS_000_ENABLE_0_sqmuxa_1 \
CLK_000_D1_i state_machine_un10_clk_000_ne_1_0_n \
state_machine_un5_clk_000_d0_2_i_0_n dsack1_int_0_un3_n cpu_est_i_2__n \
dsack1_int_0_un1_n DS_000_DMA_1_sqmuxa_1_i dsack1_int_0_un0_n \
state_machine_un8_bgack_030_int_i_n bgack_030_int_0_un3_n CLK_030_i \
bgack_030_int_0_un1_n UDS_000_i bgack_030_int_0_un0_n LDS_000_i \
cpu_estse_0_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_0_un1_n \
RW_000_i cpu_estse_0_un0_n state_machine_un24_bgack_030_int_i_n \
vma_int_0_un3_n AS_000_DMA_i vma_int_0_un1_n BGACK_030_INT_i vma_int_0_un0_n \
AS_000_i ipl_030_0_0__un3_n N_90_i ipl_030_0_0__un1_n BGACK_030_INT_D_i \
ipl_030_0_0__un0_n N_89_i ipl_030_0_1__un3_n AS_030_000_SYNC_0_sqmuxa_i \
ipl_030_0_1__un1_n sm_amiga_i_7__n ipl_030_0_1__un0_n CLK_OUT_NE_i \
ipl_030_0_2__un3_n sm_amiga_i_0__n ipl_030_0_2__un1_n sm_amiga_i_1__n \
ipl_030_0_2__un0_n a_i_30__n cpu_estse_2_un3_n a_i_31__n cpu_estse_2_un1_n \
a_i_28__n cpu_estse_2_un0_n a_i_29__n as_000_dma_0_un3_n a_i_26__n \
as_000_dma_0_un1_n a_i_27__n as_000_dma_0_un0_n a_i_24__n ds_000_dma_0_un3_n \
a_i_25__n ds_000_dma_0_un1_n RST_i ds_000_dma_0_un0_n rw_000_dma_0_un3_n \
CLK_OUT_PRE_i rw_000_dma_0_un1_n CLK_OUT_PRE_50_D_i rw_000_dma_0_un0_n \
AS_030_c clk_030_h_0_un3_n clk_030_h_0_un1_n AS_000_c clk_030_h_0_un0_n \
cpu_estse_1_un3_n RW_000_c cpu_estse_1_un1_n cpu_estse_1_un0_n DS_030_c \
rw_000_int_0_un3_n rw_000_int_0_un1_n UDS_000_c rw_000_int_0_un0_n \
as_000_int_0_un3_n LDS_000_c as_000_int_0_un1_n as_000_int_0_un0_n size_c_0__n \
as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n size_c_1__n \
as_030_000_sync_0_un0_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE \
LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE \
CIIN.OE CLK_OUT_PRE_25_0 cpu_estse
.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D
1- 1
-1 1
.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D
1- 1
-1 1
.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D
1- 1
-1 1
.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D
0 1
.names N_91_i.BLIF N_93_i.BLIF SM_AMIGA_6_.D
11 1
.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D
0 1
.names sm_amiga_ns_0_3__n.BLIF SM_AMIGA_4_.D
0 1
.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D
0 1
.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
0 1
.names sm_amiga_ns_0_6__n.BLIF SM_AMIGA_1_.D
0 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i.BLIF N_92_i.BLIF SM_AMIGA_0_.D
11 1
.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D
0 1
.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D
0 1
.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D
1- 1
-1 1
.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D
1- 1
-1 1
.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D
1- 1
-1 1
.names state_machine_clk_000_n_sync_2_1_0__n.BLIF \
state_machine_clk_000_n_sync_2_2_0__n.BLIF CLK_000_N_SYNC_0_.D
11 1
.names state_machine_clk_000_p_sync_3_1_0__n.BLIF \
state_machine_un6_clk_000_p_sync_n.BLIF CLK_000_P_SYNC_0_.D
11 1
.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D
1- 1
-1 1
.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \
inst_BGACK_030_INTreg.D
1- 1
-1 1
.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \
inst_AS_030_000_SYNC.D
1- 1
-1 1
.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D
1- 1
-1 1
.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D
1- 1
-1 1
.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D
1- 1
-1 1
.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF \
inst_DS_000_ENABLE.D
1- 1
-1 1
.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D
1- 1
-1 1
.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D
1- 1
-1 1
.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D
1- 1
-1 1
.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D
11 1
.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D
1- 1
-1 1
.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF inst_RW_000_DMA.D
1- 1
-1 1
.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D
1- 1
-1 1
.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D
1- 1
-1 1
.names amiga_bus_enable_int_0_un1_n.BLIF amiga_bus_enable_int_0_un0_n.BLIF \
inst_AMIGA_BUS_ENABLE_INTreg.D
1- 1
-1 1
.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_i.BLIF inst_CLK_OUT_NEreg.D
11 1
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
0 1
.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un3_n
0 1
.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un1_n
11 1
.names un1_bgack_030_int_d.BLIF amiga_bus_enable_int_0_un3_n.BLIF \
amiga_bus_enable_int_0_un0_n
11 1
.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n
0 1
.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n
11 1
.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
11 1
.names DS_030_c.BLIF lds_000_int_0_un3_n
0 1
.names vcc_n_n
 1
.names inst_LDS_000_INT.BLIF DS_030_c.BLIF lds_000_int_0_un1_n
11 1
.names state_machine_un7_ds_030_i_n.BLIF lds_000_int_0_un3_n.BLIF \
lds_000_int_0_un0_n
11 1
.names un1_as_030.BLIF ds_000_enable_0_un3_n
0 1
.names inst_DS_000_ENABLE.BLIF un1_as_030.BLIF ds_000_enable_0_un1_n
11 1
.names un1_SM_AMIGA_0_sqmuxa_1.BLIF ds_000_enable_0_un3_n.BLIF \
ds_000_enable_0_un0_n
11 1
.names DS_030_c.BLIF uds_000_int_0_un3_n
0 1
.names inst_UDS_000_INT.BLIF DS_030_c.BLIF uds_000_int_0_un1_n
11 1
.names A0_c.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
11 1
.names gnd_n_n
.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \
state_machine_un3_clk_out_pre_50_n
11 1
.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT
0 1
.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT
0 1
.names un1_SM_AMIGA_0_sqmuxa_1_i.BLIF un1_SM_AMIGA_0_sqmuxa_1
0 1
.names AS_030_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_i.BLIF un1_as_030
11 1
.names un19_fpu_cs_5.BLIF un19_fpu_cs_6.BLIF un19_fpu_cs
11 1
.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n
0 1
.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
0 1
.names SM_AMIGA_0_sqmuxa.BLIF SM_AMIGA_0_sqmuxa_i
0 1
.names DS_000_ENABLE_0_sqmuxa.BLIF DS_000_ENABLE_0_sqmuxa_i
0 1
.names DS_000_ENABLE_0_sqmuxa_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF \
un1_SM_AMIGA_0_sqmuxa_1_i
11 1
.names state_machine_un10_clk_000_ne_n.BLIF state_machine_un10_clk_000_ne_i_n
0 1
.names state_machine_un4_clk_000_ne_n.BLIF state_machine_un4_clk_000_ne_i_n
0 1
.names state_machine_un4_clk_000_ne_i_n.BLIF \
state_machine_un10_clk_000_ne_i_n.BLIF state_machine_un6_clk_000_ne_i_n
11 1
.names N_97.BLIF N_97_i
0 1
.names N_97_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF sm_amiga_ns_0_4__n
11 1
.names N_99.BLIF N_99_i
0 1
.names N_98.BLIF N_98_i
0 1
.names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_5__n
11 1
.names inst_CLK_000_NE.BLIF state_machine_un6_clk_000_ne_n.BLIF N_86_i
11 1
.names state_machine_un6_clk_000_p_sync_n.BLIF \
state_machine_un6_clk_000_p_sync_i_n
0 1
.names BGACK_000_c.BLIF state_machine_un6_clk_000_p_sync_i_n.BLIF \
state_machine_un6_bgack_000_0_n
11 1
.names N_167.BLIF N_167_i
0 1
.names N_166.BLIF N_166_i
0 1
.names N_166_i.BLIF N_167_i.BLIF AMIGA_BUS_DATA_DIR_c_0
11 1
.names N_162.BLIF N_162_i
0 1
.names N_161.BLIF N_161_i
0 1
.names N_161_i.BLIF N_162_i.BLIF N_152_i
11 1
.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n
0 1
.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_n
0 1
.names state_machine_un5_clk_000_d0_i_n.BLIF \
state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n
11 1
.names N_198_1.BLIF N_198_2.BLIF N_198
11 1
.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n
11 1
.names N_207_5.BLIF N_207_6.BLIF N_207
11 1
.names N_156.BLIF N_156_i
0 1
.names SM_AMIGA_4_.BLIF inst_avec_expreg.BLIF SM_AMIGA_0_sqmuxa
11 1
.names N_155.BLIF N_155_i
0 1
.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_89
11 1
.names N_163.BLIF N_163_i
0 1
.names SM_AMIGA_6_.BLIF inst_avec_expreg.BLIF N_90
11 1
.names state_machine_un5_clk_000_d0_1_n.BLIF \
state_machine_un5_clk_000_d0_1_i_n
0 1
.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF \
state_machine_un8_bg_030_n
11 1
.names state_machine_un10_clk_000_d0_2_n.BLIF \
state_machine_un10_clk_000_d0_2_i_n
0 1
.names N_84.BLIF SM_AMIGA_7_.BLIF N_91
11 1
.names N_159.BLIF N_159_i
0 1
.names SM_AMIGA_0_.BLIF inst_avec_expreg.BLIF N_92
11 1
.names N_160.BLIF N_160_i
0 1
.names N_87_0.BLIF N_87
0 1
.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \
cpu_est_ns_0_2__n
11 1
.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_94
11 1
.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n
11 1
.names inst_CLK_000_NE.BLIF SM_AMIGA_5_.BLIF N_95
11 1
.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \
state_machine_ds_000_dma_3_0_n
11 1
.names SM_AMIGA_4_.BLIF avec_exp_i.BLIF N_96
11 1
.names state_machine_un8_bgack_030_int_n.BLIF \
state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n
11 1
.names SM_AMIGA_2_.BLIF inst_avec_expreg.BLIF N_100
11 1
.names state_machine_un8_bgack_030_int_n.BLIF \
state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n
11 1
.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_101
11 1
.names inst_CLK_030_H.BLIF CLK_030_H_i
0 1
.names N_85.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1
11 1
.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i
0 1
.names N_85_0.BLIF N_85
0 1
.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF \
state_machine_clk_030_h_2_f1_0_n
11 1
.names DSACK1_INT_0_sqmuxa_1.BLIF SM_AMIGA_1_.BLIF DSACK1_INT_0_sqmuxa
11 1
.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i
11 1
.names AS_030_000_SYNC_0_sqmuxa_1_0.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF \
AS_030_000_SYNC_0_sqmuxa
11 1
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
state_machine_un5_bgack_030_int_d_i_n
11 1
.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d
0 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i
0 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF \
state_machine_un3_bgack_030_int_d_n
11 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i
0 1
.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1
11 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0
11 1
.names N_89_i.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \
AMIGA_BUS_ENABLE_INT_3_sqmuxa
11 1
.names RW_i.BLIF sm_amiga_i_7__n.BLIF state_machine_rw_000_int_3_0_n
11 1
.names N_84_0.BLIF N_84
0 1
.names N_90_i.BLIF sm_amiga_i_7__n.BLIF N_66_0
11 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0.BLIF \
state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa
11 1
.names N_91.BLIF N_91_i
0 1
.names N_87.BLIF sm_amiga_i_7__n.BLIF N_93
11 1
.names N_93.BLIF N_93_i
0 1
.names N_66_0.BLIF N_66
0 1
.names state_machine_rw_000_int_3_0_n.BLIF state_machine_rw_000_int_3_n
0 1
.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
0 1
.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa
0 1
.names N_84_0_1.BLIF N_84_0_2.BLIF N_84_0
11 1
.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_2
11 1
.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i
0 1
.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF \
AS_030_000_SYNC_0_sqmuxa_1
11 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i
0 1
.names AS_030_i.BLIF N_90_i.BLIF AS_000_INT_1_sqmuxa
11 1
.names state_machine_un3_bgack_030_int_d_n.BLIF \
state_machine_un3_bgack_030_int_d_i_n
0 1
.names N_167_1.BLIF state_machine_un10_bgack_030_int_n.BLIF \
state_machine_un8_bgack_030_int_n
11 1
.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \
un1_bgack_030_int_d_0
11 1
.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_167_1
11 1
.names SM_AMIGA_6_.BLIF avec_exp_i.BLIF N_87_0
11 1
.names state_machine_un10_bgack_030_int_0_n.BLIF \
state_machine_un10_bgack_030_int_n
0 1
.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_85_0
11 1
.names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa
11 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_i
0 1
.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF \
AS_000_DMA_1_sqmuxa
11 1
.names N_92.BLIF N_92_i
0 1
.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \
DS_000_DMA_1_sqmuxa
11 1
.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \
DS_000_DMA_1_sqmuxa_1
11 1
.names N_100.BLIF N_100_i
0 1
.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n
11 1
.names N_101.BLIF N_101_i
0 1
.names state_machine_clk_030_h_2_f1_n.BLIF \
state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n
11 1
.names N_100_i.BLIF N_101_i.BLIF sm_amiga_ns_0_6__n
11 1
.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n
0 1
.names N_95.BLIF N_95_i
0 1
.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n
11 1
.names N_96.BLIF N_96_i
0 1
.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n
0 1
.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_3__n
11 1
.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n
0 1
.names N_94.BLIF N_94_i
0 1
.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_160
11 1
.names N_90_i.BLIF N_94_i.BLIF sm_amiga_ns_0_2__n
11 1
.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_159
11 1
.names N_91_i.BLIF N_92_i.BLIF sm_amiga_ns_0_0__n
11 1
.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n
11 1
.names BG_030_c.BLIF BG_030_c_i
0 1
.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_1_n
11 1
.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n
0 1
.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_163
11 1
.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF \
state_machine_un10_bg_030_0_n
11 1
.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_155
11 1
.names inst_LDS_000_INT.BLIF LDS_000_INT_i
0 1
.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_156
11 1
.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0
11 1
.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n
0 1
.names inst_UDS_000_INT.BLIF UDS_000_INT_i
0 1
.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n
0 1
.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0
11 1
.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF \
state_machine_un6_clk_000_p_sync_n
11 1
.names state_machine_un7_ds_030_i_1_n.BLIF size_c_0__n.BLIF \
state_machine_un7_ds_030_i_n
11 1
.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF \
state_machine_un10_clk_000_d0_n
11 1
.names A0_c.BLIF A0_c_i
0 1
.names state_machine_un5_clk_000_d0_1_n.BLIF \
state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n
11 1
.names size_c_1__n.BLIF size_c_i_1__n
0 1
.names cpu_est_2_.BLIF state_machine_un10_clk_000_ne_1_i_n.BLIF N_161
11 1
.names state_machine_un3_bgack_030_int_d_i_n.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1
11 1
.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF \
state_machine_un10_clk_000_ne_1_n
11 1
.names AS_030_000_SYNC_i.BLIF CLK_000_D1_i.BLIF N_84_0_1
11 1
.names N_163.BLIF cpu_est_i_3__n.BLIF N_162
11 1
.names inst_CLK_000_D2.BLIF nEXP_SPACE_c.BLIF N_84_0_2
11 1
.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_2_n
11 1
.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1
11 1
.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_166
11 1
.names N_160_i.BLIF N_159_i.BLIF cpu_est_ns_0_1_2__n
11 1
.names N_167_1_0.BLIF nEXP_SPACE_i.BLIF N_167
11 1
.names a_c_20__n.BLIF a_c_21__n.BLIF N_198_1
11 1
.names AS_030_i.BLIF DSACK1_INT_0_sqmuxa_i.BLIF DSACK1_INT_1_sqmuxa
11 1
.names a_c_22__n.BLIF a_c_23__n.BLIF N_198_2
11 1
.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
0 1
.names a_i_24__n.BLIF a_i_25__n.BLIF N_207_1
11 1
.names DS_000_ENABLE_0_sqmuxa_1.BLIF inst_avec_expreg.BLIF \
DS_000_ENABLE_0_sqmuxa
11 1
.names a_i_26__n.BLIF a_i_27__n.BLIF N_207_2
11 1
.names state_machine_un10_clk_000_ne_1_0_n.BLIF VPA_D_i.BLIF \
state_machine_un10_clk_000_ne_n
11 1
.names a_i_28__n.BLIF a_i_29__n.BLIF N_207_3
11 1
.names N_86_i.BLIF N_86
0 1
.names a_i_30__n.BLIF a_i_31__n.BLIF N_207_4
11 1
.names state_machine_un6_clk_000_ne_i_n.BLIF state_machine_un6_clk_000_ne_n
0 1
.names N_207_1.BLIF N_207_2.BLIF N_207_5
11 1
.names SM_AMIGA_2_.BLIF avec_exp_i.BLIF N_98
11 1
.names N_207_3.BLIF N_207_4.BLIF N_207_6
11 1
.names N_86_i.BLIF SM_AMIGA_3_.BLIF N_99
11 1
.names size_c_i_1__n.BLIF A0_c_i.BLIF state_machine_un7_ds_030_i_1_n
11 1
.names N_86.BLIF SM_AMIGA_3_.BLIF N_97
11 1
.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n
11 1
.names DTACK_i.BLIF inst_VPA_D.BLIF state_machine_un4_clk_000_ne_n
11 1
.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n
11 1
.names un19_fpu_cs.BLIF un19_fpu_cs_i
0 1
.names inst_CLK_000_D1.BLIF CLK_OUT_NE_i.BLIF DSACK1_INT_0_sqmuxa_1
11 1
.names DTACK_c.BLIF DTACK_i
0 1
.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF \
AS_030_000_SYNC_0_sqmuxa_1_0
11 1
.names inst_avec_expreg.BLIF avec_exp_i
0 1
.names nEXP_SPACE_c.BLIF un19_fpu_cs_i.BLIF AS_030_000_SYNC_0_sqmuxa_2
11 1
.names inst_CLK_000_NE.BLIF CLK_000_NE_i
0 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF sm_amiga_i_7__n.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_1_0
11 1
.names inst_VPA_D.BLIF VPA_D_i
0 1
.names N_155_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_1__n
11 1
.names inst_VMA_INTreg.BLIF VMA_INT_i
0 1
.names N_163_i.BLIF state_machine_un5_clk_000_d0_1_i_n.BLIF \
cpu_est_ns_0_2_1__n
11 1
.names AS_030_c.BLIF AS_030_i
0 1
.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF \
state_machine_un10_clk_000_d0_1_n
11 1
.names a_c_19__n.BLIF a_i_19__n
0 1
.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF \
state_machine_un10_clk_000_d0_2_0_n
11 1
.names DSACK1_INT_0_sqmuxa.BLIF DSACK1_INT_0_sqmuxa_i
0 1
.names state_machine_un10_clk_000_d0_1_n.BLIF \
state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n
11 1
.names a_c_16__n.BLIF a_i_16__n
0 1
.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF \
state_machine_clk_000_n_sync_2_1_0__n
11 1
.names a_c_18__n.BLIF a_i_18__n
0 1
.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.BLIF \
state_machine_clk_000_n_sync_2_2_0__n
11 1
.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
0 1
.names CLK_000_D2_i.BLIF CLK_000_D3_i.BLIF \
state_machine_clk_000_p_sync_3_1_0__n
11 1
.names RW_c.BLIF RW_i
0 1
.names N_167_1.BLIF RW_c.BLIF N_167_1_0
11 1
.names inst_CLK_000_D3.BLIF CLK_000_D3_i
0 1
.names AS_030_i.BLIF a_c_17__n.BLIF un19_fpu_cs_1
11 1
.names inst_CLK_000_D2.BLIF CLK_000_D2_i
0 1
.names a_i_16__n.BLIF a_i_18__n.BLIF un19_fpu_cs_2
11 1
.names inst_CLK_000_D0.BLIF CLK_000_D0_i
0 1
.names a_i_19__n.BLIF BGACK_000_c.BLIF un19_fpu_cs_3
11 1
.names cpu_est_3_reg.BLIF cpu_est_i_3__n
0 1
.names fc_c_0__n.BLIF fc_c_1__n.BLIF un19_fpu_cs_4
11 1
.names cpu_est_0_.BLIF cpu_est_i_0__n
0 1
.names un19_fpu_cs_1.BLIF un19_fpu_cs_2.BLIF un19_fpu_cs_5
11 1
.names cpu_est_1_.BLIF cpu_est_i_1__n
0 1
.names un19_fpu_cs_3.BLIF un19_fpu_cs_4.BLIF un19_fpu_cs_6
11 1
.names state_machine_un10_clk_000_ne_1_n.BLIF \
state_machine_un10_clk_000_ne_1_i_n
0 1
.names RW_c.BLIF SM_AMIGA_6_.BLIF DS_000_ENABLE_0_sqmuxa_1
11 1
.names inst_CLK_000_D1.BLIF CLK_000_D1_i
0 1
.names state_machine_un10_clk_000_ne_1_n.BLIF VMA_INT_i.BLIF \
state_machine_un10_clk_000_ne_1_0_n
11 1
.names state_machine_un5_clk_000_d0_2_n.BLIF \
state_machine_un5_clk_000_d0_2_i_0_n
0 1
.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n
0 1
.names cpu_est_2_.BLIF cpu_est_i_2__n
0 1
.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n
11 1
.names DS_000_DMA_1_sqmuxa_1.BLIF DS_000_DMA_1_sqmuxa_1_i
0 1
.names DSACK1_INT_0_sqmuxa_i.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
11 1
.names state_machine_un8_bgack_030_int_n.BLIF \
state_machine_un8_bgack_030_int_i_n
0 1
.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
0 1
.names CLK_030_c.BLIF CLK_030_i
0 1
.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \
bgack_030_int_0_un1_n
11 1
.names UDS_000_c.BLIF UDS_000_i
0 1
.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \
bgack_030_int_0_un0_n
11 1
.names LDS_000_c.BLIF LDS_000_i
0 1
.names inst_avec_expreg.BLIF cpu_estse_0_un3_n
0 1
.names state_machine_un31_bgack_030_int_n.BLIF \
state_machine_un31_bgack_030_int_i_n
0 1
.names cpu_est_ns_1__n.BLIF inst_avec_expreg.BLIF cpu_estse_0_un1_n
11 1
.names RW_000_c.BLIF RW_000_i
0 1
.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n
11 1
.names state_machine_un24_bgack_030_int_n.BLIF \
state_machine_un24_bgack_030_int_i_n
0 1
.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n
0 1
.names inst_AS_000_DMA.BLIF AS_000_DMA_i
0 1
.names state_machine_un5_clk_000_d0_2_i_0_n.BLIF \
state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n
11 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
0 1
.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
11 1
.names AS_000_c.BLIF AS_000_i
0 1
.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_0__un3_n
0 1
.names N_90.BLIF N_90_i
0 1
.names ipl_c_0__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF \
ipl_030_0_0__un1_n
11 1
.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i
0 1
.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
11 1
.names N_89.BLIF N_89_i
0 1
.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_1__un3_n
0 1
.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i
0 1
.names ipl_c_1__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF \
ipl_030_0_1__un1_n
11 1
.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
0 1
.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
11 1
.names inst_CLK_OUT_NEreg.BLIF CLK_OUT_NE_i
0 1
.names state_machine_un6_clk_000_p_sync_n.BLIF ipl_030_0_2__un3_n
0 1
.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
0 1
.names ipl_c_2__n.BLIF state_machine_un6_clk_000_p_sync_n.BLIF \
ipl_030_0_2__un1_n
11 1
.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
0 1
.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
11 1
.names a_c_30__n.BLIF a_i_30__n
0 1
.names inst_avec_expreg.BLIF cpu_estse_2_un3_n
0 1
.names a_c_31__n.BLIF a_i_31__n
0 1
.names N_152_i.BLIF inst_avec_expreg.BLIF cpu_estse_2_un1_n
11 1
.names a_c_28__n.BLIF a_i_28__n
0 1
.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n
11 1
.names a_c_29__n.BLIF a_i_29__n
0 1
.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n
0 1
.names a_c_26__n.BLIF a_i_26__n
0 1
.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n
11 1
.names a_c_27__n.BLIF a_i_27__n
0 1
.names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF \
as_000_dma_0_un0_n
11 1
.names a_c_24__n.BLIF a_i_24__n
0 1
.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n
0 1
.names a_c_25__n.BLIF a_i_25__n
0 1
.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n
11 1
.names RST_c.BLIF RST_i
0 1
.names state_machine_ds_000_dma_3_n.BLIF ds_000_dma_0_un3_n.BLIF \
ds_000_dma_0_un0_n
11 1
.names AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un3_n
0 1
.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i
0 1
.names inst_RW_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un1_n
11 1
.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i
0 1
.names DS_000_DMA_1_sqmuxa_1_i.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n
11 1
.names RST_c.BLIF clk_030_h_0_un3_n
0 1
.names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n
11 1
.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n
11 1
.names inst_avec_expreg.BLIF cpu_estse_1_un3_n
0 1
.names cpu_est_ns_2__n.BLIF inst_avec_expreg.BLIF cpu_estse_1_un1_n
11 1
.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n
11 1
.names N_66.BLIF rw_000_int_0_un3_n
0 1
.names state_machine_rw_000_int_3_n.BLIF N_66.BLIF rw_000_int_0_un1_n
11 1
.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n
11 1
.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
0 1
.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n
11 1
.names N_90_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
11 1
.names AS_030_000_SYNC_0_sqmuxa_1.BLIF as_030_000_sync_0_un3_n
0 1
.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_0_sqmuxa_1.BLIF \
as_030_000_sync_0_un1_n
11 1
.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n
11 1
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
1 1
0 0
.names gnd_n_n.BLIF BERR
1 1
0 0
.names BG_000DFFSHreg.BLIF BG_000
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF BGACK_030
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_EXP
1 1
0 0
.names un19_fpu_cs_i.BLIF FPU_CS
1 1
0 0
.names vcc_n_n.BLIF AVEC
1 1
0 0
.names inst_avec_expreg.BLIF AVEC_EXP
1 1
0 0
.names cpu_est_3_reg.BLIF E
1 1
0 0
.names inst_VMA_INTreg.BLIF VMA
1 1
0 0
.names RESETDFFRHreg.BLIF RESET
1 1
0 0
.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF AMIGA_BUS_ENABLE
1 1
0 0
.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
1 1
0 0
.names inst_CLK_OUT_NEreg.BLIF AMIGA_BUS_ENABLE_LOW
1 1
0 0
.names N_198.BLIF CIIN
1 1
0 0
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
1 1
0 0
.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
1 1
0 0
.names cpu_estse.BLIF cpu_est_0_.D
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_0_.C
1 1
0 0
.names RST_i.BLIF cpu_est_0_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_1_.C
1 1
0 0
.names RST_i.BLIF cpu_est_1_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_2_.C
1 1
0 0
.names RST_i.BLIF cpu_est_2_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_3_reg.C
1 1
0 0
.names RST_i.BLIF cpu_est_3_reg.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_7_.AP
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_6_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_5_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_4_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_3_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_2_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_1_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_0_.AR
1 1
0 0
.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_2_.AR
1 1
0 0
.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_3_.AR
1 1
0 0
.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_4_.AR
1 1
0 0
.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_5_.AR
1 1
0 0
.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_6_.AR
1 1
0 0
.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_7_.AR
1 1
0 0
.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_8_.AR
1 1
0 0
.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_9_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C
1 1
0 0
.names RST_i.BLIF SIZE_DMA_0_.AP
1 1
0 0
.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C
1 1
0 0
.names RST_i.BLIF SIZE_DMA_1_.AP
1 1
0 0
.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C
1 1
0 0
.names RST_i.BLIF IPL_030DFFSH_0_reg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C
1 1
0 0
.names RST_i.BLIF IPL_030DFFSH_1_reg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C
1 1
0 0
.names RST_i.BLIF IPL_030DFFSH_2_reg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_0_.AR
1 1
0 0
.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_1_.AR
1 1
0 0
.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_2_.AR
1 1
0 0
.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_3_.AR
1 1
0 0
.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_4_.AR
1 1
0 0
.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_5_.AR
1 1
0 0
.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_6_.AR
1 1
0 0
.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_7_.AR
1 1
0 0
.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_8_.AR
1 1
0 0
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_9_.AR
1 1
0 0
.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_10_.AR
1 1
0 0
.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_11_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_0_.AR
1 1
0 0
.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_1_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
1 1
0 0
.names RST_i.BLIF inst_VMA_INTreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names RST_i.BLIF inst_BGACK_030_INTreg.AP
1 1
0 0
.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_25.AR
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names RST_i.BLIF inst_AS_030_000_SYNC.AP
1 1
0 0
.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C
1 1
0 0
.names RST_i.BLIF BG_000DFFSHreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_LDS_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_AS_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C
1 1
0 0
.names RST_i.BLIF inst_DS_000_ENABLE.AR
1 1
0 0
.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C
1 1
0 0
.names RST_i.BLIF inst_DSACK1_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_UDS_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_RW_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_RW_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_A0_DMA.C
1 1
0 0
.names RST_i.BLIF inst_A0_DMA.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C
1 1
0 0
.names RST_i.BLIF inst_RW_000_DMA.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C
1 1
0 0
.names RST_i.BLIF inst_DS_000_DMA.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
1 1
0 0
.names RST_i.BLIF inst_AS_000_DMA.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_INTreg.C
1 1
0 0
.names RST_i.BLIF inst_AMIGA_BUS_ENABLE_INTreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_NEreg.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_NEreg.AR
1 1
0 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D2.AP
1 1
0 0
.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE.AR
1 1
0 0
.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D3.AP
1 1
0 0
.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names RST_i.BLIF CLK_OUT_INTreg.AR
1 1
0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D1.AP
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
1 1
0 0
.names RST_i.BLIF inst_BGACK_030_INT_D.AP
1 1
0 0
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50_D.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR
1 1
0 0
.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_D.AR
1 1
0 0
.names CLK_000_c.BLIF inst_CLK_000_D0.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D0.AP
1 1
0 0
.names VPA.BLIF inst_VPA_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_VPA_D.C
1 1
0 0
.names RST_i.BLIF inst_VPA_D.AP
1 1
0 0
.names CLK_000_P_SYNC_9_.BLIF inst_avec_expreg.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_avec_expreg.C
1 1
0 0
.names RST_i.BLIF inst_avec_expreg.AR
1 1
0 0
.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_NE.AR
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_50.AR
1 1
0 0
.names vcc_n_n.BLIF RESETDFFRHreg.D
1 1
0 0
.names CLK_OSZI_c.BLIF RESETDFFRHreg.C
1 1
0 0
.names RST_i.BLIF RESETDFFRHreg.AR
1 1
0 0
.names SIZE_DMA_1_.BLIF SIZE_1_
1 1
0 0
.names inst_AS_000_DMA.BLIF AS_030
1 1
0 0
.names inst_AS_000_INT.BLIF AS_000
1 1
0 0
.names inst_RW_000_INT.BLIF RW_000
1 1
0 0
.names inst_DS_000_DMA.BLIF DS_030
1 1
0 0
.names un1_UDS_000_INT.BLIF UDS_000
1 1
0 0
.names un1_LDS_000_INT.BLIF LDS_000
1 1
0 0
.names inst_A0_DMA.BLIF A0
1 1
0 0
.names inst_DSACK1_INT.BLIF DSACK1
1 1
0 0
.names DSACK1_c.BLIF DTACK
1 1
0 0
.names inst_RW_000_DMA.BLIF RW
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_0_
1 1
0 0
.names A_16_.BLIF a_c_16__n
1 1
0 0
.names A_17_.BLIF a_c_17__n
1 1
0 0
.names A_18_.BLIF a_c_18__n
1 1
0 0
.names A_19_.BLIF a_c_19__n
1 1
0 0
.names A_20_.BLIF a_c_20__n
1 1
0 0
.names A_21_.BLIF a_c_21__n
1 1
0 0
.names A_22_.BLIF a_c_22__n
1 1
0 0
.names A_23_.BLIF a_c_23__n
1 1
0 0
.names A_24_.BLIF a_c_24__n
1 1
0 0
.names A_25_.BLIF a_c_25__n
1 1
0 0
.names A_26_.BLIF a_c_26__n
1 1
0 0
.names A_27_.BLIF a_c_27__n
1 1
0 0
.names A_28_.BLIF a_c_28__n
1 1
0 0
.names A_29_.BLIF a_c_29__n
1 1
0 0
.names A_30_.BLIF a_c_30__n
1 1
0 0
.names A_31_.BLIF a_c_31__n
1 1
0 0
.names A0.PIN.BLIF A0_c
1 1
0 0
.names nEXP_SPACE.BLIF nEXP_SPACE_c
1 1
0 0
.names BG_030.BLIF BG_030_c
1 1
0 0
.names BGACK_000.BLIF BGACK_000_c
1 1
0 0
.names CLK_030.BLIF CLK_030_c
1 1
0 0
.names CLK_000.BLIF CLK_000_c
1 1
0 0
.names CLK_OSZI.BLIF CLK_OSZI_c
1 1
0 0
.names IPL_0_.BLIF ipl_c_0__n
1 1
0 0
.names IPL_1_.BLIF ipl_c_1__n
1 1
0 0
.names IPL_2_.BLIF ipl_c_2__n
1 1
0 0
.names DSACK1.PIN.BLIF DSACK1_c
1 1
0 0
.names DTACK.PIN.BLIF DTACK_c
1 1
0 0
.names RST.BLIF RST_c
1 1
0 0
.names RW.PIN.BLIF RW_c
1 1
0 0
.names FC_0_.BLIF fc_c_0__n
1 1
0 0
.names FC_1_.BLIF fc_c_1__n
1 1
0 0
.names AS_030.PIN.BLIF AS_030_c
1 1
0 0
.names AS_000.PIN.BLIF AS_000_c
1 1
0 0
.names RW_000.PIN.BLIF RW_000_c
1 1
0 0
.names DS_030.PIN.BLIF DS_030_c
1 1
0 0
.names UDS_000.PIN.BLIF UDS_000_c
1 1
0 0
.names LDS_000.PIN.BLIF LDS_000_c
1 1
0 0
.names SIZE_0_.PIN.BLIF size_c_0__n
1 1
0 0
.names SIZE_1_.PIN.BLIF size_c_1__n
1 1
0 0
.names un3_dtack_i.BLIF AS_030.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF RW_000.OE
1 1
0 0
.names un3_dtack_i.BLIF DS_030.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
1 1
0 0
.names un3_dtack_i.BLIF SIZE_0_.OE
1 1
0 0
.names un3_dtack_i.BLIF SIZE_1_.OE
1 1
0 0
.names un3_dtack_i.BLIF A0.OE
1 1
0 0
.names nEXP_SPACE_c.BLIF DSACK1.OE
1 1
0 0
.names un3_dtack_i.BLIF DTACK.OE
1 1
0 0
.names BGACK_030_INT_i.BLIF RW.OE
1 1
0 0
.names un19_fpu_cs.BLIF BERR.OE
1 1
0 0
.names N_207.BLIF CIIN.OE
1 1
0 0
.names inst_CLK_OUT_PRE_25.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \
CLK_OUT_PRE_25_0
01 1
10 1
11 0
00 0
.names inst_avec_expreg.BLIF cpu_est_0_.BLIF cpu_estse
01 1
10 1
11 0
00 0
.end