mirror of https://github.com/kr239/68030tk.git
1384 lines
32 KiB
Plaintext
1384 lines
32 KiB
Plaintext
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
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#$ DATE Thu Sep 24 16:20:59 2015
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#$ MODULE 68030_tk
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#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \
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# IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 DS_030 UDS_000 LDS_000 A0 A1 \
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# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI IPL_030_1_ \
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# CLK_DIV_OUT IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E \
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# VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
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# AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_
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#$ NODES 84 inst_BGACK_030_INTreg cpu_est_3_reg inst_VMA_INTreg inst_RESET_OUTreg \
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# cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW \
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# inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC \
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# inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ \
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# SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT \
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# inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 \
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# inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE \
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# CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ \
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# inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg \
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# SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ \
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# RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ \
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# CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ \
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# CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ \
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# CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ \
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# pos_clk_un29_clk_000_ne_d0_i_n CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ \
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# CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ \
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# inst_RW_000_INT inst_RW_000_DMA inst_A0_DMA inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ \
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# SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ BG_000DFFreg IPL_030DFF_0_reg \
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# IPL_030DFF_1_reg IPL_030DFF_2_reg
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.model bus68030
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.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
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BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
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DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \
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A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
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A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \
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inst_BGACK_030_INTreg.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF \
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inst_RESET_OUTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \
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SM_AMIGA_5_.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
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inst_nEXP_SPACE_D0reg.BLIF inst_DS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF \
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inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF \
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CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF \
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inst_VPA_D.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \
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inst_CLK_OUT_PRE_D.BLIF inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF \
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inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \
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CLK_000_P_SYNC_9_.BLIF inst_CLK_000_NE.BLIF CLK_000_N_SYNC_11_.BLIF \
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cpu_est_2_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF SM_AMIGA_3_.BLIF \
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inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \
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inst_DSACK1_INTreg.BLIF SM_AMIGA_6_.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
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RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \
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RST_DLY_6_.BLIF RST_DLY_7_.BLIF CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.BLIF \
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CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF \
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CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.BLIF \
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CLK_000_P_SYNC_8_.BLIF CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.BLIF \
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CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.BLIF \
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pos_clk_un29_clk_000_ne_d0_i_n.BLIF CLK_000_N_SYNC_5_.BLIF \
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CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF \
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CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF inst_RW_000_INT.BLIF \
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inst_RW_000_DMA.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF \
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SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_i_7_.BLIF \
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BG_000DFFreg.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF \
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IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \
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DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
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SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
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.outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E \
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VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
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AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D \
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IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \
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IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \
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SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D \
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SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \
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cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \
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cpu_est_3_reg.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D \
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IPL_030DFF_1_reg.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C \
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CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \
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CLK_000_N_SYNC_11_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \
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RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C \
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RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \
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CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
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SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \
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CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \
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CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \
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CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \
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CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \
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CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \
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CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \
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CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \
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CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \
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CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \
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CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \
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CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \
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CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C inst_CLK_030_H.C inst_RESET_OUTreg.D \
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inst_RESET_OUTreg.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \
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inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \
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inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \
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inst_BGACK_030_INTreg.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
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inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
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inst_A0_DMA.D inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C \
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inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C \
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inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \
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inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \
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inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
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inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \
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inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
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inst_UDS_000_INT.D inst_UDS_000_INT.C inst_BGACK_030_INT_D.D \
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inst_BGACK_030_INT_D.C inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D \
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inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
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inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
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inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C \
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SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 BERR RW SIZE_0_ \
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pos_clk_un29_clk_000_ne_d0_i_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE \
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UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE \
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DSACK1.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 SM_AMIGA_3_.D.X1 \
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SM_AMIGA_3_.D.X2 RST_DLY_4_.D.X1 RST_DLY_4_.D.X2 RST_DLY_5_.D.X1 \
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RST_DLY_5_.D.X2 RST_DLY_6_.D.X1 RST_DLY_6_.D.X2 inst_CLK_030_H.D.X1 \
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inst_CLK_030_H.D.X2 SM_AMIGA_i_7_.D.X1 SM_AMIGA_i_7_.D.X2
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.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
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IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D
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1-00001- 1
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1-01101- 1
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1-10011- 1
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1-11111- 1
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1------1 1
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------11 1
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--1--0-1 1
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--0--1-1 1
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---10--1 1
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---01--1 1
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-0------ 1
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0100000- 0
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0101100- 0
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0110010- 0
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0111110- 0
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-11--0-0 0
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-10--1-0 0
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-1-10--0 0
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-1-01--0 0
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-1----00 0
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01-----0 0
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.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D
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0- 1
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-1 1
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10 0
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.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D
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0- 1
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-1 1
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10 0
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.names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D
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1- 1
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-0 1
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01 0
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.names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
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inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \
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SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D
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11010--0- 1
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1----01-1 1
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1-----10- 1
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-----1-1- 0
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----1-0-- 0
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---0--0-- 0
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--1---0-- 0
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-0----0-- 0
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------01- 0
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0-------- 0
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-------10 0
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.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
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SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
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101-1- 1
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11-0-1 1
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11--11 1
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---10- 0
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-00--- 0
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-0--0- 0
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-1---0 0
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0----- 0
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.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
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SM_AMIGA_4_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D
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1-0-11 1
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11-1-- 1
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11--1- 1
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---00- 0
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-01--- 0
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-0--0- 0
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0----- 0
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-0---0 0
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.names RST.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \
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cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF inst_CLK_000_PE.BLIF \
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cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_2_.BLIF \
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BERR.PIN.BLIF SM_AMIGA_2_.D
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110000--111-- 1
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1----10--11-- 1
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1------0---11 1
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1--------1-1- 1
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-----11----0- 0
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-------1-0--- 0
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-----0--0--0- 0
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----10-----0- 0
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---1-0-----0- 0
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--1--0-----0- 0
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-0---0-----0- 0
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----------00- 0
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---------0-0- 0
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0------------ 0
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---------0--0 0
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.names RST.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF \
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SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D
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11-01- 1
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1-01-1 1
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1--111 1
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--1-0- 0
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-0-0-- 0
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---00- 0
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---1-0 0
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0----- 0
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.names RST.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_0_.BLIF \
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SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D
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1-101- 1
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10-1-1 1
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-1-1-- 0
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---00- 0
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--00-- 0
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---1-0 0
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0----- 0
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.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
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inst_CLK_000_NE_D0.BLIF cpu_est_1_.D
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0--01 1
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010-1 1
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1-11- 1
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10--1 1
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--1-0 1
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-01-- 1
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0001- 0
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01111 0
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11-01 0
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110-- 0
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--0-0 0
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.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
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inst_CLK_000_NE_D0.BLIF cpu_est_2_.D
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-00-1 1
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11--1 1
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--11- 1
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---10 1
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0-10- 0
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-010- 0
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010-1 0
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---00 0
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.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
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IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D
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0-01100- 1
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0-11110- 1
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1-01101- 1
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1-11111- 1
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1-----01 1
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0-----11 1
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--1--0-1 1
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--0--1-1 1
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---1---1 1
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----1--1 1
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-0------ 1
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0100000- 0
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0110010- 0
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1100001- 0
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1110011- 0
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11----00 0
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01----10 0
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-11--0-0 0
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-10--1-0 0
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-1--0--0 0
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-1-0---0 0
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.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
|
|
IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_1_reg.D
|
|
0-10010- 1
|
|
0-11110- 1
|
|
1-10011- 1
|
|
1-11111- 1
|
|
1-----01 1
|
|
0-----11 1
|
|
--1----1 1
|
|
-----1-1 1
|
|
---10--1 1
|
|
---01--1 1
|
|
-0------ 1
|
|
0100000- 0
|
|
0101100- 0
|
|
1100001- 0
|
|
1101101- 0
|
|
11----00 0
|
|
01----10 0
|
|
-1-10--0 0
|
|
-1-01--0 0
|
|
-1---0-0 0
|
|
-10----0 0
|
|
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \
|
|
RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_0_.D
|
|
1-11111111 1
|
|
110------- 1
|
|
101------- 1
|
|
-00------- 0
|
|
-11-----0- 0
|
|
-11----0-- 0
|
|
-11---0--- 0
|
|
-11--0---- 0
|
|
-11-0----- 0
|
|
-110------ 0
|
|
0--------- 0
|
|
-11------0 0
|
|
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \
|
|
RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_1_.D
|
|
1--1111111 1
|
|
1110------ 1
|
|
1-01------ 1
|
|
10-1------ 1
|
|
-111----0- 0
|
|
-111---0-- 0
|
|
-111--0--- 0
|
|
-111-0---- 0
|
|
-1110----- 0
|
|
--00------ 0
|
|
-0-0------ 0
|
|
-111-----0 0
|
|
0--------- 0
|
|
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \
|
|
RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_2_.D
|
|
1---111111 1
|
|
11110----- 1
|
|
1--01----- 1
|
|
1-0-1----- 1
|
|
10--1----- 1
|
|
-1111---0- 0
|
|
-1111--0-- 0
|
|
-1111-0--- 0
|
|
-11110---- 0
|
|
-1111----0 0
|
|
---00----- 0
|
|
--0-0----- 0
|
|
-0--0----- 0
|
|
0--------- 0
|
|
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \
|
|
RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_3_.D
|
|
1----11111 1
|
|
111110---- 1
|
|
1---01---- 1
|
|
1--0-1---- 1
|
|
1-0--1---- 1
|
|
10---1---- 1
|
|
-11111--0- 0
|
|
-11111-0-- 0
|
|
-111110--- 0
|
|
-11111---0 0
|
|
----00---- 0
|
|
---0-0---- 0
|
|
--0--0---- 0
|
|
-0---0---- 0
|
|
0--------- 0
|
|
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \
|
|
RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_7_.D
|
|
111111111- 1
|
|
1--------1 1
|
|
0--------- 0
|
|
--------00 0
|
|
-------0-0 0
|
|
------0--0 0
|
|
-----0---0 0
|
|
----0----0 0
|
|
---0-----0 0
|
|
--0------0 0
|
|
-0-------0 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF \
|
|
inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D
|
|
10100 1
|
|
10010 1
|
|
--00- 0
|
|
--11- 0
|
|
-1--- 0
|
|
0---- 0
|
|
----1 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
|
|
inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D
|
|
101010 1
|
|
10-100 1
|
|
1001-0 1
|
|
--111- 0
|
|
---00- 0
|
|
--00-- 0
|
|
-1---- 0
|
|
0----- 0
|
|
-----1 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
SIZE_DMA_0_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_0_.D
|
|
-111-- 1
|
|
-0--1- 1
|
|
0----- 1
|
|
-0---1 1
|
|
10--00 0
|
|
11-0-- 0
|
|
110--- 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D
|
|
-111-- 1
|
|
-0--00 1
|
|
0----- 1
|
|
10--1- 0
|
|
11-0-- 0
|
|
110--- 0
|
|
10---1 0
|
|
.names inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF CLK_000_P_SYNC_0_.D
|
|
01 1
|
|
1- 0
|
|
-0 0
|
|
.names RST.BLIF inst_RESET_OUTreg.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF \
|
|
RST_DLY_1_.BLIF RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF \
|
|
RST_DLY_5_.BLIF RST_DLY_6_.BLIF RST_DLY_7_.BLIF inst_RESET_OUTreg.D
|
|
1-111111111 1
|
|
11--------- 1
|
|
0---------- 0
|
|
-0-------0- 0
|
|
-0------0-- 0
|
|
-0-----0--- 0
|
|
-0----0---- 0
|
|
-0---0----- 0
|
|
-0--0------ 0
|
|
-0-0------- 0
|
|
-00-------- 0
|
|
-0--------0 0
|
|
.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF SM_AMIGA_3_.BLIF \
|
|
inst_DS_000_ENABLE.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D
|
|
1-0-11- 1
|
|
10-1--- 1
|
|
11----1 1
|
|
-0-0-0- 0
|
|
-0-00-- 0
|
|
-010--- 0
|
|
-1---00 0
|
|
-1--0-0 0
|
|
-11---0 0
|
|
0------ 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
|
|
-1-1- 1
|
|
-10-- 1
|
|
0---- 1
|
|
-0--1 1
|
|
1110- 0
|
|
10--0 0
|
|
.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \
|
|
inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D
|
|
-0--1-- 1
|
|
-011--- 1
|
|
-0---0- 1
|
|
0------ 1
|
|
-1----1 1
|
|
10-001- 0
|
|
100-01- 0
|
|
11----0 0
|
|
.names RST.BLIF inst_DS_030_D0.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF \
|
|
SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D
|
|
-0-1100 1
|
|
--10--- 1
|
|
-11---- 1
|
|
0------ 1
|
|
10-1-1- 0
|
|
10-10-- 0
|
|
10-1--1 0
|
|
1-00--- 0
|
|
110---- 0
|
|
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \
|
|
AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
|
|
1-1-- 1
|
|
1--11 1
|
|
-0--- 1
|
|
-100- 0
|
|
-10-0 0
|
|
01--- 0
|
|
.names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
|
|
FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \
|
|
inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D
|
|
1-00101---1--- 1
|
|
----------1-1- 1
|
|
----------10-- 1
|
|
---------01--- 1
|
|
-------0--1--- 1
|
|
--------1----- 1
|
|
-0------------ 1
|
|
-------------0 1
|
|
-1----0101-101 0
|
|
-1---1-101-101 0
|
|
-1--0--101-101 0
|
|
-1-1---101-101 0
|
|
-11----101-101 0
|
|
01-----101-101 0
|
|
-1------0-0--1 0
|
|
.names RST.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF \
|
|
BERR.PIN.BLIF inst_AS_000_INT.D
|
|
-10-- 1
|
|
--01- 1
|
|
0---- 1
|
|
--0-0 1
|
|
10-01 0
|
|
1-1-- 0
|
|
.names CLK_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_CLK_OUT_PRE_D.BLIF \
|
|
inst_DSACK1_INTreg.BLIF CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF \
|
|
SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D
|
|
1--01-0-- 1
|
|
----100-- 1
|
|
1-10--0-- 1
|
|
1--0--0-0 1
|
|
----1--0- 1
|
|
--1--00-- 1
|
|
-----00-0 1
|
|
--1----0- 1
|
|
-0------- 1
|
|
-------00 1
|
|
-10-0---1 0
|
|
-1-1-1-1- 0
|
|
01---1-1- 0
|
|
-1----11- 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D
|
|
-111- 1
|
|
0---- 1
|
|
-0--1 1
|
|
11-0- 0
|
|
110-- 0
|
|
10--0 0
|
|
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
|
|
LDS_000.PIN.BLIF inst_AS_000_DMA.D
|
|
----00--- 1
|
|
----11--- 1
|
|
0--1----- 1
|
|
------1-- 1
|
|
--1------ 1
|
|
-0------- 1
|
|
-------11 1
|
|
-1001000- 0
|
|
110-1000- 0
|
|
-1000100- 0
|
|
110-0100- 0
|
|
-100100-0 0
|
|
110-100-0 0
|
|
-100010-0 0
|
|
110-010-0 0
|
|
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \
|
|
AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
|
|
inst_DS_000_DMA.D
|
|
1--1---1-0-- 1
|
|
----1--0-0-- 1
|
|
0---1----0-- 1
|
|
-----00----- 1
|
|
-----11----- 1
|
|
--------1--- 1
|
|
--1--------- 1
|
|
-0---------- 1
|
|
----------11 1
|
|
1100-1010-0- 0
|
|
1100-0110-0- 0
|
|
1100-1010--0 0
|
|
1100-0110--0 0
|
|
-10-01000-0- 0
|
|
-10-00100-0- 0
|
|
010-010-0-0- 0
|
|
010-001-0-0- 0
|
|
-10-01000--0 0
|
|
-10-00100--0 0
|
|
010-010-0--0 0
|
|
010-001-0--0 0
|
|
-10--10-010- 0
|
|
-10--01-010- 0
|
|
-10--10-01-0 0
|
|
-10--01-01-0 0
|
|
.names RST.BLIF DS_030.PIN.BLIF inst_DS_030_D0.D
|
|
0- 1
|
|
-1 1
|
|
10 0
|
|
.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D
|
|
0- 1
|
|
-1 1
|
|
10 0
|
|
.names nEXP_SPACE.BLIF RST.BLIF inst_nEXP_SPACE_D0reg.D
|
|
1- 1
|
|
-0 1
|
|
01 0
|
|
.names VPA.BLIF RST.BLIF inst_VPA_D.D
|
|
1- 1
|
|
-0 1
|
|
01 0
|
|
.names DTACK.BLIF RST.BLIF inst_DTACK_D0.D
|
|
1- 1
|
|
-0 1
|
|
01 0
|
|
.names BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF \
|
|
inst_CLK_000_D0.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
|
|
----01 1
|
|
---0-1 1
|
|
--0--1 1
|
|
-0---- 1
|
|
1----- 1
|
|
01111- 0
|
|
01---0 0
|
|
.names A1.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D
|
|
--1-1 1
|
|
1-0-- 1
|
|
--10- 1
|
|
-0--- 1
|
|
-1110 0
|
|
010-- 0
|
|
.names A1.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF \
|
|
inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
inst_AMIGA_BUS_ENABLE_DMA_LOW.D
|
|
--11- 1
|
|
0-0-- 1
|
|
--1-0 1
|
|
-0--- 1
|
|
-1101 0
|
|
110-- 0
|
|
.names RST.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \
|
|
cpu_est_1_.BLIF inst_VPA_D.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
|
|
cpu_est_2_.BLIF inst_VMA_INTreg.D
|
|
-0-01-1-1 1
|
|
--1----0- 1
|
|
--1--1--- 1
|
|
--10----- 1
|
|
--1-1---- 1
|
|
0-------- 1
|
|
-11------ 1
|
|
--1-----0 1
|
|
10-100-11 0
|
|
1-0---0-- 0
|
|
110------ 0
|
|
1-0-----0 0
|
|
1-0-0---- 0
|
|
1-01----- 0
|
|
.names RST.BLIF inst_DS_030_D0.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF \
|
|
A0.PIN.BLIF inst_UDS_000_INT.D
|
|
-0-11 1
|
|
--10- 1
|
|
-11-- 1
|
|
0---- 1
|
|
10-10 0
|
|
1-00- 0
|
|
110-- 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
|
|
0- 1
|
|
-1 1
|
|
10 0
|
|
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
|
|
0 1
|
|
1 0
|
|
.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
|
inst_VPA_D.BLIF inst_DTACK_D0.BLIF cpu_est_2_.BLIF inst_CLK_000_NE_D0.BLIF \
|
|
pos_clk_un29_clk_000_ne_d0_i_n
|
|
----0-0- 1
|
|
----11-- 1
|
|
---10--- 1
|
|
--1-0--- 1
|
|
-1--0--- 1
|
|
0---0--- 1
|
|
-------0 1
|
|
10000-11 0
|
|
----10-1 0
|
|
.names IPL_030DFF_2_reg.BLIF IPL_030_2_
|
|
1 1
|
|
0 0
|
|
.names BG_000DFFreg.BLIF BG_000
|
|
1 1
|
|
0 0
|
|
.names inst_BGACK_030_INTreg.BLIF BGACK_030
|
|
1 1
|
|
0 0
|
|
.names CLK_DIV_OUT
|
|
0
|
|
.names CLK_030.BLIF CLK_EXP
|
|
1 1
|
|
0 0
|
|
.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \
|
|
A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF FPU_CS
|
|
-------0- 1
|
|
------1-- 1
|
|
-----0--- 1
|
|
----1---- 1
|
|
---1----- 1
|
|
--1------ 1
|
|
-0------- 1
|
|
0-------- 1
|
|
--------1 1
|
|
110001010 0
|
|
.names inst_DSACK1_INTreg.BLIF DSACK1
|
|
1 1
|
|
0 0
|
|
.names AVEC
|
|
1
|
|
.names cpu_est_3_reg.BLIF E
|
|
1 1
|
|
0 0
|
|
.names inst_VMA_INTreg.BLIF VMA
|
|
1 1
|
|
0 0
|
|
.names inst_RESET_OUTreg.BLIF RESET
|
|
1 1
|
|
0 0
|
|
.names AMIGA_ADDR_ENABLE
|
|
0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF AS_000.PIN.BLIF \
|
|
RW_000.PIN.BLIF AMIGA_BUS_DATA_DIR
|
|
0001 1
|
|
1--0 1
|
|
-1-1 0
|
|
--11 0
|
|
0--0 0
|
|
1--1 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \
|
|
AMIGA_BUS_ENABLE_LOW
|
|
1- 1
|
|
-1 1
|
|
00 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \
|
|
SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
|
|
01- 1
|
|
1-0 1
|
|
00- 0
|
|
1-1 0
|
|
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
|
|
A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
|
|
inst_AS_030_D0.BLIF CIIN
|
|
0000000011110 1
|
|
-----------0- 0
|
|
----------0-- 0
|
|
---------0--- 0
|
|
--------0---- 0
|
|
-------1----- 0
|
|
------1------ 0
|
|
-----1------- 0
|
|
----1-------- 0
|
|
---1--------- 0
|
|
--1---------- 0
|
|
-1----------- 0
|
|
1------------ 0
|
|
------------1 0
|
|
.names IPL_030DFF_1_reg.BLIF IPL_030_1_
|
|
1 1
|
|
0 0
|
|
.names IPL_030DFF_0_reg.BLIF IPL_030_0_
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_030DFF_2_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_D0_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_D0_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_D0_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
|
|
1 1
|
|
0 0
|
|
.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_.D
|
|
10 1
|
|
01 1
|
|
00 0
|
|
11 0
|
|
.names CLK_OSZI.BLIF cpu_est_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_3_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_030DFF_0_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_030DFF_1_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RST_DLY_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CYCLE_DMA_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CYCLE_DMA_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SIZE_DMA_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SIZE_DMA_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_8_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF CLK_000_N_SYNC_0_.D
|
|
10 1
|
|
0- 0
|
|
-1 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_030_H.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_RESET_OUTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_RW_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_RW_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_DSACK1_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_A0_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_DS_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_DS_030_D0.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AS_030_D0.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_nEXP_SPACE_D0reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_VPA_D.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_DTACK_D0.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF BG_000DFFreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_VMA_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_UDS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_PE.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_NE.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_D1.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_NE_D0.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000.BLIF inst_CLK_000_D0.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_D0.C
|
|
1 1
|
|
0 0
|
|
.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_1_
|
|
01 1
|
|
1- 0
|
|
-0 0
|
|
.names inst_AS_000_DMA.BLIF AS_000.PIN.BLIF AS_030
|
|
1- 1
|
|
-1 1
|
|
00 0
|
|
.names inst_AS_000_INT.BLIF AS_030.PIN.BLIF AS_000
|
|
1- 1
|
|
-1 1
|
|
00 0
|
|
.names inst_RW_000_INT.BLIF RW_000
|
|
1 1
|
|
0 0
|
|
.names inst_DS_000_DMA.BLIF AS_000.PIN.BLIF DS_030
|
|
1- 1
|
|
-1 1
|
|
00 0
|
|
.names inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF DS_030.PIN.BLIF UDS_000
|
|
-0- 1
|
|
1-- 1
|
|
--1 1
|
|
010 0
|
|
.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF DS_030.PIN.BLIF LDS_000
|
|
-0- 1
|
|
1-- 1
|
|
--1 1
|
|
010 0
|
|
.names inst_A0_DMA.BLIF A0
|
|
1 1
|
|
0 0
|
|
.names BERR
|
|
0
|
|
.names inst_RW_000_DMA.BLIF RW
|
|
1 1
|
|
0 0
|
|
.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_0_
|
|
10 1
|
|
0- 0
|
|
-1 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF \
|
|
inst_nEXP_SPACE_D0reg.BLIF AS_030.OE
|
|
010 1
|
|
-0- 0
|
|
1-- 0
|
|
--1 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF AS_000.OE
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF RW_000.OE
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF \
|
|
inst_nEXP_SPACE_D0reg.BLIF DS_030.OE
|
|
010 1
|
|
-0- 0
|
|
1-- 0
|
|
--1 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF UDS_000.OE
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF LDS_000.OE
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF SIZE_0_.OE
|
|
00 1
|
|
1- 0
|
|
-1 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF SIZE_1_.OE
|
|
00 1
|
|
1- 0
|
|
-1 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF \
|
|
inst_nEXP_SPACE_D0reg.BLIF A0.OE
|
|
010 1
|
|
-0- 0
|
|
1-- 0
|
|
--1 0
|
|
.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \
|
|
A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF BERR.OE
|
|
111001010 1
|
|
-------0- 0
|
|
------1-- 0
|
|
-----0--- 0
|
|
----1---- 0
|
|
---1----- 0
|
|
--0------ 0
|
|
-0------- 0
|
|
0-------- 0
|
|
--------1 0
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF RW.OE
|
|
01 1
|
|
1- 0
|
|
-0 0
|
|
.names CLK_DIV_OUT.OE
|
|
0
|
|
.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE
|
|
1 1
|
|
0 0
|
|
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
|
|
A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
|
|
inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF CIIN.OE
|
|
0000000011110- 1
|
|
-------------1 1
|
|
------------10 0
|
|
-----------0-0 0
|
|
----------0--0 0
|
|
---------0---0 0
|
|
--------0----0 0
|
|
-------1-----0 0
|
|
------1------0 0
|
|
-----1-------0 0
|
|
----1--------0 0
|
|
---1---------0 0
|
|
--1----------0 0
|
|
-1-----------0 0
|
|
1------------0 0
|
|
.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
|
|
inst_CLK_000_NE_D0.BLIF cpu_est_3_reg.D.X1
|
|
11111 1
|
|
0---- 0
|
|
-0--- 0
|
|
--0-- 0
|
|
---0- 0
|
|
----0 0
|
|
.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
|
|
inst_CLK_000_NE_D0.BLIF cpu_est_3_reg.D.X2
|
|
1---- 1
|
|
-0001 1
|
|
-1101 1
|
|
0--1- 0
|
|
0---0 0
|
|
001-- 0
|
|
010-- 0
|
|
.names RST.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D.X1
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names RST.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \
|
|
cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF inst_CLK_000_PE.BLIF \
|
|
cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_4_.BLIF \
|
|
BERR.PIN.BLIF SM_AMIGA_3_.D.X2
|
|
1------1-0-1- 1
|
|
1--------1--0 1
|
|
110000--1110- 1
|
|
1----10--110- 1
|
|
0------------ 0
|
|
-------0-0--- 0
|
|
---------0-0- 0
|
|
---------10-1 0
|
|
---------1-11 0
|
|
-0---0---1--1 0
|
|
--1--0---1--1 0
|
|
---1-0---1--1 0
|
|
----10---1--1 0
|
|
-----11--1--1 0
|
|
-----0--01--1 0
|
|
.names RST.BLIF RST_DLY_4_.BLIF RST_DLY_4_.D.X1
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \
|
|
RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_4_.D.X2
|
|
1111110--- 1
|
|
111111-0-- 1
|
|
111111--0- 1
|
|
111111---0 1
|
|
0--------- 0
|
|
-0-------- 0
|
|
--0------- 0
|
|
---0------ 0
|
|
----0----- 0
|
|
-----0---- 0
|
|
------1111 0
|
|
.names RST_DLY_5_.BLIF RST_DLY_5_.D.X1
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \
|
|
RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_5_.D.X2
|
|
11111110-- 1
|
|
0------1-- 1
|
|
-11111110- 1
|
|
-1111111-0 1
|
|
10-------- 0
|
|
1-0------- 0
|
|
1--0------ 0
|
|
1---0----- 0
|
|
1----0---- 0
|
|
1-----0--- 0
|
|
0------0-- 0
|
|
-0-----0-- 0
|
|
--0----0-- 0
|
|
---0---0-- 0
|
|
----0--0-- 0
|
|
-----0-0-- 0
|
|
------00-- 0
|
|
1------111 0
|
|
.names RST_DLY_6_.BLIF RST_DLY_6_.D.X1
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
|
RST_DLY_2_.BLIF RST_DLY_3_.BLIF RST_DLY_4_.BLIF RST_DLY_5_.BLIF \
|
|
RST_DLY_6_.BLIF RST_DLY_7_.BLIF RST_DLY_6_.D.X2
|
|
111111110- 1
|
|
0-------1- 1
|
|
-111111110 1
|
|
10-------- 0
|
|
1-0------- 0
|
|
1--0------ 0
|
|
1---0----- 0
|
|
1----0---- 0
|
|
1-----0--- 0
|
|
1------0-- 0
|
|
0-------0- 0
|
|
-0------0- 0
|
|
--0-----0- 0
|
|
---0----0- 0
|
|
----0---0- 0
|
|
-----0--0- 0
|
|
------0-0- 0
|
|
-------00- 0
|
|
1-------11 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_030_H.D.X1
|
|
10 1
|
|
0- 0
|
|
-1 0
|
|
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
|
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF AS_000.PIN.BLIF \
|
|
UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2
|
|
-10-00---- 1
|
|
-10----1-- 1
|
|
110---0--- 1
|
|
-101--0--- 1
|
|
-10-----11 1
|
|
-10-11---- 1
|
|
-0-------- 0
|
|
--1------- 0
|
|
----01100- 0
|
|
----10100- 0
|
|
----0110-0 0
|
|
----1010-0 0
|
|
0--001-00- 0
|
|
0--010-00- 0
|
|
0--001-0-0 0
|
|
0--010-0-0 0
|
|
.names RST.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_i_7_.D.X1
|
|
10 1
|
|
0- 0
|
|
-1 0
|
|
.names RST.BLIF SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF \
|
|
inst_AS_030_000_SYNC.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF \
|
|
inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_0_.BLIF \
|
|
SM_AMIGA_6_.BLIF pos_clk_un29_clk_000_ne_d0_i_n.BLIF SM_AMIGA_1_.BLIF \
|
|
SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_i_7_.D.X2
|
|
100-----000-000- 1
|
|
10-1----000-000- 1
|
|
10--0---000-000- 1
|
|
10---1--000-000- 1
|
|
1-----0--0----10 1
|
|
1-----0--0---1-0 1
|
|
1------0-0--1--0 1
|
|
1-----0--01----0 1
|
|
1-------10-1---0 1
|
|
11-----0-0-----0 1
|
|
1-----0--1-----1 1
|
|
0--------------- 0
|
|
------1--1------ 0
|
|
---------1-----0 0
|
|
-1-------0-----1 0
|
|
--------10-----1 0
|
|
---------01----1 0
|
|
---------0--1--1 0
|
|
---------0---1-1 0
|
|
---------0----11 0
|
|
-1----110------- 0
|
|
------110-1----- 0
|
|
-1----11---0---- 0
|
|
------111--0---- 0
|
|
------110---1--- 0
|
|
-0----1-0-1-0--- 0
|
|
-0----1-1--00--- 0
|
|
-0----1-0---01-- 0
|
|
-0----1-0---0-1- 0
|
|
-1-----1000--00- 0
|
|
-1-----1-000-00- 0
|
|
-------11000-00- 0
|
|
-------1000-100- 0
|
|
-0------1000000- 0
|
|
-01010--000-000- 0
|
|
.end
|