mirror of https://github.com/kr239/68030tk.git
112 lines
8.5 KiB
HTML
112 lines
8.5 KiB
HTML
<html><body><samp><pre>
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<!@TC:1443104452>
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#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
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#install: C:\ispLever\synpbase
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#OS: Windows 7 6.2
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#Hostname: DEEPTHOUGHT
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#Implementation: logic
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<a name=compilerReport1>$ Start of Compile</a>
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#Thu Sep 24 16:20:52 2015
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Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
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@N: : <!@TM:1443104452> | Running in 64-bit mode
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Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
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@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1443104452> | Setting time resolution to ns
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@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1443104452> | Top entity is set to BUS68030.
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File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
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VHDL syntax check successful!
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File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1443104452> | Synthesizing work.bus68030.behavioral
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<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:7:126:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1443104452> | Signal clk_out_pre is undriven </font>
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Post processing for work.bus68030.behavioral
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<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1443104452> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
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<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1443104452> | Pruning register CLK_000_D4_2 </font>
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<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1443104452> | Pruning register CLK_000_D3_2 </font>
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<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1443104452> | Pruning register CLK_000_D2_2 </font>
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<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:127:35:127:38:@W:CL169:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1443104452> | Pruning register CLK_OUT_INT_2 </font>
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<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:36:124:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1443104452> | Pruning register CLK_OUT_PRE_50_D_2 </font>
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<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:155:2:155:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(155)</a><!@TM:1443104452> | Pruning register CLK_030_D0_2 </font>
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<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:135:61:135:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(135)</a><!@TM:1443104452> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
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<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1443104452> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
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<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1443104452> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
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@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1443104452> | Trying to extract state machine for register SM_AMIGA
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Extracted state machine for register SM_AMIGA
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State machine has 8 reachable states with original encodings of:
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000
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001
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010
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011
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100
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101
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110
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111
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@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1443104452> | Trying to extract state machine for register cpu_est
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<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1443104452> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
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@END
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Thu Sep 24 16:20:52 2015
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###########################################################]
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Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
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@N: : <!@TM:1443104453> | Running in 64-bit mode
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File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Thu Sep 24 16:20:53 2015
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###########################################################]
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Map & Optimize Report
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<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
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Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
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Product Version I-2014.03LC
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@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1443104454> | Running in 64-bit mode.
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<font color=#A52A2A>@W:<a href="@W:MO111:@XP_HELP">MO111</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:498:16:498:19:@W:MO111:@XP_MSG">68030-68000-bus.vhd(498)</a><!@TM:1443104454> | Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) </font>
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Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
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original code -> new code
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000 -> 00000000
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001 -> 00000011
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010 -> 00000101
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011 -> 00001001
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100 -> 00010001
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101 -> 00100001
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110 -> 01000001
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111 -> 10000001
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@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:190:4:190:8:@N:MO106:@XP_MSG">68030-68000-bus.vhd(190)</a><!@TM:1443104454> | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
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<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1443104454> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
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---------------------------------------
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<a name=resourceUsage3>Resource Usage Report</a>
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Simple gate primitives:
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DFF 83 uses
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BI_DIR 11 uses
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IBUF 46 uses
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OBUF 15 uses
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BUFTH 3 uses
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AND2 308 uses
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INV 261 uses
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OR2 25 uses
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XOR2 15 uses
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@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1443104454> | Timing Report not generated for this device, please use place and route tools for timing analysis.
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I-2014.03LC
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Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Thu Sep 24 16:20:54 2015
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###########################################################]
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</pre></samp></body></html>
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