mirror of https://github.com/kr239/68030tk.git
571 lines
18 KiB
VHDL
571 lines
18 KiB
VHDL
-- Copyright: Matthias Heinrichs 2014
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-- Free for non-comercial use
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-- No warranty just for fun
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-- If you want to earn money with this code, ask me first!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity BUS68030 is
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port(
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AS_030: inout std_logic ;
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AS_000: inout std_logic ;
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RW_000: inout std_logic ;
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DS_030: inout std_logic ;
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UDS_000: inout std_logic;
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LDS_000: inout std_logic;
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SIZE: inout std_logic_vector ( 1 downto 0 );
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AHIGH: inout std_logic_vector ( 31 downto 24 );
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A_DECODE: in std_logic_vector ( 23 downto 2 );
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A: inout std_logic_vector ( 1 downto 0 );
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--A0: inout std_logic;
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--A1: in std_logic;
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nEXP_SPACE: in std_logic ;
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BERR: inout std_logic ;
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BG_030: in std_logic ;
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BG_000: out std_logic ;
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BGACK_030: out std_logic ;
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BGACK_000: in std_logic ;
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CLK_030: in std_logic ;
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CLK_000: in std_logic ;
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CLK_OSZI: in std_logic ;
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CLK_DIV_OUT: out std_logic ;
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CLK_EXP: out std_logic ;
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FPU_CS: out std_logic ;
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FPU_SENSE: in std_logic ;
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IPL_030: out std_logic_vector ( 2 downto 0 );
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IPL: in std_logic_vector ( 2 downto 0 );
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DSACK1: inout std_logic;
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DTACK: inout std_logic ;
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AVEC: out std_logic ;
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E: out std_logic ;
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VPA: in std_logic ;
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VMA: out std_logic ;
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RST: in std_logic ;
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RESET: inout std_logic ;
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RW: inout std_logic ;
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-- D: inout std_logic_vector ( 31 downto 28 );
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FC: in std_logic_vector ( 1 downto 0 );
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AMIGA_ADDR_ENABLE: out std_logic ;
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AMIGA_BUS_DATA_DIR: out std_logic ;
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AMIGA_BUS_ENABLE_LOW: out std_logic;
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AMIGA_BUS_ENABLE_HIGH: out std_logic;
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CIIN: out std_logic
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);
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end BUS68030;
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architecture Behavioral of BUS68030 is
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-- values are determined empirically
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constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 25MHZ
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--constant DS_SAMPLE : integer := 12; -- for 7.09 MHz Clock with a base clock of 100Mhz and CPU running at 50MHZ
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TYPE SM_E IS (
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E1,
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E2,
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E3,
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E4,
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E5,
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E6,
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E7,
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E8,
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E9,
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E10
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);
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signal cpu_est : SM_E;
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TYPE SM_68000 IS (
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IDLE_P,
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IDLE_N,
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AS_SET_P,
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AS_SET_N,
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SAMPLE_DTACK_P,
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DATA_FETCH_N,
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DATA_FETCH_P,
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END_CYCLE_N
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);
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signal SM_AMIGA : SM_68000;
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--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
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signal AS_000_INT:STD_LOGIC := '1';
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signal AS_000_D0:STD_LOGIC := '1';
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signal RW_000_INT:STD_LOGIC := '1';
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signal AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC := '1';
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signal AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC := '1';
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signal AS_030_D0:STD_LOGIC := '1';
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signal AS_030_D1:STD_LOGIC := '1';
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signal nEXP_SPACE_D0:STD_LOGIC := '0';
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signal DS_030_D0:STD_LOGIC := '1';
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signal AS_030_000_SYNC:STD_LOGIC := '1';
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signal BGACK_030_INT:STD_LOGIC := '1';
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signal BGACK_030_INT_D:STD_LOGIC := '1';
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signal BGACK_030_INT_PRE:STD_LOGIC := '1';
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signal AS_000_DMA:STD_LOGIC := '1';
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signal DS_000_DMA:STD_LOGIC := '1';
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signal RW_000_DMA:STD_LOGIC := '1';
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signal CYCLE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
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signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
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signal IPL_D0: STD_LOGIC_VECTOR ( 2 downto 0 ) := "111";
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signal A0_DMA: STD_LOGIC := '1';
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signal VMA_INT: STD_LOGIC := '1';
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signal VPA_D: STD_LOGIC := '1';
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signal UDS_000_INT: STD_LOGIC := '1';
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signal LDS_000_INT: STD_LOGIC := '1';
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signal DS_000_ENABLE: STD_LOGIC := '0';
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signal DSACK1_INT: STD_LOGIC := '1';
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signal CLK_OUT_PRE_50: STD_LOGIC := '1';
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signal CLK_OUT_PRE_25: STD_LOGIC := '1';
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signal CLK_OUT_PRE: STD_LOGIC := '1';
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signal CLK_OUT_PRE_D: STD_LOGIC := '1';
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signal CLK_OUT_INT: STD_LOGIC := '1';
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signal CLK_OUT_EXP_INT: STD_LOGIC := '1';
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signal CLK_030_H: STD_LOGIC := '1';
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signal CLK_000_D: STD_LOGIC_VECTOR ( DS_SAMPLE downto 0 );
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signal CLK_000_PE: STD_LOGIC := '0';
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signal CLK_000_NE: STD_LOGIC := '0';
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signal DTACK_D0: STD_LOGIC := '1';
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signal RESET_OUT: STD_LOGIC := '0';
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signal CLK_030_D0: STD_LOGIC := '0';
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signal RST_DLY: STD_LOGIC_VECTOR ( 2 downto 0 ) := "000";
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signal CLK_030_PE: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
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signal AMIGA_DS: STD_LOGIC := '1';
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signal DTACK_DMA: STD_LOGIC := '1';
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begin
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CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1);
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CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1);
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--pos edge clock process
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--no ansynchronious reset! the reset is sampled synchroniously
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--this mut be because of the e-clock: The E-Clock has to run CONSTANTLY
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--or the Amiga will fail to boot from a reset.
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--However a compilation with no resets on the E-Clock and resets on other signals does not work, either!
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pos_clk: process(CLK_OSZI)
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begin
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if(rising_edge(CLK_OSZI)) then
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--clk generation :
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CLK_030_D0 <=CLK_030;
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CLK_OUT_PRE_50 <= not CLK_OUT_PRE_50;
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if(CLK_OUT_PRE_50 = '1' )then
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CLK_OUT_PRE_25<= not CLK_OUT_PRE_25;
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end if;
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--here the clock is selected
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--CLK_OUT_PRE_D <= CLK_OUT_PRE_25;
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CLK_OUT_PRE_D <= CLK_OUT_PRE_50;
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-- the external clock to the processor is generated here
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CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
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CLK_OUT_EXP_INT <= CLK_OUT_PRE_D;
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--delayed Clocks and signals for edge detection
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CLK_000_D(0) <= CLK_000;
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CLK_000_D(DS_SAMPLE downto 1) <= CLK_000_D((DS_SAMPLE-1) downto 0);
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-- e-clock is changed on the FALLING edge!
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if(CLK_000_NE = '1' ) then
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case (cpu_est) is
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when E1 => cpu_est <= E2 ;
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when E2 => cpu_est <= E3 ;
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when E3 => cpu_est <= E4;
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when E4 => cpu_est <= E5 ;
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when E5 => cpu_est <= E6 ;
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when E6 => cpu_est <= E7 ;
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when E7 => cpu_est <= E8 ;
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when E8 => cpu_est <= E9 ;
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when E9 => cpu_est <= E10;
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when E10 => cpu_est <= E1 ;
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end case;
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end if;
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--the statemachine
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if(RST = '0' ) then
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VPA_D <= '1';
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DTACK_D0 <= '1';
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SM_AMIGA <= IDLE_P;
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AS_000_INT <= '1';
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RW_000_INT <= '1';
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RW_000_DMA <= '1';
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AS_030_000_SYNC <= '1';
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UDS_000_INT <= '1';
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LDS_000_INT <= '1';
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DS_000_ENABLE <= '0';
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VMA_INT <= '1';
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BG_000 <= '1';
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BGACK_030_INT <= '1';
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BGACK_030_INT_D <= '1';
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BGACK_030_INT_PRE<= '1';
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DSACK1_INT <= '1';
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IPL_D0 <= "111";
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IPL_030 <= "111";
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AS_000_DMA <= '1';
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DS_000_DMA <= '1';
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SIZE_DMA <= "11";
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A0_DMA <= '1';
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AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
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AMIGA_BUS_ENABLE_DMA_LOW <= '1';
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AS_030_D0 <= '1';
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nEXP_SPACE_D0 <= '1';
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DS_030_D0 <= '1';
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CYCLE_DMA <= "00";
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RST_DLY <= "000";
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RESET_OUT <= '0';
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AS_000_D0 <='1';
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AMIGA_DS <='1';
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CLK_030_PE <= "00";
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else
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if(CLK_000_NE='1')then
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if(RST_DLY="111")then
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RESET_OUT <= '1';
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else
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RST_DLY <= RST_DLY+1;
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end if;
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end if;
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--now: 68000 state machine and signals
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--buffering signals
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AS_030_D0 <= AS_030;
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AS_030_D1 <= AS_030_D0;
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nEXP_SPACE_D0 <= nEXP_SPACE;
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DS_030_D0 <= DS_030;
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DTACK_D0 <= DTACK;
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VPA_D <= VPA;
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--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
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if(BGACK_000='0') then
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BGACK_030_INT <= '0';
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--BGACK_030_INT_PRE<= '0';
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elsif ( BGACK_000='1'
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AND CLK_000_NE='1'
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AND AS_000 = '1' --the amiga AS can be still active while bgack is deasserted, so wait for this signal too!
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) then -- BGACK_000 is high here!
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--BGACK_030_INT_PRE<= '1';
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BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes low
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end if;
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BGACK_030_INT_D <= BGACK_030_INT;
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--bus grant only in idle state
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if(BG_030= '1')then
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BG_000 <= '1';
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elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
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and nEXP_SPACE = '1' and AS_030_D0='1'
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and CLK_000_D(0)='1'
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) then --bus granted no local access and no AS_030 running!
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BG_000 <= '0';
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end if;
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--interrupt buffering to avoid ghost interrupts
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IPL_D0<=IPL;
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if(IPL = IPL_D0) then --and CLK_000_PE = '1')then
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IPL_030<=IPL;
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end if;
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-- as030-sampling and FPU-Select
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if(AS_030 ='1') then -- "async" reset of various signals
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AS_030_000_SYNC <= '1';
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DSACK1_INT <= '1';
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AS_000_INT <= '1';
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DS_000_ENABLE <= '0';
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--RW_000_INT <= '1';
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elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
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AS_030_D1 = '0' AND --as set
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BGACK_030_INT='1' AND
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BGACK_030_INT_D='1' AND --no dma -cycle
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NOT (FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0') AND --FPU-Select
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nEXP_SPACE ='1' and --not an expansion space cycle
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SM_AMIGA = IDLE_P --last amiga cycle terminated
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) then
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AS_030_000_SYNC <= '0';
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end if;
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-- VMA generation
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if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
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VMA_INT <= '0';
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elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert
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VMA_INT <= '1';
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end if;
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--uds/lds precalculation
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if (SM_AMIGA = IDLE_N) then --DS: set udl/lds
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if(A(0)='0') then
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UDS_000_INT <= '0';
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else
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UDS_000_INT <= '1';
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end if;
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if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
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LDS_000_INT <= '0';
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else
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LDS_000_INT <= '1';
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end if;
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end if;
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--Amiga statemachine
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case (SM_AMIGA) is
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when IDLE_P => --68000:S0 wait for a falling edge
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RW_000_INT <= '1';
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if( CLK_000_D(3)='0' and CLK_000_D(4)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
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SM_AMIGA<=IDLE_N; --go to s1
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end if;
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when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
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if(CLK_000_PE='1')then --go to s2
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SM_AMIGA <= AS_SET_P; --as for amiga set!
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RW_000_INT <= RW;
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AS_000_INT <= '0';
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if (RW='1' ) then --read: set udl/lds
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DS_000_ENABLE <= '1';
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end if;
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end if;
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when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
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if(CLK_000_NE='1')then --go to s3
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SM_AMIGA<=AS_SET_N;
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end if;
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when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
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if(CLK_000_PE='1')then --go to s4
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-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
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DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
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SM_AMIGA <= SAMPLE_DTACK_P;
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end if;
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when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
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if( CLK_000_NE='1' and --falling edge
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((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
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(BERR='0') OR --Bus error
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(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
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)then --go to s5
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SM_AMIGA<=DATA_FETCH_N;
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end if;
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when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
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if(CLK_000_PE = '1')then --go to s6
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SM_AMIGA<=DATA_FETCH_P;
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end if;
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when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
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--if( (CLK_000_D(DS_SAMPLE-2)='0' AND CLK_000_D((DS_SAMPLE-1))='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
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-- (CLK_000_D(DS_SAMPLE-1)='0' AND CLK_000_D((DS_SAMPLE-0))='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
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-- DSACK1_INT <='0';
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--end if;
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--go to s7 dsack is sampled at the falling edge of the 030-clock
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--if(CLK_000_D(0)='0' and CLK_000_D(1)='1')then
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if( CLK_000_NE ='1') then
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SM_AMIGA<=END_CYCLE_N;
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DSACK1_INT <='0';
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end if;
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when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
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if(CLK_000_PE='1')then --go to s0
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SM_AMIGA<=IDLE_P;
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RW_000_INT <= '1';
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end if;
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end case;
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--dma stuff
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AS_000_D0 <=AS_000;
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if(UDS_000='0' or LDS_000='0') then
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AMIGA_DS <='0';
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else
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AMIGA_DS <='1';
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end if;
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if(BGACK_030_INT='0')then
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--set some signals NOT linked to AS_000='0'
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RW_000_DMA <= RW_000;
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-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
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if(UDS_000='0' and LDS_000='0') then
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SIZE_DMA <= "10"; --16bit
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else
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SIZE_DMA <= "01"; --8 bit
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end if;
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--now calculate the offset:
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--if uds is set low, a0 is so too.
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--if only lds is set a1 is high
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--therefore a1 = uds
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--great! life is simple here!
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A0_DMA <= UDS_000;
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--A0_DMA <= '0';
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--A1 is set by the amiga side
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--here we determine the upper or lower half of the databus
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AMIGA_BUS_ENABLE_DMA_HIGH <= A(1);
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AMIGA_BUS_ENABLE_DMA_LOW <= not A(1);
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else
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RW_000_DMA <= '1';
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SIZE_DMA <= "00";
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A0_DMA <= '0';
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AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
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AMIGA_BUS_ENABLE_DMA_LOW <= '1';
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end if;
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if(BGACK_030_INT='0' and AS_000='0')then
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-- an 68000-memory cycle is three negative edges long!
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if(CLK_000_NE='1' and CYCLE_DMA<"11")then
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CYCLE_DMA <= CYCLE_DMA+1;
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end if;
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if(nEXP_SPACE ='0') then --presume that all expansion devices can provide a buscycle in 320ns!
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DTACK_DMA <= '0';
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end if;
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else
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DTACK_DMA <= '1';
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CYCLE_DMA <= "00";
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end if;
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--as can only be done if we know the uds/lds!
|
|
if( CYCLE_DMA >"00"
|
|
and AS_000 = '0'
|
|
and AMIGA_DS ='0'
|
|
and (
|
|
CYCLE_DMA < "11"
|
|
or RW_000 = '1')
|
|
)then
|
|
--set AS_000
|
|
if( not(CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1')) then --sampled on rising edges, so we can set AS only if the next clock is not rising!!
|
|
AS_000_DMA <= '0';
|
|
--if(RW_000='1') then
|
|
DS_000_DMA <='0';
|
|
--end if;
|
|
end if;
|
|
|
|
--if( CLK_OUT_INT='0' and CLK_OUT_PRE_D ='1' and CLK_030_PE <"11" and AS_000_DMA = '0') then --sample rising edges
|
|
-- CLK_030_PE <= CLK_030_PE+1;
|
|
--end if;
|
|
|
|
--if(RW_000='0' and CLK_030_PE="01" and CLK_030='1')then
|
|
-- DS_000_DMA <= '0'; -- write: one clock delayed!
|
|
--end if;
|
|
|
|
else
|
|
--CLK_030_PE <= "00";
|
|
AS_000_DMA <= '1';
|
|
DS_000_DMA <= '1';
|
|
end if;
|
|
end if;
|
|
|
|
end if;
|
|
end process pos_clk;
|
|
|
|
--output clock assignment
|
|
CLK_DIV_OUT <= CLK_OUT_INT;
|
|
CLK_EXP <= CLK_OUT_INT;--not CLK_OUT_EXP_INT;
|
|
--CLK_DIV_OUT <= 'Z';
|
|
--CLK_EXP <= CLK_030;
|
|
|
|
|
|
RESET <= 'Z';
|
|
--RESET <= 'Z' when RESET_OUT ='1' else '0';
|
|
--RST <= '0' when RESET_OUT_AMIGA = '1' else 'Z';
|
|
--RESET <= RESET_OUT;
|
|
|
|
-- bus drivers
|
|
AMIGA_ADDR_ENABLE <= '0';
|
|
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and AS_030_000_SYNC='0' and AS_030 = '0' else --not (SM_AMIGA = IDLE_P or (SM_AMIGA = END_CYCLE_N and CLK_000 = '1')) ELSE
|
|
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
|
|
'1';
|
|
AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE
|
|
'1';
|
|
|
|
|
|
AMIGA_BUS_DATA_DIR <= not RW_000 WHEN (BGACK_030_INT ='1') ELSE --Amiga READ/WRITE
|
|
--'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
|
|
'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
|
|
--'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
|
|
'0'; --Point towarts TK
|
|
|
|
|
|
--dma stuff
|
|
DTACK <= 'Z';--DTACK will be generated by GARY!
|
|
--DTACK <= 'Z' when DTACK_DMA='1' else '0';
|
|
|
|
AS_030 <= 'Z' when BGACK_030_INT ='1' else
|
|
'0' when AS_000_DMA ='0' and AS_000 ='0' else
|
|
'1';
|
|
DS_030 <= 'Z' when BGACK_030_INT ='1' else
|
|
'0' when DS_000_DMA ='0' and AS_000 ='0' else
|
|
'1';
|
|
A(0) <= 'Z' when BGACK_030_INT ='1' --tristate on CPU-Cycle
|
|
else A0_DMA; --drive on DMA-Cycle
|
|
A(1) <= 'Z';
|
|
AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' else x"00";
|
|
SIZE <= "ZZ" when BGACK_030_INT ='1' else
|
|
SIZE_DMA;
|
|
--rw
|
|
RW <= 'Z' when BGACK_030_INT ='1' --tristate on CPU cycle
|
|
else RW_000_DMA; --drive on DMA-Cycle
|
|
|
|
BGACK_030 <= BGACK_030_INT;
|
|
|
|
--fpu
|
|
FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0'
|
|
else '1';
|
|
|
|
--if no copro is installed:
|
|
BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1'
|
|
else 'Z';
|
|
|
|
|
|
--cache inhibit: Tristate for expansion (it decides) and off for the Amiga
|
|
CIIN <= '1' WHEN AHIGH(31 downto 24) = x"00" and A_DECODE(23 downto 20) = x"F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
|
|
'Z' WHEN nEXP_SPACE = '0' ELSE --Tristate for expansion (it decides)
|
|
'0'; --off for the Amiga
|
|
|
|
--e and VMA
|
|
E <= '1' when
|
|
cpu_est = E7 or
|
|
cpu_est = E8 or
|
|
cpu_est = E9 or
|
|
cpu_est = E10
|
|
else '0';
|
|
VMA <= 'Z' when BGACK_030_INT ='0' else VMA_INT;
|
|
|
|
|
|
--AVEC
|
|
AVEC <= '1';
|
|
|
|
--as and uds/lds
|
|
AS_000 <= 'Z' when BGACK_030_INT ='0' or RST ='0' else
|
|
'0' when AS_000_INT ='0' and AS_030 ='0' else
|
|
'1';
|
|
RW_000 <= 'Z' when BGACK_030_INT ='0' or RST ='0' --tristate on DMA-cycle
|
|
else RW_000_INT; -- drive on CPU cycle
|
|
|
|
UDS_000 <= 'Z' when BGACK_030_INT ='0' or RST ='0' else --tristate on DMA cycle
|
|
--'1' when DS_000_ENABLE ='0' else
|
|
UDS_000_INT when DS_000_ENABLE ='1' -- output on cpu cycle
|
|
else '1'; -- datastrobe not ready jet
|
|
LDS_000 <= 'Z' when BGACK_030_INT ='0' or RST ='0' else --tristate on DMA cycle
|
|
--'1' when DS_000_ENABLE ='0' else
|
|
LDS_000_INT when DS_000_ENABLE ='1' -- output on cpu cycle
|
|
else '1'; -- datastrobe not ready jet
|
|
|
|
--dsack
|
|
DSACK1 <= 'Z' when nEXP_SPACE = '0' or BGACK_030_INT ='0' else --tristate on expansionboard cycle
|
|
DSACK1_INT when AS_030 = '0' else -- output on amiga cycle
|
|
--'1' when AS_030 = '1' and AS_030_D0 = '0' else --pull high
|
|
'1';
|
|
|
|
|
|
end Behavioral;
|