mirror of https://github.com/kr239/68030tk.git
639 lines
44 KiB
Plaintext
639 lines
44 KiB
Plaintext
Section Type Array Num Name Real Name Base Number Increment
|
|
// -------------------------------------------------------------------------------------------------
|
|
Port 1 A_DECODE(23:2) A_DECODE 23 22 -1
|
|
Port 2 IPL(2:0) IPL 2 3 -1
|
|
Port 3 FC(1:0) FC 1 2 -1
|
|
Port 4 IPL_030(2:0) IPL_030 2 3 -1
|
|
Port 5 SIZE(1:0) SIZE 1 2 -1
|
|
Port 6 AHIGH(31:24) AHIGH 31 8 -1
|
|
Port 7 A(1:0) A 1 2 -1
|
|
End
|
|
Section Member Rename Array-Notation Array Number Index
|
|
// -------------------------------------------------------------------------------------
|
|
Port SIZE_1_ SIZE[1] 5 0
|
|
Port SIZE_0_ SIZE[0] 5 1
|
|
Port AHIGH_31_ AHIGH[31] 6 0
|
|
Port AHIGH_30_ AHIGH[30] 6 1
|
|
Port AHIGH_29_ AHIGH[29] 6 2
|
|
Port AHIGH_28_ AHIGH[28] 6 3
|
|
Port AHIGH_27_ AHIGH[27] 6 4
|
|
Port AHIGH_26_ AHIGH[26] 6 5
|
|
Port AHIGH_25_ AHIGH[25] 6 6
|
|
Port AHIGH_24_ AHIGH[24] 6 7
|
|
Port A_DECODE_23_ A_DECODE[23] 1 0
|
|
Port A_DECODE_22_ A_DECODE[22] 1 1
|
|
Port A_DECODE_21_ A_DECODE[21] 1 2
|
|
Port A_DECODE_20_ A_DECODE[20] 1 3
|
|
Port A_DECODE_19_ A_DECODE[19] 1 4
|
|
Port A_DECODE_18_ A_DECODE[18] 1 5
|
|
Port A_DECODE_17_ A_DECODE[17] 1 6
|
|
Port A_DECODE_16_ A_DECODE[16] 1 7
|
|
Port A_DECODE_15_ A_DECODE[15] 1 8
|
|
Port A_DECODE_14_ A_DECODE[14] 1 9
|
|
Port A_DECODE_13_ A_DECODE[13] 1 10
|
|
Port A_DECODE_12_ A_DECODE[12] 1 11
|
|
Port A_DECODE_11_ A_DECODE[11] 1 12
|
|
Port A_DECODE_10_ A_DECODE[10] 1 13
|
|
Port A_DECODE_9_ A_DECODE[9] 1 14
|
|
Port A_DECODE_8_ A_DECODE[8] 1 15
|
|
Port A_DECODE_7_ A_DECODE[7] 1 16
|
|
Port A_DECODE_6_ A_DECODE[6] 1 17
|
|
Port A_DECODE_5_ A_DECODE[5] 1 18
|
|
Port A_DECODE_4_ A_DECODE[4] 1 19
|
|
Port A_DECODE_3_ A_DECODE[3] 1 20
|
|
Port A_DECODE_2_ A_DECODE[2] 1 21
|
|
Port A_1_ A[1] 7 0
|
|
Port A_0_ A[0] 7 1
|
|
Port IPL_030_2_ IPL_030[2] 4 0
|
|
Port IPL_030_1_ IPL_030[1] 4 1
|
|
Port IPL_030_0_ IPL_030[0] 4 2
|
|
Port IPL_2_ IPL[2] 2 0
|
|
Port IPL_1_ IPL[1] 2 1
|
|
Port IPL_0_ IPL[0] 2 2
|
|
Port FC_1_ FC[1] 3 0
|
|
Port FC_0_ FC[0] 3 1
|
|
End
|
|
Section Cross Reference File
|
|
Design 'BUS68030' created Sat Dec 30 00:43:37 2017
|
|
Type New Name Original Name
|
|
// ----------------------------------------------------------------------
|
|
Inst i_z3434 AS_030
|
|
Inst i_z3535 AS_000
|
|
Inst i_z3636 RW_000
|
|
Inst i_z3737 DS_030
|
|
Inst i_z3838 UDS_000
|
|
Inst i_z3939 LDS_000
|
|
Inst i_z4D4D BERR
|
|
Inst i_z4V4V DSACK1
|
|
Inst i_z5454 VMA
|
|
Inst i_z5757 RW
|
|
Inst i_z5E5E CIIN
|
|
Inst pos_clk_un34_as_030_d1_i_i_o2_3 pos_clk.un34_as_030_d1_i_i_o2_3
|
|
Inst SM_AMIGA_i_3_ SM_AMIGA_i[3]
|
|
Inst pos_clk_un34_as_030_d1_i_i_o2_4 pos_clk.un34_as_030_d1_i_i_o2_4
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_4_ SM_AMIGA_srsts_i_0_0_o2[4]
|
|
Inst pos_clk_un34_as_030_d1_i_i_o2 pos_clk.un34_as_030_d1_i_i_o2
|
|
Inst pos_clk_un10_sm_amiga_1 pos_clk.un10_sm_amiga_1
|
|
Inst cpu_est_i_0_ cpu_est_i[0]
|
|
Inst pos_clk_un10_sm_amiga pos_clk.un10_sm_amiga
|
|
Inst cpu_est_2_0_0_a2_0_2_ cpu_est_2_0_0_a2_0[2]
|
|
Inst pos_clk_un9_clk_000_pe_0_0 pos_clk.un9_clk_000_pe_0_0
|
|
Inst IPL_030_1_i_0_ IPL_030_1_i[0]
|
|
Inst cpu_est_2_0_0_0_1_ cpu_est_2_0_0_0[1]
|
|
Inst IPL_c_i_2_ IPL_c_i[2]
|
|
Inst cpu_est_2_0_0_0_2_ cpu_est_2_0_0_0[2]
|
|
Inst IPL_D0_0_i_2_ IPL_D0_0_i[2]
|
|
Inst cpu_est_2_0_0_0_3_ cpu_est_2_0_0_0[3]
|
|
Inst IPL_c_i_1_ IPL_c_i[1]
|
|
Inst IPL_D0_0_i_1_ IPL_D0_0_i[1]
|
|
Inst IPL_c_i_0_ IPL_c_i[0]
|
|
Inst pos_clk_SIZE_DMA_6_0_0_0_0_ pos_clk.SIZE_DMA_6_0_0_0[0]
|
|
Inst IPL_D0_0_i_0_ IPL_D0_0_i[0]
|
|
Inst pos_clk_SIZE_DMA_6_0_0_0_1_ pos_clk.SIZE_DMA_6_0_0_0[1]
|
|
Inst cpu_est_0_0_0_0_ cpu_est_0_0_0[0]
|
|
Inst CLK_000_D_i_1_ CLK_000_D_i[1]
|
|
Inst pos_clk_SIZE_DMA_6_0_0_0_a2_0_ pos_clk.SIZE_DMA_6_0_0_0_a2[0]
|
|
Inst pos_clk_SIZE_DMA_6_0_0_0_a2_1_ pos_clk.SIZE_DMA_6_0_0_0_a2[1]
|
|
Inst SM_AMIGA_i_2_ SM_AMIGA_i[2]
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_2_ SM_AMIGA_srsts_i_0_0_a2[2]
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_3_ SM_AMIGA_srsts_i_0_0_a2[3]
|
|
Inst cpu_est_2_0_0_0_i_1_ cpu_est_2_0_0_0_i[1]
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_0_3_ SM_AMIGA_srsts_i_0_0_a2_0[3]
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_4_ SM_AMIGA_srsts_i_0_0_a2[4]
|
|
Inst SM_AMIGA_nss_i_i_0_0_a2_0_0_ SM_AMIGA_nss_i_i_0_0_a2_0[0]
|
|
Inst cpu_est_0_0_0_a2_0_ cpu_est_0_0_0_a2[0]
|
|
Inst cpu_est_0_0_0_a2_0_0_ cpu_est_0_0_0_a2_0[0]
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_2_3_ SM_AMIGA_srsts_i_0_0_a2_2[3]
|
|
Inst pos_clk_un9_clk_000_pe_0_0_i pos_clk.un9_clk_000_pe_0_0_i
|
|
Inst cpu_est_i_2_ cpu_est_i[2]
|
|
Inst IPL_030_1_i_2_ IPL_030_1_i[2]
|
|
Inst IPL_030_1_i_1_ IPL_030_1_i[1]
|
|
Inst pos_clk_SIZE_DMA_6_0_0_0_i_1_ pos_clk.SIZE_DMA_6_0_0_0_i[1]
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_1_ SM_AMIGA_srsts_i_0_0_a2[1]
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_0_1_ SM_AMIGA_srsts_i_0_0_a2_0[1]
|
|
Inst pos_clk_SIZE_DMA_6_0_0_0_i_0_ pos_clk.SIZE_DMA_6_0_0_0_i[0]
|
|
Inst cpu_est_2_0_0_0_a2_1_ cpu_est_2_0_0_0_a2[1]
|
|
Inst cpu_est_2_0_0_0_a2_2_ cpu_est_2_0_0_0_a2[2]
|
|
Inst cpu_est_2_0_0_0_a2_3_ cpu_est_2_0_0_0_a2[3]
|
|
Inst SM_AMIGA_4_ SM_AMIGA[4]
|
|
Inst SM_AMIGA_3_ SM_AMIGA[3]
|
|
Inst cpu_est_2_0_0_0_i_3_ cpu_est_2_0_0_0_i[3]
|
|
Inst SM_AMIGA_2_ SM_AMIGA[2]
|
|
Inst SM_AMIGA_1_ SM_AMIGA[1]
|
|
Inst SM_AMIGA_0_ SM_AMIGA[0]
|
|
Inst cpu_est_2_0_0_0_i_2_ cpu_est_2_0_0_0_i[2]
|
|
Inst IPL_030DFF_0_ IPL_030DFF[0]
|
|
Inst IPL_030DFF_1_ IPL_030DFF[1]
|
|
Inst cpu_est_2_0_0_0_o2_i_2_ cpu_est_2_0_0_0_o2_i[2]
|
|
Inst IPL_030DFF_2_ IPL_030DFF[2]
|
|
Inst IPL_D0_0_ IPL_D0[0]
|
|
Inst cpu_est_2_0_0_0_o2_i_3_ cpu_est_2_0_0_0_o2_i[3]
|
|
Inst IPL_D0_1_ IPL_D0[1]
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_i_1_ SM_AMIGA_srsts_i_0_0_o2_i[1]
|
|
Inst IPL_D0_2_ IPL_D0[2]
|
|
Inst SM_AMIGA_i_7_ SM_AMIGA_i[7]
|
|
Inst pos_clk_un6_bg_030_0_a3_i_i pos_clk.un6_bg_030_0_a3_i_i
|
|
Inst SM_AMIGA_6_ SM_AMIGA[6]
|
|
Inst IPL_D0_0_1_ IPL_D0_0[1]
|
|
Inst SM_AMIGA_5_ SM_AMIGA[5]
|
|
Inst IPL_D0_0_2_ IPL_D0_0[2]
|
|
Inst CLK_000_D_1_ CLK_000_D[1]
|
|
Inst IPL_030_1_0_ IPL_030_1[0]
|
|
Inst CLK_000_D_2_ CLK_000_D[2]
|
|
Inst IPL_030_1_1_ IPL_030_1[1]
|
|
Inst CLK_000_D_3_ CLK_000_D[3]
|
|
Inst IPL_030_1_2_ IPL_030_1[2]
|
|
Inst CLK_000_D_4_ CLK_000_D[4]
|
|
Inst cpu_est_0_1__r cpu_est_0_1_.r
|
|
Inst SIZE_DMA_0_ SIZE_DMA[0]
|
|
Inst cpu_est_0_1__m cpu_est_0_1_.m
|
|
Inst SIZE_DMA_1_ SIZE_DMA[1]
|
|
Inst cpu_est_0_1__n cpu_est_0_1_.n
|
|
Inst CYCLE_DMA_0_ CYCLE_DMA[0]
|
|
Inst cpu_est_0_1__p cpu_est_0_1_.p
|
|
Inst CYCLE_DMA_1_ CYCLE_DMA[1]
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_i_6_ SM_AMIGA_srsts_i_0_0_o2_i[6]
|
|
Inst cpu_est_0_2__r cpu_est_0_2_.r
|
|
Inst cpu_est_0_ cpu_est[0]
|
|
Inst cpu_est_0_2__m cpu_est_0_2_.m
|
|
Inst cpu_est_1_ cpu_est[1]
|
|
Inst cpu_est_0_2__n cpu_est_0_2_.n
|
|
Inst cpu_est_2_ cpu_est[2]
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_i_4_ SM_AMIGA_srsts_i_0_0_o2_i[4]
|
|
Inst cpu_est_0_2__p cpu_est_0_2_.p
|
|
Inst cpu_est_3_ cpu_est[3]
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_i_2_ SM_AMIGA_srsts_i_0_0_o2_i[2]
|
|
Inst cpu_est_0_3__r cpu_est_0_3_.r
|
|
Inst CLK_000_D_0_ CLK_000_D[0]
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_0_i_3_ SM_AMIGA_srsts_i_0_0_o2_0_i[3]
|
|
Inst cpu_est_0_3__m cpu_est_0_3_.m
|
|
Inst cpu_est_0_3__n cpu_est_0_3_.n
|
|
Inst cpu_est_0_3__p cpu_est_0_3_.p
|
|
Inst pos_clk_SIZE_DMA_6_0_0_0_o2_i_0_ pos_clk.SIZE_DMA_6_0_0_0_o2_i[0]
|
|
Inst IPL_030_0_0__r IPL_030_0_0_.r
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_i_3_ SM_AMIGA_srsts_i_0_0_o2_i[3]
|
|
Inst IPL_030_0_0__m IPL_030_0_0_.m
|
|
Inst IPL_030_0_0__n IPL_030_0_0_.n
|
|
Inst IPL_030_0_0__p IPL_030_0_0_.p
|
|
Inst IPL_030_0_1__r IPL_030_0_1_.r
|
|
Inst IPL_030_0_1__m IPL_030_0_1_.m
|
|
Inst IPL_030_0_1__n IPL_030_0_1_.n
|
|
Inst IPL_030_0_1__p IPL_030_0_1_.p
|
|
Inst pos_clk_un6_bgack_000_0_0_i pos_clk.un6_bgack_000_0_0_i
|
|
Inst IPL_030_0_2__r IPL_030_0_2_.r
|
|
Inst IPL_030_0_2__m IPL_030_0_2_.m
|
|
Inst pos_clk_RW_000_INT_5_0_0_i pos_clk.RW_000_INT_5_0_0_i
|
|
Inst IPL_030_0_2__n IPL_030_0_2_.n
|
|
Inst IPL_030_0_2__p IPL_030_0_2_.p
|
|
Inst DS_000_ENABLE_0_r DS_000_ENABLE_0.r
|
|
Inst pos_clk_un34_as_030_d1_i_i_o2_i pos_clk.un34_as_030_d1_i_i_o2_i
|
|
Inst DS_000_ENABLE_0_m DS_000_ENABLE_0.m
|
|
Inst CLK_000_D_i_3_ CLK_000_D_i[3]
|
|
Inst DS_000_ENABLE_0_n DS_000_ENABLE_0.n
|
|
Inst SM_AMIGA_nss_i_i_0_0_o2_i_0_ SM_AMIGA_nss_i_i_0_0_o2_i[0]
|
|
Inst DS_000_ENABLE_0_p DS_000_ENABLE_0.p
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_i_0_ SM_AMIGA_srsts_i_0_0_o2_i[0]
|
|
Inst VMA_INT_0_r VMA_INT_0.r
|
|
Inst VMA_INT_0_m VMA_INT_0.m
|
|
Inst VMA_INT_0_n VMA_INT_0.n
|
|
Inst VMA_INT_0_p VMA_INT_0.p
|
|
Inst SIZE_0_ SIZE[0]
|
|
Inst A_c_i_0_ A_c_i[0]
|
|
Inst SIZE_1_ SIZE[1]
|
|
Inst SIZE_c_i_1_ SIZE_c_i[1]
|
|
Inst IPL_D0_0_0_ IPL_D0_0[0]
|
|
Inst AHIGH_24_ AHIGH[24]
|
|
Inst AHIGH_25_ AHIGH[25]
|
|
Inst pos_clk_un34_as_030_d1_i_i_i pos_clk.un34_as_030_d1_i_i_i
|
|
Inst AHIGH_26_ AHIGH[26]
|
|
Inst AHIGH_27_ AHIGH[27]
|
|
Inst AHIGH_28_ AHIGH[28]
|
|
Inst AHIGH_29_ AHIGH[29]
|
|
Inst AHIGH_30_ AHIGH[30]
|
|
Inst AHIGH_31_ AHIGH[31]
|
|
Inst pos_clk_un9_bg_030_i pos_clk.un9_bg_030_i
|
|
Inst pos_clk_as_000_dma6_i_0_0_i pos_clk.as_000_dma6_i_0_0_i
|
|
Inst A_DECODE_16_ A_DECODE[16]
|
|
Inst A_DECODE_17_ A_DECODE[17]
|
|
Inst A_DECODE_18_ A_DECODE[18]
|
|
Inst A_DECODE_19_ A_DECODE[19]
|
|
Inst A_DECODE_20_ A_DECODE[20]
|
|
Inst A_DECODE_21_ A_DECODE[21]
|
|
Inst CYCLE_DMA_i_0_ CYCLE_DMA_i[0]
|
|
Inst A_DECODE_22_ A_DECODE[22]
|
|
Inst pos_clk_CYCLE_DMA_5_0_i_a2 pos_clk.CYCLE_DMA_5_0_i_a2
|
|
Inst A_DECODE_23_ A_DECODE[23]
|
|
Inst A_0_ A[0]
|
|
Inst A_1_ A[1]
|
|
Inst A_i_1_ A_i[1]
|
|
Inst DS_000_DMA_0_r DS_000_DMA_0.r
|
|
Inst DS_000_DMA_0_m DS_000_DMA_0.m
|
|
Inst DS_000_DMA_0_n DS_000_DMA_0.n
|
|
Inst IPL_030_0_ IPL_030[0]
|
|
Inst DS_000_DMA_0_p DS_000_DMA_0.p
|
|
Inst IPL_030_1_ IPL_030[1]
|
|
Inst AS_000_DMA_0_r AS_000_DMA_0.r
|
|
Inst IPL_030_2_ IPL_030[2]
|
|
Inst AS_000_DMA_0_m AS_000_DMA_0.m
|
|
Inst IPL_0_ IPL[0]
|
|
Inst AS_000_DMA_0_n AS_000_DMA_0.n
|
|
Inst IPL_1_ IPL[1]
|
|
Inst AS_000_DMA_0_p AS_000_DMA_0.p
|
|
Inst IPL_2_ IPL[2]
|
|
Inst CYCLE_DMA_i_1_ CYCLE_DMA_i[1]
|
|
Inst UDS_000_INT_0_r UDS_000_INT_0.r
|
|
Inst FC_0_ FC[0]
|
|
Inst UDS_000_INT_0_m UDS_000_INT_0.m
|
|
Inst FC_1_ FC[1]
|
|
Inst UDS_000_INT_0_n UDS_000_INT_0.n
|
|
Inst UDS_000_INT_0_p UDS_000_INT_0.p
|
|
Inst BG_000_0_r BG_000_0.r
|
|
Inst BG_000_0_m BG_000_0.m
|
|
Inst BG_000_0_n BG_000_0.n
|
|
Inst BG_000_0_p BG_000_0.p
|
|
Inst SM_AMIGA_srsts_i_0_0_1_3_ SM_AMIGA_srsts_i_0_0_1[3]
|
|
Inst LDS_000_INT_0_r LDS_000_INT_0.r
|
|
Inst SM_AMIGA_srsts_i_0_0_3_ SM_AMIGA_srsts_i_0_0[3]
|
|
Inst LDS_000_INT_0_m LDS_000_INT_0.m
|
|
Inst SM_AMIGA_srsts_i_0_0_1_2_ SM_AMIGA_srsts_i_0_0_1[2]
|
|
Inst LDS_000_INT_0_n LDS_000_INT_0.n
|
|
Inst SM_AMIGA_srsts_i_0_0_2_ SM_AMIGA_srsts_i_0_0[2]
|
|
Inst LDS_000_INT_0_p LDS_000_INT_0.p
|
|
Inst SM_AMIGA_srsts_i_0_0_1_0_ SM_AMIGA_srsts_i_0_0_1[0]
|
|
Inst AS_030_D1_0_r AS_030_D1_0.r
|
|
Inst SM_AMIGA_srsts_i_0_0_0_ SM_AMIGA_srsts_i_0_0[0]
|
|
Inst AS_030_D1_0_m AS_030_D1_0.m
|
|
Inst AS_030_D1_0_n AS_030_D1_0.n
|
|
Inst AS_030_D1_0_p AS_030_D1_0.p
|
|
Inst RW_000_INT_0_r RW_000_INT_0.r
|
|
Inst RW_000_INT_0_m RW_000_INT_0.m
|
|
Inst cpu_est_2_0_0_a2_0_1_1_ cpu_est_2_0_0_a2_0_1[1]
|
|
Inst RW_000_INT_0_n RW_000_INT_0.n
|
|
Inst cpu_est_2_0_0_a2_0_1_ cpu_est_2_0_0_a2_0[1]
|
|
Inst RW_000_INT_0_p RW_000_INT_0.p
|
|
Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r
|
|
Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m
|
|
Inst pos_clk_as_000_dma6_i_0_0_2 pos_clk.as_000_dma6_i_0_0_2
|
|
Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n
|
|
Inst pos_clk_as_000_dma6_i_0_0 pos_clk.as_000_dma6_i_0_0
|
|
Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p
|
|
Inst BGACK_030_INT_0_r BGACK_030_INT_0.r
|
|
Inst BGACK_030_INT_0_m BGACK_030_INT_0.m
|
|
Inst BGACK_030_INT_0_n BGACK_030_INT_0.n
|
|
Inst pos_clk_un6_bg_030_0_a3_i_1 pos_clk.un6_bg_030_0_a3_i_1
|
|
Inst BGACK_030_INT_0_p BGACK_030_INT_0.p
|
|
Inst pos_clk_un6_bg_030_0_a3_i pos_clk.un6_bg_030_0_a3_i
|
|
Inst pos_clk_un9_bg_030 pos_clk.un9_bg_030
|
|
Inst SM_AMIGA_nss_i_i_0_0_1_0_ SM_AMIGA_nss_i_i_0_0_1[0]
|
|
Inst SM_AMIGA_nss_i_i_0_0_0_ SM_AMIGA_nss_i_i_0_0[0]
|
|
Inst SM_AMIGA_srsts_i_0_0_1_6_ SM_AMIGA_srsts_i_0_0_1[6]
|
|
Inst SM_AMIGA_srsts_i_0_0_6_ SM_AMIGA_srsts_i_0_0[6]
|
|
Inst SM_AMIGA_srsts_i_0_0_1_5_ SM_AMIGA_srsts_i_0_0_1[5]
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_5_ SM_AMIGA_srsts_i_0_0_a2[5]
|
|
Inst SM_AMIGA_srsts_i_0_0_5_ SM_AMIGA_srsts_i_0_0[5]
|
|
Inst SM_AMIGA_i_0_ SM_AMIGA_i[0]
|
|
Inst SM_AMIGA_srsts_i_0_0_1_4_ SM_AMIGA_srsts_i_0_0_1[4]
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_0_ SM_AMIGA_srsts_i_0_0_a2[0]
|
|
Inst SM_AMIGA_srsts_i_0_0_4_ SM_AMIGA_srsts_i_0_0[4]
|
|
Inst pos_clk_CYCLE_DMA_5_1_1 pos_clk.CYCLE_DMA_5_1_1
|
|
Inst pos_clk_CYCLE_DMA_5_1 pos_clk.CYCLE_DMA_5_1
|
|
Inst A_DECODE_i_16_ A_DECODE_i[16]
|
|
Inst A_DECODE_i_19_ A_DECODE_i[19]
|
|
Inst A_DECODE_i_18_ A_DECODE_i[18]
|
|
Inst pos_clk_as_000_dma6_i_0_0_a2_1 pos_clk.as_000_dma6_i_0_0_a2_1
|
|
Inst pos_clk_as_000_dma6_i_0_0_a2 pos_clk.as_000_dma6_i_0_0_a2
|
|
Inst pos_clk_CYCLE_DMA_5_0_i_1 pos_clk.CYCLE_DMA_5_0_i_1
|
|
Inst pos_clk_CYCLE_DMA_5_0_i_2 pos_clk.CYCLE_DMA_5_0_i_2
|
|
Inst pos_clk_un34_as_030_d1_i_i pos_clk.un34_as_030_d1_i_i
|
|
Inst pos_clk_CYCLE_DMA_5_0_i pos_clk.CYCLE_DMA_5_0_i
|
|
Inst pos_clk_as_000_dma6_i_0_0_1 pos_clk.as_000_dma6_i_0_0_1
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_2_ SM_AMIGA_srsts_i_0_0_o2[2]
|
|
Inst pos_clk_un6_bgack_000_0_0_a2 pos_clk.un6_bgack_000_0_0_a2
|
|
Inst SM_AMIGA_srsts_i_0_0_1_1_ SM_AMIGA_srsts_i_0_0_1[1]
|
|
Inst SM_AMIGA_srsts_i_0_0_2_1_ SM_AMIGA_srsts_i_0_0_2[1]
|
|
Inst pos_clk_DSACK1_INT_1_i_a2_0_a2 pos_clk.DSACK1_INT_1_i_a2_0_a2
|
|
Inst SM_AMIGA_srsts_i_0_0_1_ SM_AMIGA_srsts_i_0_0[1]
|
|
Inst pos_clk_un9_clk_000_pe_0_0_a2_0_1 pos_clk.un9_clk_000_pe_0_0_a2_0_1
|
|
Inst pos_clk_un9_clk_000_pe_0_0_a2_0_2 pos_clk.un9_clk_000_pe_0_0_a2_0_2
|
|
Inst pos_clk_AS_000_INT_1_i_a2_0_a2 pos_clk.AS_000_INT_1_i_a2_0_a2
|
|
Inst pos_clk_un9_clk_000_pe_0_0_a2_0 pos_clk.un9_clk_000_pe_0_0_a2_0
|
|
Inst SM_AMIGA_i_i_7_ SM_AMIGA_i_i[7]
|
|
Inst pos_clk_un9_clk_000_pe_0_0_a2_1 pos_clk.un9_clk_000_pe_0_0_a2_1
|
|
Inst SM_AMIGA_nss_i_i_0_0_a2_0_ SM_AMIGA_nss_i_i_0_0_a2[0]
|
|
Inst pos_clk_un9_clk_000_pe_0_0_a2_2 pos_clk.un9_clk_000_pe_0_0_a2_2
|
|
Inst SM_AMIGA_i_6_ SM_AMIGA_i[6]
|
|
Inst pos_clk_un9_clk_000_pe_0_0_a2 pos_clk.un9_clk_000_pe_0_0_a2
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_6_ SM_AMIGA_srsts_i_0_0_a2[6]
|
|
Inst pos_clk_un34_as_030_d1_i_i_a2_1 pos_clk.un34_as_030_d1_i_i_a2_1
|
|
Inst SM_AMIGA_i_5_ SM_AMIGA_i[5]
|
|
Inst pos_clk_un34_as_030_d1_i_i_a2_2 pos_clk.un34_as_030_d1_i_i_a2_2
|
|
Inst cpu_est_i_3_ cpu_est_i[3]
|
|
Inst pos_clk_un34_as_030_d1_i_i_a2_3 pos_clk.un34_as_030_d1_i_i_a2_3
|
|
Inst pos_clk_un34_as_030_d1_i_i_a2 pos_clk.un34_as_030_d1_i_i_a2
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_6_ SM_AMIGA_srsts_i_0_0_o2[6]
|
|
Inst pos_clk_RW_000_INT_5_0_0_o2 pos_clk.RW_000_INT_5_0_0_o2
|
|
Inst SM_AMIGA_i_1_ SM_AMIGA_i[1]
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_0_ SM_AMIGA_srsts_i_0_0_o2[0]
|
|
Inst pos_clk_RW_000_INT_5_0_0 pos_clk.RW_000_INT_5_0_0
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_1_1_3_ SM_AMIGA_srsts_i_0_0_a2_1_1[3]
|
|
Inst pos_clk_un6_bgack_000_0_0 pos_clk.un6_bgack_000_0_0
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_1_2_3_ SM_AMIGA_srsts_i_0_0_a2_1_2[3]
|
|
Inst SM_AMIGA_srsts_i_0_0_a2_1_3_ SM_AMIGA_srsts_i_0_0_a2_1[3]
|
|
Inst CLK_000_D_i_0_ CLK_000_D_i[0]
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_0_1_3_ SM_AMIGA_srsts_i_0_0_o2_0_1[3]
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_1_ SM_AMIGA_srsts_i_0_0_o2[1]
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_0_3_ SM_AMIGA_srsts_i_0_0_o2_0[3]
|
|
Inst cpu_est_2_0_0_0_o2_3_ cpu_est_2_0_0_0_o2[3]
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_1_2_ SM_AMIGA_srsts_i_0_0_o2_1[2]
|
|
Inst pos_clk_un9_clk_000_pe_0_0_o2 pos_clk.un9_clk_000_pe_0_0_o2
|
|
Inst cpu_est_i_1_ cpu_est_i[1]
|
|
Inst SM_AMIGA_nss_i_i_0_0_o2_1_0_ SM_AMIGA_nss_i_i_0_0_o2_1[0]
|
|
Inst cpu_est_2_0_0_0_o2_2_ cpu_est_2_0_0_0_o2[2]
|
|
Inst SM_AMIGA_nss_i_i_0_0_o2_2_0_ SM_AMIGA_nss_i_i_0_0_o2_2[0]
|
|
Inst SM_AMIGA_nss_i_i_0_0_o2_0_ SM_AMIGA_nss_i_i_0_0_o2[0]
|
|
Inst SM_AMIGA_i_4_ SM_AMIGA_i[4]
|
|
Inst pos_clk_un34_as_030_d1_i_i_o2_1 pos_clk.un34_as_030_d1_i_i_o2_1
|
|
Inst SM_AMIGA_srsts_i_0_0_o2_3_ SM_AMIGA_srsts_i_0_0_o2[3]
|
|
Inst pos_clk_un34_as_030_d1_i_i_o2_2 pos_clk.un34_as_030_d1_i_i_o2_2
|
|
Inst pos_clk_SIZE_DMA_6_0_0_0_o2_0_ pos_clk.SIZE_DMA_6_0_0_0_o2[0]
|
|
Net size_c_0__n SIZE_c[0]
|
|
Net ipl_c_i_2__n IPL_c_i[2]
|
|
Net size_0__n SIZE[0]
|
|
Net size_c_1__n SIZE_c[1]
|
|
Net ipl_c_i_1__n IPL_c_i[1]
|
|
Net vcc_n_n VCC
|
|
Net ahigh_c_24__n AHIGH_c[24]
|
|
Net ipl_c_i_0__n IPL_c_i[0]
|
|
Net ahigh_24__n AHIGH[24]
|
|
Net gnd_n_n GND
|
|
Net ahigh_c_25__n AHIGH_c[25]
|
|
Net ahigh_25__n AHIGH[25]
|
|
Net ahigh_c_26__n AHIGH_c[26]
|
|
Net ahigh_26__n AHIGH[26]
|
|
Net ahigh_c_27__n AHIGH_c[27]
|
|
Net ahigh_27__n AHIGH[27]
|
|
Net ahigh_c_28__n AHIGH_c[28]
|
|
Net ahigh_28__n AHIGH[28]
|
|
Net ahigh_c_29__n AHIGH_c[29]
|
|
Net ahigh_29__n AHIGH[29]
|
|
Net cpu_est_0__n cpu_est[0]
|
|
Net ahigh_c_30__n AHIGH_c[30]
|
|
Net cpu_est_1__n cpu_est[1]
|
|
Net ahigh_30__n AHIGH[30]
|
|
Net cpu_est_2__n cpu_est[2]
|
|
Net ahigh_c_31__n AHIGH_c[31]
|
|
Net cpu_est_3__n cpu_est[3]
|
|
Net pos_clk_un10_sm_amiga_i_1_n pos_clk.un10_sm_amiga_i_1
|
|
Net clk_000_d_3__n CLK_000_D[3]
|
|
Net clk_000_d_1__n CLK_000_D[1]
|
|
Net clk_000_d_0__n CLK_000_D[0]
|
|
Net ipl_d0_0__n IPL_D0[0]
|
|
Net ipl_d0_1__n IPL_D0[1]
|
|
Net ipl_d0_2__n IPL_D0[2]
|
|
Net clk_000_d_2__n CLK_000_D[2]
|
|
Net clk_000_d_4__n CLK_000_D[4]
|
|
Net pos_clk_ipl_n pos_clk.ipl
|
|
Net size_dma_0__n SIZE_DMA[0]
|
|
Net size_dma_1__n SIZE_DMA[1]
|
|
Net a_decode_c_16__n A_DECODE_c[16]
|
|
Net a_decode_16__n A_DECODE[16]
|
|
Net pos_clk_cycle_dma_5_1_1__n pos_clk.CYCLE_DMA_5_1[1]
|
|
Net sm_amiga_6__n SM_AMIGA[6]
|
|
Net a_decode_c_17__n A_DECODE_c[17]
|
|
Net a_decode_17__n A_DECODE[17]
|
|
Net sm_amiga_4__n SM_AMIGA[4]
|
|
Net a_decode_c_18__n A_DECODE_c[18]
|
|
Net sm_amiga_1__n SM_AMIGA[1]
|
|
Net a_decode_18__n A_DECODE[18]
|
|
Net sm_amiga_0__n SM_AMIGA[0]
|
|
Net a_decode_c_19__n A_DECODE_c[19]
|
|
Net cycle_dma_0__n CYCLE_DMA[0]
|
|
Net a_decode_19__n A_DECODE[19]
|
|
Net cycle_dma_1__n CYCLE_DMA[1]
|
|
Net a_decode_c_20__n A_DECODE_c[20]
|
|
Net a_decode_20__n A_DECODE[20]
|
|
Net a_decode_c_21__n A_DECODE_c[21]
|
|
Net pos_clk_un9_clk_000_pe_n pos_clk.un9_clk_000_pe
|
|
Net a_decode_21__n A_DECODE[21]
|
|
Net sm_amiga_5__n SM_AMIGA[5]
|
|
Net a_decode_c_22__n A_DECODE_c[22]
|
|
Net sm_amiga_3__n SM_AMIGA[3]
|
|
Net a_decode_22__n A_DECODE[22]
|
|
Net sm_amiga_2__n SM_AMIGA[2]
|
|
Net a_decode_c_23__n A_DECODE_c[23]
|
|
Net pos_clk_cycle_dma_5_1__n pos_clk.CYCLE_DMA_5[1]
|
|
Net a_c_0__n A_c[0]
|
|
Net a_0__n A[0]
|
|
Net a_c_1__n A_c[1]
|
|
Net pos_clk_ipl_1_n pos_clk.ipl_1
|
|
Net ds_000_dma_0_un3_n DS_000_DMA_0.un3
|
|
Net ds_000_dma_0_un1_n DS_000_DMA_0.un1
|
|
Net ds_000_dma_0_un0_n DS_000_DMA_0.un0
|
|
Net as_000_dma_0_un3_n AS_000_DMA_0.un3
|
|
Net as_000_dma_0_un1_n AS_000_DMA_0.un1
|
|
Net as_000_dma_0_un0_n AS_000_DMA_0.un0
|
|
Net uds_000_int_0_un3_n UDS_000_INT_0.un3
|
|
Net uds_000_int_0_un1_n UDS_000_INT_0.un1
|
|
Net uds_000_int_0_un0_n UDS_000_INT_0.un0
|
|
Net bg_000_0_un3_n BG_000_0.un3
|
|
Net bg_000_0_un1_n BG_000_0.un1
|
|
Net bg_000_0_un0_n BG_000_0.un0
|
|
Net lds_000_int_0_un3_n LDS_000_INT_0.un3
|
|
Net lds_000_int_0_un1_n LDS_000_INT_0.un1
|
|
Net lds_000_int_0_un0_n LDS_000_INT_0.un0
|
|
Net as_030_d1_0_un3_n AS_030_D1_0.un3
|
|
Net as_030_d1_0_un1_n AS_030_D1_0.un1
|
|
Net as_030_d1_0_un0_n AS_030_D1_0.un0
|
|
Net rw_000_int_0_un3_n RW_000_INT_0.un3
|
|
Net rw_000_int_0_un1_n RW_000_INT_0.un1
|
|
Net ipl_030_c_0__n IPL_030_c[0]
|
|
Net rw_000_int_0_un0_n RW_000_INT_0.un0
|
|
Net ipl_030_0__n IPL_030[0]
|
|
Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3
|
|
Net ipl_030_c_1__n IPL_030_c[1]
|
|
Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1
|
|
Net sm_amiga_i_7__n SM_AMIGA_i[7]
|
|
Net ipl_030_1__n IPL_030[1]
|
|
Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0
|
|
Net pos_clk_size_dma_6_0__n pos_clk.SIZE_DMA_6[0]
|
|
Net ipl_030_c_2__n IPL_030_c[2]
|
|
Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3
|
|
Net pos_clk_size_dma_6_1__n pos_clk.SIZE_DMA_6[1]
|
|
Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1
|
|
Net cpu_est_2_1__n cpu_est_2[1]
|
|
Net ipl_c_0__n IPL_c[0]
|
|
Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0
|
|
Net cpu_est_2_2__n cpu_est_2[2]
|
|
Net ipl_0__n IPL[0]
|
|
Net cpu_est_0_1__un3_n cpu_est_0_1_.un3
|
|
Net cpu_est_2_3__n cpu_est_2[3]
|
|
Net ipl_c_1__n IPL_c[1]
|
|
Net cpu_est_0_1__un1_n cpu_est_0_1_.un1
|
|
Net ipl_1__n IPL[1]
|
|
Net cpu_est_0_1__un0_n cpu_est_0_1_.un0
|
|
Net ipl_c_2__n IPL_c[2]
|
|
Net cpu_est_0_2__un3_n cpu_est_0_2_.un3
|
|
Net cpu_est_0_2__un1_n cpu_est_0_2_.un1
|
|
Net cpu_est_0_2__un0_n cpu_est_0_2_.un0
|
|
Net cpu_est_0_3__un3_n cpu_est_0_3_.un3
|
|
Net cpu_est_0_3__un1_n cpu_est_0_3_.un1
|
|
Net cpu_est_0_3__un0_n cpu_est_0_3_.un0
|
|
Net ipl_030_0_0__un3_n IPL_030_0_0_.un3
|
|
Net ipl_030_0_0__un1_n IPL_030_0_0_.un1
|
|
Net ipl_030_0_0__un0_n IPL_030_0_0_.un0
|
|
Net ipl_030_0_1__un3_n IPL_030_0_1_.un3
|
|
Net ipl_030_0_1__un1_n IPL_030_0_1_.un1
|
|
Net ipl_030_0_1__un0_n IPL_030_0_1_.un0
|
|
Net ipl_030_0_2__un3_n IPL_030_0_2_.un3
|
|
Net ipl_030_0_2__un1_n IPL_030_0_2_.un1
|
|
Net ipl_030_0_2__un0_n IPL_030_0_2_.un0
|
|
Net ds_000_enable_0_un3_n DS_000_ENABLE_0.un3
|
|
Net fc_c_0__n FC_c[0]
|
|
Net ds_000_enable_0_un1_n DS_000_ENABLE_0.un1
|
|
Net fc_0__n FC[0]
|
|
Net ds_000_enable_0_un0_n DS_000_ENABLE_0.un0
|
|
Net fc_c_1__n FC_c[1]
|
|
Net vma_int_0_un3_n VMA_INT_0.un3
|
|
Net vma_int_0_un1_n VMA_INT_0.un1
|
|
Net vma_int_0_un0_n VMA_INT_0.un0
|
|
Net a_decode_15__n A_DECODE[15]
|
|
Net a_decode_14__n A_DECODE[14]
|
|
Net a_decode_13__n A_DECODE[13]
|
|
Net a_decode_12__n A_DECODE[12]
|
|
Net a_decode_11__n A_DECODE[11]
|
|
Net a_decode_10__n A_DECODE[10]
|
|
Net a_decode_9__n A_DECODE[9]
|
|
Net pos_clk_un2_i_n pos_clk.un2_i
|
|
Net a_decode_8__n A_DECODE[8]
|
|
Net a_decode_7__n A_DECODE[7]
|
|
Net a_decode_6__n A_DECODE[6]
|
|
Net a_decode_5__n A_DECODE[5]
|
|
Net pos_clk_un9_bg_030_0_n pos_clk.un9_bg_030_0
|
|
Net a_decode_4__n A_DECODE[4]
|
|
Net a_decode_3__n A_DECODE[3]
|
|
Net a_decode_2__n A_DECODE[2]
|
|
Net a_c_i_0__n A_c_i[0]
|
|
Net size_c_i_1__n SIZE_c_i[1]
|
|
Net pos_clk_un10_sm_amiga_i_n pos_clk.un10_sm_amiga_i
|
|
Net pos_clk_rw_000_int_5_n pos_clk.RW_000_INT_5
|
|
Net pos_clk_un6_bgack_000_n pos_clk.un6_bgack_000
|
|
Net pos_clk_un6_bgack_000_0_n pos_clk.un6_bgack_000_0
|
|
Net pos_clk_rw_000_int_5_0_n pos_clk.RW_000_INT_5_0
|
|
Net pos_clk_un9_bg_030_n pos_clk.un9_bg_030
|
|
Net un1_cycle_dma_2__n un1_CYCLE_DMA[2]
|
|
Net pos_clk_un2_n pos_clk.un2
|
|
Net clk_000_d_i_3__n CLK_000_D_i[3]
|
|
Net cycle_dma_i_0__n CYCLE_DMA_i[0]
|
|
Net cycle_dma_i_1__n CYCLE_DMA_i[1]
|
|
Net a_i_1__n A_i[1]
|
|
Net a_decode_i_19__n A_DECODE_i[19]
|
|
Net a_decode_i_18__n A_DECODE_i[18]
|
|
Net a_decode_i_16__n A_DECODE_i[16]
|
|
Net sm_amiga_i_0__n SM_AMIGA_i[0]
|
|
Net sm_amiga_i_5__n SM_AMIGA_i[5]
|
|
Net sm_amiga_i_6__n SM_AMIGA_i[6]
|
|
Net sm_amiga_i_i_7__n SM_AMIGA_i_i[7]
|
|
Net sm_amiga_i_1__n SM_AMIGA_i[1]
|
|
Net cpu_est_i_0__n cpu_est_i[0]
|
|
Net cpu_est_i_3__n cpu_est_i[3]
|
|
Net sm_amiga_i_3__n SM_AMIGA_i[3]
|
|
Net sm_amiga_i_4__n SM_AMIGA_i[4]
|
|
Net cpu_est_i_1__n cpu_est_i[1]
|
|
Net clk_000_d_i_0__n CLK_000_D_i[0]
|
|
Net clk_000_d_i_1__n CLK_000_D_i[1]
|
|
Net cpu_est_i_2__n cpu_est_i[2]
|
|
Net sm_amiga_i_2__n SM_AMIGA_i[2]
|
|
Net ahigh_i_30__n AHIGH_i[30]
|
|
Net ahigh_i_31__n AHIGH_i[31]
|
|
Net ahigh_i_28__n AHIGH_i[28]
|
|
Net pos_clk_size_dma_6_0_1__n pos_clk.SIZE_DMA_6_0[1]
|
|
Net ahigh_i_29__n AHIGH_i[29]
|
|
Net ahigh_i_26__n AHIGH_i[26]
|
|
Net pos_clk_size_dma_6_0_0__n pos_clk.SIZE_DMA_6_0[0]
|
|
Net ahigh_i_27__n AHIGH_i[27]
|
|
Net ahigh_i_24__n AHIGH_i[24]
|
|
Net ahigh_i_25__n AHIGH_i[25]
|
|
Net cpu_est_2_0_3__n cpu_est_2_0[3]
|
|
Net cpu_est_2_0_2__n cpu_est_2_0[2]
|
|
Net cpu_est_2_0_1__n cpu_est_2_0[1]
|
|
Net pos_clk_un9_clk_000_pe_0_n pos_clk.un9_clk_000_pe_0
|
|
End
|
|
Section Type Name
|
|
// ----------------------------------------------------------------------
|
|
Input A_DECODE_23_
|
|
Input IPL_2_
|
|
Input FC_1_
|
|
Input nEXP_SPACE
|
|
Input BG_030
|
|
Input BGACK_000
|
|
Input CLK_030
|
|
Input CLK_000
|
|
Input CLK_OSZI
|
|
Input FPU_SENSE
|
|
Input DTACK
|
|
Input VPA
|
|
Input RST
|
|
Input RESET
|
|
Input A_DECODE_22_
|
|
Input A_DECODE_21_
|
|
Input A_DECODE_20_
|
|
Input A_DECODE_19_
|
|
Input A_DECODE_18_
|
|
Input A_DECODE_17_
|
|
Input A_DECODE_16_
|
|
Input A_DECODE_15_
|
|
Input A_DECODE_14_
|
|
Input A_DECODE_13_
|
|
Input A_DECODE_12_
|
|
Input A_DECODE_11_
|
|
Input A_DECODE_10_
|
|
Input A_DECODE_9_
|
|
Input A_DECODE_8_
|
|
Input A_DECODE_7_
|
|
Input A_DECODE_6_
|
|
Input A_DECODE_5_
|
|
Input A_DECODE_4_
|
|
Input A_DECODE_3_
|
|
Input A_DECODE_2_
|
|
Input IPL_1_
|
|
Input IPL_0_
|
|
Input FC_0_
|
|
Input A_1_
|
|
Output IPL_030_2_
|
|
Output DS_030
|
|
Output BG_000
|
|
Output BGACK_030
|
|
Output CLK_DIV_OUT
|
|
Output CLK_EXP
|
|
Output FPU_CS
|
|
Output DSACK1
|
|
Output AVEC
|
|
Output E
|
|
Output VMA
|
|
Output AMIGA_ADDR_ENABLE
|
|
Output AMIGA_BUS_DATA_DIR
|
|
Output AMIGA_BUS_ENABLE_LOW
|
|
Output AMIGA_BUS_ENABLE_HIGH
|
|
Output CIIN
|
|
Output IPL_030_1_
|
|
Output IPL_030_0_
|
|
Bidi SIZE_1_
|
|
Bidi AHIGH_31_
|
|
Bidi AS_030
|
|
Bidi AS_000
|
|
Bidi RW_000
|
|
Bidi UDS_000
|
|
Bidi LDS_000
|
|
Bidi BERR
|
|
Bidi RW
|
|
Bidi SIZE_0_
|
|
Bidi AHIGH_30_
|
|
Bidi AHIGH_29_
|
|
Bidi AHIGH_28_
|
|
Bidi AHIGH_27_
|
|
Bidi AHIGH_26_
|
|
Bidi AHIGH_25_
|
|
Bidi AHIGH_24_
|
|
Bidi A_0_
|
|
End
|