mirror of https://github.com/kr239/68030tk.git
71 lines
5.1 KiB
Plaintext
71 lines
5.1 KiB
Plaintext
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
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#install: E:\ispLEVER_Classic2_0\synpbase
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#OS: Windows 7 6.2
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#Hostname: DEEPTHOUGHT
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#Implementation: logic
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$ Start of Compile
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#Sat Dec 30 00:43:29 2017
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Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
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@N|Running in 64-bit mode
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Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
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@N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N:"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
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File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
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VHDL syntax check successful!
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File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
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@N: CD630 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
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@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":70:10:70:11|Using sequential encoding for type sm_e
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@N: CD233 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":87:14:87:15|Using sequential encoding for type sm_68000
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@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":130:7:130:17|Signal clk_out_pre is undriven
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@W: CD638 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":134:7:134:15|Signal clk_030_h is undriven
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Post processing for work.bus68030.behavioral
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register DTACK_DMA_4
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register CLK_030_PE_2(1 downto 0)
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register AS_000_D0_3
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register RESET_OUT_4
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register RST_DLY_6(2 downto 0)
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register DS_030_D0_3
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register nEXP_SPACE_D0_3
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning register BGACK_030_INT_PRE_2
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_OUT_EXP_INT_1
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":128:36:128:38|Pruning register CLK_OUT_PRE_25_3
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@W: CL169 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":158:2:158:3|Pruning register CLK_030_D0_2
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@W: CL271 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ...
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@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Trying to extract state machine for register SM_AMIGA
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Extracted state machine for register SM_AMIGA
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State machine has 8 reachable states with original encodings of:
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000
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001
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010
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011
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100
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101
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110
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111
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@N: CL201 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":133:38:133:40|Trying to extract state machine for register cpu_est
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@W: CL246 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused
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@W: CL159 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":34:1:34:7|Input CLK_030 is unused
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@W: CL158 :"C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd":50:1:50:5|Inout RESET is unused
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@END
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sat Dec 30 00:43:29 2017
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###########################################################]
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Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
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@N|Running in 64-bit mode
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File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sat Dec 30 00:43:31 2017
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###########################################################]
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