68030tk/Logic/synlog/bus68030_fpga_mapper.srr

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Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N: MF248 |Running in 64-bit mode.
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
001 -> 00000011
010 -> 00000101
011 -> 00001001
100 -> 00010001
101 -> 00100001
110 -> 01000001
111 -> 10000001
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Resource Usage Report
Simple gate primitives:
DFF 52 uses
BI_DIR 18 uses
BUFTH 4 uses
IBUF 39 uses
OBUF 14 uses
AND2 221 uses
INV 203 uses
OR2 17 uses
XOR2 4 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Dec 30 00:43:31 2017
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