68030tk/Logic/68030_tk.tlg

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// Batch Timer Log File (Release Version: 1.7.00.05.28.13)
// Project = 68030_tk
// Family = mach4a
// Device = M4A5-128/64
// Speed = -10
// Voltage = 5.0
// Operating Condition = COM
// Data sheet version = RevD-8/2000
// Pass Bidirection = OFF
// Pass S/R = OFF
// Pass Latch = OFF
// Pass Clock = OFF
// Maximum Paths = 20
// T_SU Endpoints D/T inputs = ON
// T_SU Endpoints CE inputs = OFF
// T_SU Endpoints S/R inputs = OFF
// T_SU Endpoints RAM gated = ON
// Fmax of CE = ON
// Fmax of RAM = ON
// Location(From => To)
// Pin number: numeric number preceded by "p", BGA number as is
// Macrocell number: Segment#,GLB#,Macrocell#
// Segment#: starts from 0 (if applicable)
// GLB#: starts from A..Z, AA..ZZ
// Macrocell#: starts from 0 to 31
// Register-to-register critical path delay: 9.5 ns
// - 3.0 tCOSi E.C ==> E.Q
// - 0.0 E.Q ==> cpu_est_1_.T
// - 6.5 tSST cpu_est_1_.T ==> cpu_est_1_.C