mirror of https://github.com/kr239/68030tk.git
538 lines
36 KiB
Plaintext
538 lines
36 KiB
Plaintext
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Timing Report for STAMP
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// Project = 68030_tk
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// Family = mach4a
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// Device = M4A5-128/64
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// Speed = -10
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// Voltage = 5.0
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// Operating Condition = COM
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// Data sheet version = RevD-8/2000
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// Pass Bidirection = OFF
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// Pass S/R = OFF
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// Pass Latch = OFF
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// T_SU Endpoints D/T inputs = ON
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// T_SU Endpoints CE inputs = OFF
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// T_SU Endpoints S/R inputs = OFF
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// T_SU Endpoints RAM gated = ON
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// Fmax of CE = ON
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// Fmax of RAM = ON
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// Location(From => To)
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// Pin number: numeric number preceded by "p", BGA number as is
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// Macrocell number: Segment#,GLB#,Macrocell#
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// Segment#: starts from 0 (if applicable)
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// GLB#: starts from A..Z, AA..ZZ
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// Macrocell#: starts from 0 to 31
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Section IO
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//DESTINATION NODES;
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A0 [bidi]
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AS_000 [bidi]
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AS_030 [bidi]
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DSACK[1] [bidi]
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DS_030 [bidi]
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DTACK [bidi]
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LDS_000 [bidi]
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SIZE[0] [bidi]
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SIZE[1] [bidi]
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UDS_000 [bidi]
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AMIGA_BUS_DATA_DIR [out]
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AMIGA_BUS_ENABLE [out]
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AMIGA_BUS_ENABLE_LOW [out]
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AVEC [out]
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AVEC_EXP [out]
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BERR [out]
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BGACK_030 [out]
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BG_000 [out]
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CIIN [out]
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CLK_DIV_OUT [out]
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CLK_EXP [out]
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DSACK[0] [out]
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E [out]
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FPU_CS [out]
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IPL_030[0] [out]
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IPL_030[1] [out]
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IPL_030[2] [out]
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RESET [out]
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VMA [out]
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A0.C [reg]
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AMIGA_BUS_ENABLE.C [reg]
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AS_000.C [reg]
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AS_030.C [reg]
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BGACK_030.C [reg]
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BG_000.C [reg]
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CLK_CNT_N_0_.C [reg]
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CLK_CNT_N_1_.C [reg]
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CLK_CNT_P_0_.C [reg]
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CLK_CNT_P_1_.C [reg]
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CLK_DIV_OUT.C [reg]
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CLK_EXP.C [reg]
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DSACK_1_.C [reg]
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DS_030.C [reg]
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E.C [reg]
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FPU_CS.C [reg]
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IPL_030_0_.C [reg]
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IPL_030_1_.C [reg]
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IPL_030_2_.C [reg]
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LDS_000.C [reg]
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RESET.C [reg]
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SIZE_0_.C [reg]
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SIZE_1_.C [reg]
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SM_AMIGA_0_.C [reg]
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SM_AMIGA_1_.C [reg]
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SM_AMIGA_2_.C [reg]
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SM_AMIGA_3_.C [reg]
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SM_AMIGA_4_.C [reg]
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SM_AMIGA_5_.C [reg]
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SM_AMIGA_6_.C [reg]
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SM_AMIGA_7_.C [reg]
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UDS_000.C [reg]
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VMA.C [reg]
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cpu_est_0_.C [reg]
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cpu_est_1_.C [reg]
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cpu_est_2_.C [reg]
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inst_AS_030_000_SYNC.C [reg]
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inst_BGACK_030_INT_D.C [reg]
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inst_CLK_000_D0.C [reg]
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inst_CLK_000_D1.C [reg]
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inst_CLK_000_D2.C [reg]
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inst_CLK_000_D3.C [reg]
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inst_CLK_000_D4.C [reg]
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inst_CLK_000_D5.C [reg]
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inst_CLK_000_D6.C [reg]
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inst_CLK_OUT_PRE.C [reg]
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inst_DTACK_SYNC.C [reg]
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inst_VPA_D.C [reg]
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inst_VPA_SYNC.C [reg]
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A0.D [reg]
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AMIGA_BUS_ENABLE.D [reg]
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AS_000.D [reg]
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AS_030.D [reg]
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BGACK_030.D [reg]
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BG_000.D [reg]
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CLK_CNT_N_0_.D [reg]
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CLK_CNT_N_1_.D [reg]
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CLK_CNT_P_0_.D [reg]
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CLK_CNT_P_1_.D [reg]
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CLK_DIV_OUT.D [reg]
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CLK_EXP.D [reg]
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DSACK_1_.D [reg]
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DS_030.D [reg]
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E.D.X1 [reg]
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E.D.X2 [reg]
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FPU_CS.D [reg]
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IPL_030_0_.D [reg]
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IPL_030_1_.D [reg]
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IPL_030_2_.D [reg]
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LDS_000.D [reg]
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RESET.D [reg]
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SIZE_0_.D [reg]
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SIZE_1_.D [reg]
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SM_AMIGA_0_.D [reg]
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SM_AMIGA_1_.D [reg]
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SM_AMIGA_2_.D [reg]
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SM_AMIGA_3_.D [reg]
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SM_AMIGA_4_.D [reg]
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SM_AMIGA_5_.D [reg]
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SM_AMIGA_6_.D [reg]
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SM_AMIGA_7_.D [reg]
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UDS_000.D [reg]
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VMA.D.X1 [reg]
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VMA.D.X2 [reg]
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cpu_est_0_.D [reg]
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cpu_est_1_.T [reg]
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cpu_est_2_.D.X1 [reg]
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cpu_est_2_.D.X2 [reg]
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inst_AS_030_000_SYNC.D [reg]
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inst_BGACK_030_INT_D.D [reg]
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inst_CLK_000_D0.D [reg]
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inst_CLK_000_D1.D [reg]
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inst_CLK_000_D2.D [reg]
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inst_CLK_000_D3.D [reg]
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inst_CLK_000_D4.D [reg]
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inst_CLK_000_D5.D [reg]
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inst_CLK_000_D6.D [reg]
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inst_CLK_OUT_PRE.D [reg]
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inst_DTACK_SYNC.D [reg]
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inst_VPA_D.D [reg]
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inst_VPA_SYNC.D [reg]
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//SOURCE NODES;
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A[16] [in]
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A[17] [in]
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A[18] [in]
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A[19] [in]
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A[20] [in]
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A[21] [in]
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A[22] [in]
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A[23] [in]
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A[24] [in]
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A[25] [in]
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A[26] [in]
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A[27] [in]
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A[28] [in]
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A[29] [in]
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A[30] [in]
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A[31] [in]
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BGACK_000 [in]
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BG_030 [in]
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CLK_000 [in]
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CLK_030 [in]
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CLK_OSZI [in]
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FC[0] [in]
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FC[1] [in]
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IPL[0] [in]
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IPL[1] [in]
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IPL[2] [in]
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RST [in]
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RW [in]
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VPA [in]
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nEXP_SPACE [in]
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A0.Q [reg]
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AMIGA_BUS_ENABLE.Q [reg]
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AS_000.Q [reg]
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AS_030.Q [reg]
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BGACK_030.Q [reg]
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BG_000.Q [reg]
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CLK_CNT_N_0_.Q [reg]
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CLK_CNT_N_1_.Q [reg]
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CLK_CNT_P_0_.Q [reg]
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CLK_CNT_P_1_.Q [reg]
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CLK_DIV_OUT.Q [reg]
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CLK_EXP.Q [reg]
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DSACK_1_.Q [reg]
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DS_030.Q [reg]
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E.Q [reg]
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FPU_CS.Q [reg]
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IPL_030_0_.Q [reg]
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IPL_030_1_.Q [reg]
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IPL_030_2_.Q [reg]
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LDS_000.Q [reg]
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RESET.Q [reg]
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SIZE_0_.Q [reg]
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SIZE_1_.Q [reg]
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SM_AMIGA_0_.Q [reg]
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SM_AMIGA_1_.Q [reg]
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SM_AMIGA_2_.Q [reg]
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SM_AMIGA_3_.Q [reg]
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SM_AMIGA_4_.Q [reg]
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SM_AMIGA_5_.Q [reg]
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SM_AMIGA_6_.Q [reg]
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SM_AMIGA_7_.Q [reg]
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UDS_000.Q [reg]
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VMA.Q [reg]
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cpu_est_0_.Q [reg]
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cpu_est_1_.Q [reg]
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cpu_est_2_.Q [reg]
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inst_AS_030_000_SYNC.Q [reg]
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inst_BGACK_030_INT_D.Q [reg]
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inst_CLK_000_D0.Q [reg]
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inst_CLK_000_D1.Q [reg]
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inst_CLK_000_D2.Q [reg]
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inst_CLK_000_D3.Q [reg]
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inst_CLK_000_D4.Q [reg]
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inst_CLK_000_D5.Q [reg]
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inst_CLK_000_D6.Q [reg]
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inst_CLK_OUT_PRE.Q [reg]
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inst_DTACK_SYNC.Q [reg]
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inst_VPA_D.Q [reg]
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inst_VPA_SYNC.Q [reg]
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Section fMAX
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Maximum Operating Frequency: 105.26 MHz
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Clock Source From: CLK_OSZI
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Logic Levels: 1
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Path Delay: 9.5 ns
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Path Expansion Source Destination
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============== ====== ===========
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3.0 tCOSi E.C E.Q
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0.0 E.Q cpu_est_1_.T
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6.5 tSST cpu_est_1_.T cpu_est_1_.C
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Clock Source From: CLK_OSZI
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Delay Level Location(From => To) Source Destination Destination_Clock
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===== ===== ==================== ====== =========== =================
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9.5 1 G4 => G12 E.C cpu_est_1_.T CLK_OSZI
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9.5 1 B9 => G12 cpu_est_0_.C cpu_est_1_.T CLK_OSZI
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9.5 1 G12 => G12 cpu_est_1_.C cpu_est_1_.T CLK_OSZI
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9.5 1 G5 => G12 cpu_est_2_.C cpu_est_1_.T CLK_OSZI
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9.5 1 F0 => G12 inst_CLK_000_D0.C cpu_est_1_.T CLK_OSZI
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9.5 1 H5 => G12 inst_CLK_000_D1.C cpu_est_1_.T CLK_OSZI
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8.5 1 G8 => G8 A0.C A0.D CLK_OSZI
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8.5 1 D5 => D5 AMIGA_BUS_ENABLE.C AMIGA_BUS_ENABLE.D CLK_OSZI
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8.5 1 D4 => D4 AS_000.C AS_000.D CLK_OSZI
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8.5 1 D4 => C4 AS_000.C SM_AMIGA_0_.D CLK_OSZI
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8.5 1 D4 => B5 AS_000.C SM_AMIGA_7_.D CLK_OSZI
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8.5 1 D4 => D1 AS_000.C VMA.D.X1 CLK_OSZI
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8.5 1 H8 => H8 AS_030.C AS_030.D CLK_OSZI
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8.5 1 H8 => A0 AS_030.C DS_030.D CLK_OSZI
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8.5 1 H4 => G8 BGACK_030.C A0.D CLK_OSZI
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8.5 1 H4 => D5 BGACK_030.C AMIGA_BUS_ENABLE.D CLK_OSZI
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8.5 1 H4 => H8 BGACK_030.C AS_030.D CLK_OSZI
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8.5 1 H4 => H4 BGACK_030.C BGACK_030.D CLK_OSZI
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8.5 1 H4 => A0 BGACK_030.C DS_030.D CLK_OSZI
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8.5 1 H4 => G0 BGACK_030.C SIZE_0_.D CLK_OSZI
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8.5 1 H4 => H0 BGACK_030.C SIZE_1_.D CLK_OSZI
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8.5 1 H4 => A12 BGACK_030.C inst_BGACK_030_INT_D.D CLK_OSZI
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8.5 1 D13 => D13 BG_000.C BG_000.D CLK_OSZI
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8.5 1 E1 => E1 CLK_CNT_N_0_.C CLK_CNT_N_0_.D CLK_OSZI
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8.5 1 E1 => G9 CLK_CNT_N_0_.C CLK_CNT_N_1_.D CLK_OSZI
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8.5 1 E1 => A1 CLK_CNT_N_0_.C inst_CLK_OUT_PRE.D CLK_OSZI
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8.5 1 G9 => E1 CLK_CNT_N_1_.C CLK_CNT_N_0_.D CLK_OSZI
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8.5 1 G9 => A1 CLK_CNT_N_1_.C inst_CLK_OUT_PRE.D CLK_OSZI
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8.5 1 F1 => F1 CLK_CNT_P_0_.C CLK_CNT_P_0_.D CLK_OSZI
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8.5 1 F1 => F9 CLK_CNT_P_0_.C CLK_CNT_P_1_.D CLK_OSZI
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8.5 1 F1 => A1 CLK_CNT_P_0_.C inst_CLK_OUT_PRE.D CLK_OSZI
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8.5 1 F9 => F1 CLK_CNT_P_1_.C CLK_CNT_P_0_.D CLK_OSZI
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8.5 1 F9 => A1 CLK_CNT_P_1_.C inst_CLK_OUT_PRE.D CLK_OSZI
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8.5 1 H12 => H12 DSACK_1_.C DSACK_1_.D CLK_OSZI
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8.5 1 A0 => A0 DS_030.C DS_030.D CLK_OSZI
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8.5 1 G4 => G4 E.C E.D.X1 CLK_OSZI
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8.5 1 G4 => G4 E.C E.D.X2 CLK_OSZI
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8.5 1 G4 => D1 E.C VMA.D.X1 CLK_OSZI
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8.5 1 G4 => G5 E.C cpu_est_2_.D.X1 CLK_OSZI
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8.5 1 G4 => C5 E.C inst_VPA_SYNC.D CLK_OSZI
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8.5 1 H1 => H1 FPU_CS.C FPU_CS.D CLK_OSZI
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8.5 1 B8 => B8 IPL_030_0_.C IPL_030_0_.D CLK_OSZI
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8.5 1 B12 => B12 IPL_030_1_.C IPL_030_1_.D CLK_OSZI
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8.5 1 B4 => B4 IPL_030_2_.C IPL_030_2_.D CLK_OSZI
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8.5 1 D8 => D8 LDS_000.C LDS_000.D CLK_OSZI
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8.5 1 G0 => G0 SIZE_0_.C SIZE_0_.D CLK_OSZI
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8.5 1 H0 => H0 SIZE_1_.C SIZE_1_.D CLK_OSZI
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8.5 1 C4 => D5 SM_AMIGA_0_.C AMIGA_BUS_ENABLE.D CLK_OSZI
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8.5 1 C4 => C4 SM_AMIGA_0_.C SM_AMIGA_0_.D CLK_OSZI
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8.5 1 C4 => B5 SM_AMIGA_0_.C SM_AMIGA_7_.D CLK_OSZI
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8.5 1 A8 => D5 SM_AMIGA_1_.C AMIGA_BUS_ENABLE.D CLK_OSZI
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8.5 1 A8 => H12 SM_AMIGA_1_.C DSACK_1_.D CLK_OSZI
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8.5 1 A8 => C4 SM_AMIGA_1_.C SM_AMIGA_0_.D CLK_OSZI
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8.5 1 A8 => A8 SM_AMIGA_1_.C SM_AMIGA_1_.D CLK_OSZI
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8.5 1 A8 => F12 SM_AMIGA_1_.C inst_AS_030_000_SYNC.D CLK_OSZI
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8.5 1 C8 => A8 SM_AMIGA_2_.C SM_AMIGA_1_.D CLK_OSZI
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8.5 1 C8 => C8 SM_AMIGA_2_.C SM_AMIGA_2_.D CLK_OSZI
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8.5 1 C1 => C8 SM_AMIGA_3_.C SM_AMIGA_2_.D CLK_OSZI
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8.5 1 C1 => C1 SM_AMIGA_3_.C SM_AMIGA_3_.D CLK_OSZI
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8.5 1 C1 => C9 SM_AMIGA_3_.C inst_DTACK_SYNC.D CLK_OSZI
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8.5 1 C1 => C5 SM_AMIGA_3_.C inst_VPA_SYNC.D CLK_OSZI
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8.5 1 F8 => D8 SM_AMIGA_4_.C LDS_000.D CLK_OSZI
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8.5 1 F8 => C1 SM_AMIGA_4_.C SM_AMIGA_3_.D CLK_OSZI
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8.5 1 F8 => F8 SM_AMIGA_4_.C SM_AMIGA_4_.D CLK_OSZI
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8.5 1 F8 => D12 SM_AMIGA_4_.C UDS_000.D CLK_OSZI
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8.5 1 F5 => D4 SM_AMIGA_5_.C AS_000.D CLK_OSZI
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8.5 1 F5 => D8 SM_AMIGA_5_.C LDS_000.D CLK_OSZI
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8.5 1 F5 => F8 SM_AMIGA_5_.C SM_AMIGA_4_.D CLK_OSZI
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8.5 1 F5 => F5 SM_AMIGA_5_.C SM_AMIGA_5_.D CLK_OSZI
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8.5 1 F5 => D12 SM_AMIGA_5_.C UDS_000.D CLK_OSZI
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8.5 1 B13 => D5 SM_AMIGA_6_.C AMIGA_BUS_ENABLE.D CLK_OSZI
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8.5 1 B13 => F5 SM_AMIGA_6_.C SM_AMIGA_5_.D CLK_OSZI
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8.5 1 B13 => B13 SM_AMIGA_6_.C SM_AMIGA_6_.D CLK_OSZI
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8.5 1 B13 => B5 SM_AMIGA_6_.C SM_AMIGA_7_.D CLK_OSZI
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8.5 1 B13 => F12 SM_AMIGA_6_.C inst_AS_030_000_SYNC.D CLK_OSZI
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8.5 1 B5 => D13 SM_AMIGA_7_.C BG_000.D CLK_OSZI
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8.5 1 B5 => B13 SM_AMIGA_7_.C SM_AMIGA_6_.D CLK_OSZI
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8.5 1 B5 => B5 SM_AMIGA_7_.C SM_AMIGA_7_.D CLK_OSZI
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8.5 1 B5 => F12 SM_AMIGA_7_.C inst_AS_030_000_SYNC.D CLK_OSZI
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8.5 1 D12 => D12 UDS_000.C UDS_000.D CLK_OSZI
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8.5 1 D1 => D1 VMA.C VMA.D.X1 CLK_OSZI
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8.5 1 D1 => D1 VMA.C VMA.D.X2 CLK_OSZI
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8.5 1 D1 => C5 VMA.C inst_VPA_SYNC.D CLK_OSZI
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8.5 1 B9 => G4 cpu_est_0_.C E.D.X1 CLK_OSZI
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8.5 1 B9 => D1 cpu_est_0_.C VMA.D.X1 CLK_OSZI
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8.5 1 B9 => D1 cpu_est_0_.C VMA.D.X2 CLK_OSZI
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8.5 1 B9 => B9 cpu_est_0_.C cpu_est_0_.D CLK_OSZI
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8.5 1 B9 => G5 cpu_est_0_.C cpu_est_2_.D.X1 CLK_OSZI
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8.5 1 G12 => G4 cpu_est_1_.C E.D.X1 CLK_OSZI
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8.5 1 G12 => D1 cpu_est_1_.C VMA.D.X1 CLK_OSZI
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8.5 1 G12 => D1 cpu_est_1_.C VMA.D.X2 CLK_OSZI
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8.5 1 G12 => G5 cpu_est_1_.C cpu_est_2_.D.X1 CLK_OSZI
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8.5 1 G12 => C5 cpu_est_1_.C inst_VPA_SYNC.D CLK_OSZI
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8.5 1 G5 => G4 cpu_est_2_.C E.D.X1 CLK_OSZI
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8.5 1 G5 => D1 cpu_est_2_.C VMA.D.X1 CLK_OSZI
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8.5 1 G5 => G5 cpu_est_2_.C cpu_est_2_.D.X1 CLK_OSZI
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8.5 1 G5 => G5 cpu_est_2_.C cpu_est_2_.D.X2 CLK_OSZI
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8.5 1 F12 => B13 inst_AS_030_000_SYNC.C SM_AMIGA_6_.D CLK_OSZI
|
|
8.5 1 F12 => B5 inst_AS_030_000_SYNC.C SM_AMIGA_7_.D CLK_OSZI
|
|
8.5 1 F12 => F12 inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.D CLK_OSZI
|
|
8.5 1 A12 => G8 inst_BGACK_030_INT_D.C A0.D CLK_OSZI
|
|
8.5 1 A12 => D5 inst_BGACK_030_INT_D.C AMIGA_BUS_ENABLE.D CLK_OSZI
|
|
8.5 1 A12 => H8 inst_BGACK_030_INT_D.C AS_030.D CLK_OSZI
|
|
8.5 1 A12 => A0 inst_BGACK_030_INT_D.C DS_030.D CLK_OSZI
|
|
8.5 1 A12 => G0 inst_BGACK_030_INT_D.C SIZE_0_.D CLK_OSZI
|
|
8.5 1 A12 => H0 inst_BGACK_030_INT_D.C SIZE_1_.D CLK_OSZI
|
|
8.5 1 F0 => H4 inst_CLK_000_D0.C BGACK_030.D CLK_OSZI
|
|
8.5 1 F0 => G4 inst_CLK_000_D0.C E.D.X1 CLK_OSZI
|
|
8.5 1 F0 => B8 inst_CLK_000_D0.C IPL_030_0_.D CLK_OSZI
|
|
8.5 1 F0 => B12 inst_CLK_000_D0.C IPL_030_1_.D CLK_OSZI
|
|
8.5 1 F0 => B4 inst_CLK_000_D0.C IPL_030_2_.D CLK_OSZI
|
|
8.5 1 F0 => C4 inst_CLK_000_D0.C SM_AMIGA_0_.D CLK_OSZI
|
|
8.5 1 F0 => A8 inst_CLK_000_D0.C SM_AMIGA_1_.D CLK_OSZI
|
|
8.5 1 F0 => C8 inst_CLK_000_D0.C SM_AMIGA_2_.D CLK_OSZI
|
|
8.5 1 F0 => C1 inst_CLK_000_D0.C SM_AMIGA_3_.D CLK_OSZI
|
|
8.5 1 F0 => F8 inst_CLK_000_D0.C SM_AMIGA_4_.D CLK_OSZI
|
|
8.5 1 F0 => F5 inst_CLK_000_D0.C SM_AMIGA_5_.D CLK_OSZI
|
|
8.5 1 F0 => B13 inst_CLK_000_D0.C SM_AMIGA_6_.D CLK_OSZI
|
|
8.5 1 F0 => B5 inst_CLK_000_D0.C SM_AMIGA_7_.D CLK_OSZI
|
|
8.5 1 F0 => B9 inst_CLK_000_D0.C cpu_est_0_.D CLK_OSZI
|
|
8.5 1 F0 => G5 inst_CLK_000_D0.C cpu_est_2_.D.X1 CLK_OSZI
|
|
8.5 1 F0 => H5 inst_CLK_000_D0.C inst_CLK_000_D1.D CLK_OSZI
|
|
8.5 1 F0 => C9 inst_CLK_000_D0.C inst_DTACK_SYNC.D CLK_OSZI
|
|
8.5 1 F0 => C5 inst_CLK_000_D0.C inst_VPA_SYNC.D CLK_OSZI
|
|
8.5 1 H5 => H4 inst_CLK_000_D1.C BGACK_030.D CLK_OSZI
|
|
8.5 1 H5 => G4 inst_CLK_000_D1.C E.D.X1 CLK_OSZI
|
|
8.5 1 H5 => B8 inst_CLK_000_D1.C IPL_030_0_.D CLK_OSZI
|
|
8.5 1 H5 => B12 inst_CLK_000_D1.C IPL_030_1_.D CLK_OSZI
|
|
8.5 1 H5 => B4 inst_CLK_000_D1.C IPL_030_2_.D CLK_OSZI
|
|
8.5 1 H5 => D1 inst_CLK_000_D1.C VMA.D.X1 CLK_OSZI
|
|
8.5 1 H5 => D1 inst_CLK_000_D1.C VMA.D.X2 CLK_OSZI
|
|
8.5 1 H5 => B9 inst_CLK_000_D1.C cpu_est_0_.D CLK_OSZI
|
|
8.5 1 H5 => G5 inst_CLK_000_D1.C cpu_est_2_.D.X1 CLK_OSZI
|
|
8.5 1 H5 => E5 inst_CLK_000_D1.C inst_CLK_000_D2.D CLK_OSZI
|
|
8.5 1 E5 => B13 inst_CLK_000_D2.C SM_AMIGA_6_.D CLK_OSZI
|
|
8.5 1 E5 => B5 inst_CLK_000_D2.C SM_AMIGA_7_.D CLK_OSZI
|
|
8.5 1 E5 => D1 inst_CLK_000_D2.C VMA.D.X1 CLK_OSZI
|
|
8.5 1 E5 => A5 inst_CLK_000_D2.C inst_CLK_000_D3.D CLK_OSZI
|
|
8.5 1 A5 => B13 inst_CLK_000_D3.C SM_AMIGA_6_.D CLK_OSZI
|
|
8.5 1 A5 => B5 inst_CLK_000_D3.C SM_AMIGA_7_.D CLK_OSZI
|
|
8.5 1 A5 => A9 inst_CLK_000_D3.C inst_CLK_000_D4.D CLK_OSZI
|
|
8.5 1 A9 => E8 inst_CLK_000_D4.C inst_CLK_000_D5.D CLK_OSZI
|
|
8.5 1 E8 => H12 inst_CLK_000_D5.C DSACK_1_.D CLK_OSZI
|
|
8.5 1 E8 => C4 inst_CLK_000_D5.C SM_AMIGA_0_.D CLK_OSZI
|
|
8.5 1 E8 => A8 inst_CLK_000_D5.C SM_AMIGA_1_.D CLK_OSZI
|
|
8.5 1 E8 => F12 inst_CLK_000_D5.C inst_AS_030_000_SYNC.D CLK_OSZI
|
|
8.5 1 E8 => F4 inst_CLK_000_D5.C inst_CLK_000_D6.D CLK_OSZI
|
|
8.5 1 F4 => H12 inst_CLK_000_D6.C DSACK_1_.D CLK_OSZI
|
|
8.5 1 F4 => C4 inst_CLK_000_D6.C SM_AMIGA_0_.D CLK_OSZI
|
|
8.5 1 F4 => A8 inst_CLK_000_D6.C SM_AMIGA_1_.D CLK_OSZI
|
|
8.5 1 F4 => F12 inst_CLK_000_D6.C inst_AS_030_000_SYNC.D CLK_OSZI
|
|
8.5 1 A1 => G1 inst_CLK_OUT_PRE.C CLK_DIV_OUT.D CLK_OSZI
|
|
8.5 1 A1 => B0 inst_CLK_OUT_PRE.C CLK_EXP.D CLK_OSZI
|
|
8.5 1 C9 => C8 inst_DTACK_SYNC.C SM_AMIGA_2_.D CLK_OSZI
|
|
8.5 1 C9 => C1 inst_DTACK_SYNC.C SM_AMIGA_3_.D CLK_OSZI
|
|
8.5 1 C9 => C9 inst_DTACK_SYNC.C inst_DTACK_SYNC.D CLK_OSZI
|
|
8.5 1 E9 => D1 inst_VPA_D.C VMA.D.X2 CLK_OSZI
|
|
8.5 1 E9 => C9 inst_VPA_D.C inst_DTACK_SYNC.D CLK_OSZI
|
|
8.5 1 E9 => C5 inst_VPA_D.C inst_VPA_SYNC.D CLK_OSZI
|
|
8.5 1 C5 => C8 inst_VPA_SYNC.C SM_AMIGA_2_.D CLK_OSZI
|
|
8.5 1 C5 => C1 inst_VPA_SYNC.C SM_AMIGA_3_.D CLK_OSZI
|
|
8.5 1 C5 => C5 inst_VPA_SYNC.C inst_VPA_SYNC.D CLK_OSZI
|
|
|
|
|
|
Section tSU
|
|
|
|
tSU, tHD Level Location(From => To) Source Destination Reference_Clock
|
|
=========== ===== ==================== ====== =========== ===============
|
|
5.5, 0.0 1 p69 => D8 A0 LDS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p69 => D12 A0 UDS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p33 => G8 AS_000 A0.D CLK_OSZI
|
|
5.5, 0.0 1 p33 => H8 AS_000 AS_030.D CLK_OSZI
|
|
5.5, 0.0 1 p33 => A0 AS_000 DS_030.D CLK_OSZI
|
|
5.5, 0.0 1 p33 => G0 AS_000 SIZE_0_.D CLK_OSZI
|
|
5.5, 0.0 1 p33 => H0 AS_000 SIZE_1_.D CLK_OSZI
|
|
5.5, 0.0 1 p82 => D5 AS_030 AMIGA_BUS_ENABLE.D CLK_OSZI
|
|
5.5, 0.0 1 p82 => D4 AS_030 AS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p82 => D13 AS_030 BG_000.D CLK_OSZI
|
|
5.5, 0.0 1 p82 => H12 AS_030 DSACK_1_.D CLK_OSZI
|
|
5.5, 0.0 1 p82 => H1 AS_030 FPU_CS.D CLK_OSZI
|
|
5.5, 0.0 1 p82 => D8 AS_030 LDS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p82 => D12 AS_030 UDS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p82 => F12 AS_030 inst_AS_030_000_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p82 => C9 AS_030 inst_DTACK_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p82 => C5 AS_030 inst_VPA_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p96 => H1 A[16] FPU_CS.D CLK_OSZI
|
|
5.5, 0.0 1 p96 => F12 A[16] inst_AS_030_000_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p59 => H1 A[17] FPU_CS.D CLK_OSZI
|
|
5.5, 0.0 1 p59 => F12 A[17] inst_AS_030_000_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p95 => H1 A[18] FPU_CS.D CLK_OSZI
|
|
5.5, 0.0 1 p95 => F12 A[18] inst_AS_030_000_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p97 => H1 A[19] FPU_CS.D CLK_OSZI
|
|
5.5, 0.0 1 p97 => F12 A[19] inst_AS_030_000_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p28 => H4 BGACK_000 BGACK_030.D CLK_OSZI
|
|
5.5, 0.0 1 p28 => H1 BGACK_000 FPU_CS.D CLK_OSZI
|
|
5.5, 0.0 1 p28 => F12 BGACK_000 inst_AS_030_000_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p21 => D13 BG_030 BG_000.D CLK_OSZI
|
|
5.5, 0.0 1 p11 => D13 CLK_000 BG_000.D CLK_OSZI
|
|
5.5, 0.0 1 p11 => F0 CLK_000 inst_CLK_000_D0.D CLK_OSZI
|
|
5.5, 0.0 1 p64 => G8 CLK_030 A0.D CLK_OSZI
|
|
5.5, 0.0 1 p64 => H8 CLK_030 AS_030.D CLK_OSZI
|
|
5.5, 0.0 1 p64 => A0 CLK_030 DS_030.D CLK_OSZI
|
|
5.5, 0.0 1 p64 => H1 CLK_030 FPU_CS.D CLK_OSZI
|
|
5.5, 0.0 1 p64 => G0 CLK_030 SIZE_0_.D CLK_OSZI
|
|
5.5, 0.0 1 p64 => H0 CLK_030 SIZE_1_.D CLK_OSZI
|
|
5.5, 0.0 1 p64 => F12 CLK_030 inst_AS_030_000_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p98 => D8 DS_030 LDS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p98 => D12 DS_030 UDS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p30 => C9 DTACK inst_DTACK_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p57 => H1 FC[0] FPU_CS.D CLK_OSZI
|
|
5.5, 0.0 1 p57 => F12 FC[0] inst_AS_030_000_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p58 => H1 FC[1] FPU_CS.D CLK_OSZI
|
|
5.5, 0.0 1 p58 => F12 FC[1] inst_AS_030_000_SYNC.D CLK_OSZI
|
|
5.5, 0.0 1 p67 => B8 IPL[0] IPL_030_0_.D CLK_OSZI
|
|
5.5, 0.0 1 p56 => B12 IPL[1] IPL_030_1_.D CLK_OSZI
|
|
5.5, 0.0 1 p68 => B4 IPL[2] IPL_030_2_.D CLK_OSZI
|
|
5.5, 0.0 1 p31 => G8 LDS_000 A0.D CLK_OSZI
|
|
5.5, 0.0 1 p31 => H8 LDS_000 AS_030.D CLK_OSZI
|
|
5.5, 0.0 1 p31 => A0 LDS_000 DS_030.D CLK_OSZI
|
|
5.5, 0.0 1 p31 => G0 LDS_000 SIZE_0_.D CLK_OSZI
|
|
5.5, 0.0 1 p31 => H0 LDS_000 SIZE_1_.D CLK_OSZI
|
|
5.5, 0.0 1 p71 => A0 RW DS_030.D CLK_OSZI
|
|
5.5, 0.0 1 p71 => D8 RW LDS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p71 => D12 RW UDS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p70 => D8 SIZE[0] LDS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p79 => D8 SIZE[1] LDS_000.D CLK_OSZI
|
|
5.5, 0.0 1 p32 => G8 UDS_000 A0.D CLK_OSZI
|
|
5.5, 0.0 1 p32 => H8 UDS_000 AS_030.D CLK_OSZI
|
|
5.5, 0.0 1 p32 => A0 UDS_000 DS_030.D CLK_OSZI
|
|
5.5, 0.0 1 p32 => G0 UDS_000 SIZE_0_.D CLK_OSZI
|
|
5.5, 0.0 1 p32 => H0 UDS_000 SIZE_1_.D CLK_OSZI
|
|
5.5, 0.0 1 p36 => E9 VPA inst_VPA_D.D CLK_OSZI
|
|
5.5, 0.0 1 p14 => D5 nEXP_SPACE AMIGA_BUS_ENABLE.D CLK_OSZI
|
|
5.5, 0.0 1 p14 => D13 nEXP_SPACE BG_000.D CLK_OSZI
|
|
5.5, 0.0 1 p14 => B13 nEXP_SPACE SM_AMIGA_6_.D CLK_OSZI
|
|
5.5, 0.0 1 p14 => B5 nEXP_SPACE SM_AMIGA_7_.D CLK_OSZI
|
|
5.5, 0.0 1 p14 => F12 nEXP_SPACE inst_AS_030_000_SYNC.D CLK_OSZI
|
|
|
|
|
|
Section tPD
|
|
|
|
Delay Level Location(From => To) Source Destination
|
|
===== ===== ==================== ====== ===========
|
|
10.0 1 p93 => p47 A[20] CIIN
|
|
10.0 1 p94 => p47 A[21] CIIN
|
|
10.0 1 p85 => p47 A[22] CIIN
|
|
10.0 1 p84 => p47 A[23] CIIN
|
|
10.0 1 p81 => p30 DSACK[1] DTACK
|
|
10.0 1 p71 => p48 RW AMIGA_BUS_DATA_DIR
|
|
10.0 1 p14 => p48 nEXP_SPACE AMIGA_BUS_DATA_DIR
|
|
|
|
|
|
Section tCO
|
|
|
|
tCO Level Location(From => To) Source Destination Register_Clock
|
|
=== ===== ==================== ====== =========== ==============
|
|
13.0 2 p61 => p48 CLK_OSZI AMIGA_BUS_DATA_DIR BGACK_030.C
|
|
6.0 1 p61 => p69 CLK_OSZI A0 A0.C
|
|
6.0 1 p61 => p34 CLK_OSZI AMIGA_BUS_ENABLE AMIGA_BUS_ENABLE.C
|
|
6.0 1 p61 => p33 CLK_OSZI AS_000 AS_000.C
|
|
6.0 1 p61 => p82 CLK_OSZI AS_030 AS_030.C
|
|
6.0 1 p61 => p83 CLK_OSZI BGACK_030 BGACK_030.C
|
|
6.0 1 p61 => p29 CLK_OSZI BG_000 BG_000.C
|
|
6.0 1 p61 => p65 CLK_OSZI CLK_DIV_OUT CLK_DIV_OUT.C
|
|
6.0 1 p61 => p10 CLK_OSZI CLK_EXP CLK_EXP.C
|
|
6.0 1 p61 => p81 CLK_OSZI DSACK[1] DSACK_1_.C
|
|
6.0 1 p61 => p98 CLK_OSZI DS_030 DS_030.C
|
|
6.0 1 p61 => p66 CLK_OSZI E E.C
|
|
6.0 1 p61 => p78 CLK_OSZI FPU_CS FPU_CS.C
|
|
6.0 1 p61 => p8 CLK_OSZI IPL_030[0] IPL_030_0_.C
|
|
6.0 1 p61 => p7 CLK_OSZI IPL_030[1] IPL_030_1_.C
|
|
6.0 1 p61 => p9 CLK_OSZI IPL_030[2] IPL_030_2_.C
|
|
6.0 1 p61 => p31 CLK_OSZI LDS_000 LDS_000.C
|
|
6.0 1 p61 => p3 CLK_OSZI RESET RESET.C
|
|
6.0 1 p61 => p70 CLK_OSZI SIZE[0] SIZE_0_.C
|
|
6.0 1 p61 => p79 CLK_OSZI SIZE[1] SIZE_1_.C
|
|
6.0 1 p61 => p32 CLK_OSZI UDS_000 UDS_000.C
|
|
6.0 1 p61 => p35 CLK_OSZI VMA VMA.C
|