68030tk/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt
MHeinrichs be14e6527f Cleaned up version
This version is the base for all future experiments.
2014-05-15 23:05:08 +02:00

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@N: MF248 |Running in 64-bit mode.
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":145:4:145:7|Found ROM, 'clk\.cpu_est_11[3:0]', 16 words by 4 bits
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.