mirror of https://github.com/kr239/68030tk.git
2435 lines
76 KiB
Plaintext
2435 lines
76 KiB
Plaintext
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
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#$ DATE Wed May 13 22:59:21 2015
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#$ MODULE 68030_tk
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#$ PINS 75 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ IPL_030_2_ A_22_ A_21_ \
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# IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ RW_000 A_15_ DS_030 A_14_ UDS_000 \
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# A_13_ LDS_000 A_12_ A0 A_11_ A1 A_10_ nEXP_SPACE A_9_ BERR A_8_ BG_030 A_7_ BG_000 A_6_ \
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# BGACK_030 A_5_ BGACK_000 A_4_ CLK_030 A_3_ CLK_000 A_2_ CLK_OSZI IPL_030_1_ CLK_DIV_OUT \
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# IPL_030_0_ CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DSACK1 DTACK AVEC E VPA VMA RST \
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# RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
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# AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_
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#$ NODES 695 N_310 un1_rst_dly_i_m_i_5__n sm_amiga_srsts_i_0_m2_3__un0_n N_220 \
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# sm_amiga_srsts_i_0_m2_1__un3_n pos_clk_cpu_est_11_1__n un1_rst_dly_i_m_i_6__n \
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# sm_amiga_srsts_i_0_m2_1__un1_n N_14 sm_amiga_srsts_i_0_m2_1__un0_n N_18 \
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# un1_rst_dly_i_m_i_7__n un1_amiga_bus_enable_dma_high_0_m2_0__un3_n N_22 \
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# un1_amiga_bus_enable_dma_high_0_m2_0__un1_n inst_BGACK_030_INTreg \
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# RESET_OUT_0_sqmuxa_1 un1_rst_dly_i_m_i_8__n \
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# un1_amiga_bus_enable_dma_high_0_m2_0__un0_n vcc_n_n N_205 \
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# un1_sm_amiga_7_i_m2_un3_n cpu_est_3_reg N_213 un1_rst_dly_i_m_i_2__n \
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# un1_sm_amiga_7_i_m2_un1_n inst_VMA_INTreg pos_clk_RST_DLY_5_iv_0_x2_0_ \
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# un1_sm_amiga_7_i_m2_un0_n inst_RESET_OUTreg N_105 N_98_i size_dma_0_0__un3_n \
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# gnd_n_n N_98 size_dma_0_0__un1_n un1_amiga_bus_enable_low RESET_OUT_0_sqmuxa \
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# N_105_i size_dma_0_0__un0_n un6_as_030 un1_rst_dly_i_m_2__n size_dma_0_1__un3_n \
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# un3_size G_137 N_22_i size_dma_0_1__un1_n un4_size un1_rst_dly_i_m_8__n N_33_0 \
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# size_dma_0_1__un0_n un5_ciin G_149 N_18_i ipl_030_0_0__un3_n un4_as_000 \
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# RESET_OUT_0_sqmuxa_5 N_37_0 ipl_030_0_0__un1_n un21_fpu_cs RESET_OUT_0_sqmuxa_7 \
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# N_14_i ipl_030_0_0__un0_n un22_berr G_147 N_41_0 ipl_030_0_1__un3_n un6_ds_030 G_145 \
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# N_10_i ipl_030_0_1__un1_n un6_uds_000 N_211 N_44_0 ipl_030_0_1__un0_n un6_lds_000 \
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# G_143 pos_clk_cpu_est_11_0_1__n ipl_030_0_2__un3_n cpu_est_0_ N_209 N_312_i \
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# ipl_030_0_2__un1_n cpu_est_1_ G_141 N_90_i ipl_030_0_2__un0_n inst_AS_000_INT G_139 \
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# N_88_i amiga_bus_enable_dma_high_0_un3_n SM_AMIGA_5_ un1_rst_dly_i_m_7__n N_299_i \
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# amiga_bus_enable_dma_high_0_un1_n inst_AMIGA_BUS_ENABLE_DMA_LOW \
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# un1_rst_dly_i_m_6__n N_275_0 amiga_bus_enable_dma_high_0_un0_n inst_AS_030_D0 \
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# un1_rst_dly_i_m_5__n N_274_0 bg_000_0_un3_n inst_nEXP_SPACE_D0reg \
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# un1_rst_dly_i_m_4__n N_273_i bg_000_0_un1_n inst_DS_030_D0 un1_rst_dly_i_m_3__n \
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# N_272_i bg_000_0_un0_n inst_AS_030_000_SYNC N_71_i N_270_i ds_000_dma_0_un3_n \
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# inst_BGACK_030_INT_D un1_amiga_bus_enable_low_i N_268_i ds_000_dma_0_un1_n \
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# inst_AS_000_DMA un21_fpu_cs_i N_310_i ds_000_dma_0_un0_n inst_DS_000_DMA \
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# RESET_OUT_i N_311_i as_000_dma_0_un3_n CYCLE_DMA_0_ BGACK_030_INT_i N_267_0 \
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# as_000_dma_0_un1_n CYCLE_DMA_1_ RESET_OUT_0_sqmuxa_i N_309_i as_000_dma_0_un0_n \
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# SIZE_DMA_0_ un1_rst_dly_i_3__n N_308_i a0_dma_0_un3_n SIZE_DMA_1_ \
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# un1_rst_dly_i_4__n pos_clk_un7_clk_000_pe_0_n a0_dma_0_un1_n inst_VPA_D \
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# un1_rst_dly_i_5__n N_264_0 a0_dma_0_un0_n inst_UDS_000_INT un1_rst_dly_i_6__n \
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# N_304_i dsack1_int_0_un3_n inst_LDS_000_INT un1_rst_dly_i_7__n N_303_i \
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# dsack1_int_0_un1_n inst_CLK_OUT_PRE_D un1_rst_dly_i_8__n N_186_i \
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# dsack1_int_0_un0_n inst_DTACK_D0 un1_rst_dly_i_2__n VPA_c_i as_000_int_0_un3_n \
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# inst_CLK_OUT_PRE_50 N_87_i_i N_56_0 as_000_int_0_un1_n inst_CLK_000_D1 \
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# cpu_est_i_3__n DTACK_c_i as_000_int_0_un0_n inst_CLK_000_D0 cpu_est_i_0__n N_57_0 \
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# ds_000_enable_0_un3_n inst_CLK_000_PE VPA_D_i N_97_i ds_000_enable_0_un1_n \
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# CLK_000_P_SYNC_9_ VMA_INT_i ds_000_enable_0_un0_n inst_CLK_000_NE cpu_est_i_1__n \
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# N_96_i as_030_000_sync_0_un3_n CLK_000_N_SYNC_11_ CLK_000_PE_i N_95_i \
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# as_030_000_sync_0_un1_n cpu_est_2_ BERR_i N_94_i as_030_000_sync_0_un0_n IPL_D0_0_ \
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# sm_amiga_i_4__n N_313_i lds_000_int_0_un3_n IPL_D0_1_ cpu_est_i_2__n N_136_i \
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# lds_000_int_0_un1_n IPL_D0_2_ sm_amiga_i_5__n N_81_0 lds_000_int_0_un0_n \
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# SM_AMIGA_3_ DTACK_D0_i N_116_i rw_000_dma_0_un3_n inst_CLK_000_NE_D0 \
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# sm_amiga_i_0__n N_77_i rw_000_dma_0_un1_n pos_clk_un6_bg_030_n sm_amiga_i_3__n \
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# N_73_i rw_000_dma_0_un0_n SM_AMIGA_0_ CLK_000_NE_i N_101_i uds_000_int_0_un3_n \
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# inst_AMIGA_BUS_ENABLE_DMA_HIGH sm_amiga_i_6__n uds_000_int_0_un1_n \
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# inst_DSACK1_INTreg sm_amiga_i_1__n clk_000_n_sync_i_10__n uds_000_int_0_un0_n \
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# CLK_OUT_PRE_D_i pos_clk_un9_clk_000_n_sync_i_n amiga_bus_enable_dma_low_0_un3_n \
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# pos_clk_ipl_n pos_clk_un11_clk_000_n_sync_i_n pos_clk_un14_clk_000_n_sync_0_n \
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# amiga_bus_enable_dma_low_0_un1_n pos_clk_un3_ds_030_d0_n LDS_000_i \
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# pos_clk_un22_bgack_030_int_i_n amiga_bus_enable_dma_low_0_un0_n SM_AMIGA_6_ \
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# UDS_000_i N_86_i a_15__n AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa nEXP_SPACE_D0_i N_93_i \
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# RST_DLY_0_ sm_amiga_i_2__n a_14__n RST_DLY_1_ AS_030_i N_99_i RST_DLY_2_ A1_i \
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# pos_clk_size_dma_6_0_1__n a_13__n RST_DLY_3_ CLK_000_D1_i N_100_i RST_DLY_4_ \
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# RW_000_i pos_clk_size_dma_6_0_0__n a_12__n RST_DLY_5_ CLK_030_H_i N_245_0 RST_DLY_6_ \
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# AS_000_DMA_i N_108_i a_11__n RST_DLY_7_ AS_000_i N_109_i pos_clk_un8_bg_030_n \
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# sm_amiga_i_i_7__n N_246_0 a_10__n CLK_000_P_SYNC_0_ RW_i un5_ciin_i \
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# CLK_000_P_SYNC_1_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_247_0 a_9__n CLK_000_P_SYNC_2_ \
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# FPU_SENSE_i N_248_0 CLK_000_P_SYNC_3_ AS_030_D0_i CLK_000_D0_i a_8__n \
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# CLK_000_P_SYNC_4_ a_i_24__n N_249_i CLK_000_P_SYNC_5_ size_dma_i_0__n \
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# AS_030_000_SYNC_i a_7__n CLK_000_P_SYNC_6_ size_dma_i_1__n N_251_0 \
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# CLK_000_P_SYNC_7_ a_i_16__n pos_clk_un3_as_030_d0_i_n a_6__n CLK_000_P_SYNC_8_ \
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# a_i_18__n pos_clk_un5_bgack_030_int_d_i_n CLK_000_N_SYNC_0_ a_i_19__n N_75_i a_5__n \
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# CLK_000_N_SYNC_1_ a_i_31__n N_76_i CLK_000_N_SYNC_2_ a_i_29__n N_78_0 a_4__n \
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# CLK_000_N_SYNC_3_ a_i_30__n N_80_0 CLK_000_N_SYNC_4_ a_i_27__n CLK_EXP_c_i a_3__n \
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# CLK_000_N_SYNC_5_ a_i_28__n N_258_0 CLK_000_N_SYNC_6_ a_i_25__n N_283_i a_2__n \
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# CLK_000_N_SYNC_7_ a_i_26__n N_284_i CLK_000_N_SYNC_8_ UDS_000_INT_i \
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# CLK_000_N_SYNC_9_ LDS_000_INT_i N_290_i CLK_000_N_SYNC_10_ DS_030_i N_291_i \
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# pos_clk_un5_bgack_030_int_d_n N_224_i inst_RW_000_INT N_225_i N_279_i \
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# inst_RW_000_DMA N_226_i N_293_i inst_A0_DMA inst_CLK_030_H N_82_i SM_AMIGA_1_ N_83_i \
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# SM_AMIGA_4_ N_104_i N_259_0 SM_AMIGA_2_ N_103_i N_84_i pos_clk_un3_as_030_d0_n \
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# N_282_i N_115_0 inst_DS_000_ENABLE N_92_i N_85_i AS_000_INT_1_sqmuxa un6_lds_000_i \
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# N_294_i DS_000_ENABLE_1_sqmuxa_1 un6_uds_000_i N_296_i pos_clk_a0_dma_3_n \
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# un6_ds_030_i pos_clk_cpu_est_11_0_3__n pos_clk_ds_000_dma_4_n DS_000_DMA_i N_91_i \
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# N_3 un4_as_000_i N_260_0 AS_000_INT_i N_301_i un6_as_030_i pos_clk_ds_000_dma_4_0_n \
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# N_6 AMIGA_BUS_ENABLE_DMA_LOW_i N_305_i N_8 DS_030_D0_i N_306_i N_9 AS_030_c \
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# AMIGA_BUS_DATA_DIR_c_0 N_10 N_307_i N_11 AS_000_c N_12 N_13 RW_000_c N_15 N_265_0 N_16 \
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# DS_030_c N_269_i N_19 pos_clk_un24_bgack_030_int_i_0_i_n N_20 UDS_000_c N_62_0 N_21 \
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# N_276_0 N_23 LDS_000_c N_277_0 N_24 N_286_i N_25 size_c_0__n N_288_i N_289_i size_c_1__n \
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# pos_clk_un11_ds_030_d0_i_n A0_c_i size_c_i_1__n N_25_i N_32_0 N_24_i N_31_0 N_23_i \
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# N_30_0 ipl_c_i_2__n N_54_0 ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 nEXP_SPACE_c_i \
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# N_55_0 N_50_0 N_3_i N_49_0 N_6_i N_48_0 N_8_i N_46_0 N_9_i N_45_0 N_12_i SM_AMIGA_i_7_ \
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# N_43_0 N_115 N_13_i pos_clk_size_dma_6_0__n a_c_16__n N_42_0 pos_clk_size_dma_6_1__n \
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# N_15_i pos_clk_cpu_est_11_3__n a_c_17__n N_40_0 G_165 N_16_i G_166 a_c_18__n N_39_0 \
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# G_167 N_19_i un6_uds_000_1 a_c_19__n N_36_0 pos_clk_un24_bgack_030_int_i_0_n N_20_i \
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# N_245 a_c_20__n N_35_0 N_246 N_21_i N_247 a_c_21__n N_34_0 N_248 BG_030_c_i N_89 \
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# a_c_22__n pos_clk_un6_bg_030_i_n N_92 pos_clk_un8_bg_030_0_n N_102 a_c_23__n \
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# N_127_i_1 N_103 N_127_i_2 N_104 a_c_24__n pos_clk_un24_bgack_030_int_i_0_i_1_n N_112 \
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# N_80_0_1 N_256 a_c_25__n N_75_i_1 N_258 N_251_0_1 a_c_26__n \
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# pos_clk_un11_ds_030_d0_i_1_n N_260 N_340_1 N_265 a_c_27__n N_340_2 N_282 N_340_3 N_71 \
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# a_c_28__n N_340_4 cpu_est_0_0_x2_0_ un5_ciin_1 pos_clk_un11_clk_000_n_sync_n \
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# a_c_29__n un5_ciin_2 N_76 un5_ciin_3 pos_clk_CYCLE_DMA_5_1_i_x2 a_c_30__n un5_ciin_4 \
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# pos_clk_CYCLE_DMA_5_0_i_x2 un5_ciin_5 pos_clk_un24_bgack_030_int_i_0_x2 a_c_31__n \
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# un5_ciin_6 pos_clk_un22_bgack_030_int_n un5_ciin_7 N_268 A0_c un5_ciin_8 N_270 \
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# un5_ciin_9 N_73 A1_c un5_ciin_10 N_75 un5_ciin_11 N_251 nEXP_SPACE_c un22_berr_1_0 \
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# un22_berr_1 un21_fpu_cs_1 N_95 BERR_c pos_clk_un6_bg_030_1_n N_94 N_131_i_1 N_288 \
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# BG_030_c N_131_i_2 N_289 N_131_i_3 N_286 BG_000DFFreg N_96_1 N_279 N_96_2 N_277 N_96_3 \
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# N_276 BGACK_000_c pos_clk_cpu_est_11_0_1_1__n N_62 pos_clk_cpu_est_11_0_2_1__n \
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# N_274 N_310_1 N_313 N_310_2 N_307 N_310_3 N_305 CLK_OSZI_c N_310_4 N_306 N_309_1 N_303 \
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# N_309_2 N_304 CLK_EXP_c N_308_1 N_301 N_308_2 N_91 RESET_OUT_0_sqmuxa_5_1 N_85 \
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# FPU_SENSE_c RESET_OUT_0_sqmuxa_7_1 N_294 RESET_OUT_0_sqmuxa_7_2 N_296 \
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# IPL_030DFF_0_reg RESET_OUT_0_sqmuxa_7_3 N_84 N_94_1 N_82 IPL_030DFF_1_reg N_95_1 N_83 \
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# N_119_i_1 N_293 IPL_030DFF_2_reg N_82_1 N_290 N_83_1 N_291 ipl_c_0__n N_296_1 N_283 \
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# N_303_1 N_284 ipl_c_1__n N_304_1 N_86 N_306_1 N_80 ipl_c_2__n N_129_i_1 N_78 N_125_i_1 \
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# N_108 N_123_i_1 N_109 DTACK_c N_115_0_1 N_100 pos_clk_cpu_est_11_0_1_3__n N_99 \
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# N_260_0_1 N_93 N_261_i_1 pos_clk_un14_clk_000_n_sync_n VPA_c N_262_i_1 \
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# pos_clk_un9_clk_000_n_sync_n N_263_i_1 N_340 pos_clk_ipl_1_n N_97 RST_c \
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# cpu_est_0_3__un3_n N_136 cpu_est_0_3__un1_n N_101 cpu_est_0_3__un0_n N_81 RW_c \
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# cpu_est_0_2__un3_n N_116 cpu_est_0_2__un1_n N_96 fc_c_0__n cpu_est_0_2__un0_n N_113 \
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# cpu_est_0_1__un3_n N_275 fc_c_1__n cpu_est_0_1__un1_n N_273 cpu_est_0_1__un0_n N_88 \
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# bgack_030_int_0_un3_n N_272 AMIGA_BUS_DATA_DIR_c bgack_030_int_0_un1_n N_299 \
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# bgack_030_int_0_un0_n N_90 vma_int_0_un3_n N_311 vma_int_0_un1_n N_312 \
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# vma_int_0_un0_n N_267 un1_as_000_i rw_000_int_0_un3_n N_264 un1_rst_dly_i_m_i_3__n \
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# rw_000_int_0_un1_n pos_clk_un7_clk_000_pe_n rw_000_int_0_un0_n N_308 \
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# un1_rst_dly_i_m_i_4__n sm_amiga_srsts_i_0_m2_3__un3_n N_309 \
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# sm_amiga_srsts_i_0_m2_3__un1_n
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.model bus68030
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.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
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BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
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DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \
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A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
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A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF \
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A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF \
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A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \
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SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF \
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LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_310.BLIF \
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un1_rst_dly_i_m_i_5__n.BLIF sm_amiga_srsts_i_0_m2_3__un0_n.BLIF N_220.BLIF \
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sm_amiga_srsts_i_0_m2_1__un3_n.BLIF pos_clk_cpu_est_11_1__n.BLIF \
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un1_rst_dly_i_m_i_6__n.BLIF sm_amiga_srsts_i_0_m2_1__un1_n.BLIF N_14.BLIF \
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sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_18.BLIF un1_rst_dly_i_m_i_7__n.BLIF \
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un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF N_22.BLIF \
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un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF inst_BGACK_030_INTreg.BLIF \
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RESET_OUT_0_sqmuxa_1.BLIF un1_rst_dly_i_m_i_8__n.BLIF \
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un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF vcc_n_n.BLIF N_205.BLIF \
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un1_sm_amiga_7_i_m2_un3_n.BLIF cpu_est_3_reg.BLIF N_213.BLIF \
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un1_rst_dly_i_m_i_2__n.BLIF un1_sm_amiga_7_i_m2_un1_n.BLIF \
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inst_VMA_INTreg.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF \
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un1_sm_amiga_7_i_m2_un0_n.BLIF inst_RESET_OUTreg.BLIF N_105.BLIF N_98_i.BLIF \
|
|
size_dma_0_0__un3_n.BLIF gnd_n_n.BLIF N_98.BLIF size_dma_0_0__un1_n.BLIF \
|
|
un1_amiga_bus_enable_low.BLIF RESET_OUT_0_sqmuxa.BLIF N_105_i.BLIF \
|
|
size_dma_0_0__un0_n.BLIF un6_as_030.BLIF un1_rst_dly_i_m_2__n.BLIF \
|
|
size_dma_0_1__un3_n.BLIF un3_size.BLIF G_137.BLIF N_22_i.BLIF \
|
|
size_dma_0_1__un1_n.BLIF un4_size.BLIF un1_rst_dly_i_m_8__n.BLIF N_33_0.BLIF \
|
|
size_dma_0_1__un0_n.BLIF un5_ciin.BLIF G_149.BLIF N_18_i.BLIF \
|
|
ipl_030_0_0__un3_n.BLIF un4_as_000.BLIF RESET_OUT_0_sqmuxa_5.BLIF N_37_0.BLIF \
|
|
ipl_030_0_0__un1_n.BLIF un21_fpu_cs.BLIF RESET_OUT_0_sqmuxa_7.BLIF N_14_i.BLIF \
|
|
ipl_030_0_0__un0_n.BLIF un22_berr.BLIF G_147.BLIF N_41_0.BLIF \
|
|
ipl_030_0_1__un3_n.BLIF un6_ds_030.BLIF G_145.BLIF N_10_i.BLIF \
|
|
ipl_030_0_1__un1_n.BLIF un6_uds_000.BLIF N_211.BLIF N_44_0.BLIF \
|
|
ipl_030_0_1__un0_n.BLIF un6_lds_000.BLIF G_143.BLIF \
|
|
pos_clk_cpu_est_11_0_1__n.BLIF ipl_030_0_2__un3_n.BLIF cpu_est_0_.BLIF \
|
|
N_209.BLIF N_312_i.BLIF ipl_030_0_2__un1_n.BLIF cpu_est_1_.BLIF G_141.BLIF \
|
|
N_90_i.BLIF ipl_030_0_2__un0_n.BLIF inst_AS_000_INT.BLIF G_139.BLIF \
|
|
N_88_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF SM_AMIGA_5_.BLIF \
|
|
un1_rst_dly_i_m_7__n.BLIF N_299_i.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \
|
|
inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF un1_rst_dly_i_m_6__n.BLIF N_275_0.BLIF \
|
|
amiga_bus_enable_dma_high_0_un0_n.BLIF inst_AS_030_D0.BLIF \
|
|
un1_rst_dly_i_m_5__n.BLIF N_274_0.BLIF bg_000_0_un3_n.BLIF \
|
|
inst_nEXP_SPACE_D0reg.BLIF un1_rst_dly_i_m_4__n.BLIF N_273_i.BLIF \
|
|
bg_000_0_un1_n.BLIF inst_DS_030_D0.BLIF un1_rst_dly_i_m_3__n.BLIF N_272_i.BLIF \
|
|
bg_000_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF N_71_i.BLIF N_270_i.BLIF \
|
|
ds_000_dma_0_un3_n.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
un1_amiga_bus_enable_low_i.BLIF N_268_i.BLIF ds_000_dma_0_un1_n.BLIF \
|
|
inst_AS_000_DMA.BLIF un21_fpu_cs_i.BLIF N_310_i.BLIF ds_000_dma_0_un0_n.BLIF \
|
|
inst_DS_000_DMA.BLIF RESET_OUT_i.BLIF N_311_i.BLIF as_000_dma_0_un3_n.BLIF \
|
|
CYCLE_DMA_0_.BLIF BGACK_030_INT_i.BLIF N_267_0.BLIF as_000_dma_0_un1_n.BLIF \
|
|
CYCLE_DMA_1_.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_309_i.BLIF \
|
|
as_000_dma_0_un0_n.BLIF SIZE_DMA_0_.BLIF un1_rst_dly_i_3__n.BLIF N_308_i.BLIF \
|
|
a0_dma_0_un3_n.BLIF SIZE_DMA_1_.BLIF un1_rst_dly_i_4__n.BLIF \
|
|
pos_clk_un7_clk_000_pe_0_n.BLIF a0_dma_0_un1_n.BLIF inst_VPA_D.BLIF \
|
|
un1_rst_dly_i_5__n.BLIF N_264_0.BLIF a0_dma_0_un0_n.BLIF inst_UDS_000_INT.BLIF \
|
|
un1_rst_dly_i_6__n.BLIF N_304_i.BLIF dsack1_int_0_un3_n.BLIF \
|
|
inst_LDS_000_INT.BLIF un1_rst_dly_i_7__n.BLIF N_303_i.BLIF \
|
|
dsack1_int_0_un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF un1_rst_dly_i_8__n.BLIF \
|
|
N_186_i.BLIF dsack1_int_0_un0_n.BLIF inst_DTACK_D0.BLIF \
|
|
un1_rst_dly_i_2__n.BLIF VPA_c_i.BLIF as_000_int_0_un3_n.BLIF \
|
|
inst_CLK_OUT_PRE_50.BLIF N_87_i_i.BLIF N_56_0.BLIF as_000_int_0_un1_n.BLIF \
|
|
inst_CLK_000_D1.BLIF cpu_est_i_3__n.BLIF DTACK_c_i.BLIF \
|
|
as_000_int_0_un0_n.BLIF inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF N_57_0.BLIF \
|
|
ds_000_enable_0_un3_n.BLIF inst_CLK_000_PE.BLIF VPA_D_i.BLIF N_97_i.BLIF \
|
|
ds_000_enable_0_un1_n.BLIF CLK_000_P_SYNC_9_.BLIF VMA_INT_i.BLIF \
|
|
ds_000_enable_0_un0_n.BLIF inst_CLK_000_NE.BLIF cpu_est_i_1__n.BLIF \
|
|
N_96_i.BLIF as_030_000_sync_0_un3_n.BLIF CLK_000_N_SYNC_11_.BLIF \
|
|
CLK_000_PE_i.BLIF N_95_i.BLIF as_030_000_sync_0_un1_n.BLIF cpu_est_2_.BLIF \
|
|
BERR_i.BLIF N_94_i.BLIF as_030_000_sync_0_un0_n.BLIF IPL_D0_0_.BLIF \
|
|
sm_amiga_i_4__n.BLIF N_313_i.BLIF lds_000_int_0_un3_n.BLIF IPL_D0_1_.BLIF \
|
|
cpu_est_i_2__n.BLIF N_136_i.BLIF lds_000_int_0_un1_n.BLIF IPL_D0_2_.BLIF \
|
|
sm_amiga_i_5__n.BLIF N_81_0.BLIF lds_000_int_0_un0_n.BLIF SM_AMIGA_3_.BLIF \
|
|
DTACK_D0_i.BLIF N_116_i.BLIF rw_000_dma_0_un3_n.BLIF inst_CLK_000_NE_D0.BLIF \
|
|
sm_amiga_i_0__n.BLIF N_77_i.BLIF rw_000_dma_0_un1_n.BLIF \
|
|
pos_clk_un6_bg_030_n.BLIF sm_amiga_i_3__n.BLIF N_73_i.BLIF \
|
|
rw_000_dma_0_un0_n.BLIF SM_AMIGA_0_.BLIF CLK_000_NE_i.BLIF N_101_i.BLIF \
|
|
uds_000_int_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \
|
|
sm_amiga_i_6__n.BLIF uds_000_int_0_un1_n.BLIF inst_DSACK1_INTreg.BLIF \
|
|
sm_amiga_i_1__n.BLIF clk_000_n_sync_i_10__n.BLIF uds_000_int_0_un0_n.BLIF \
|
|
CLK_OUT_PRE_D_i.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF \
|
|
amiga_bus_enable_dma_low_0_un3_n.BLIF pos_clk_ipl_n.BLIF \
|
|
pos_clk_un11_clk_000_n_sync_i_n.BLIF pos_clk_un14_clk_000_n_sync_0_n.BLIF \
|
|
amiga_bus_enable_dma_low_0_un1_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF \
|
|
LDS_000_i.BLIF pos_clk_un22_bgack_030_int_i_n.BLIF \
|
|
amiga_bus_enable_dma_low_0_un0_n.BLIF SM_AMIGA_6_.BLIF UDS_000_i.BLIF \
|
|
N_86_i.BLIF a_15__n.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF \
|
|
nEXP_SPACE_D0_i.BLIF N_93_i.BLIF RST_DLY_0_.BLIF sm_amiga_i_2__n.BLIF \
|
|
a_14__n.BLIF RST_DLY_1_.BLIF AS_030_i.BLIF N_99_i.BLIF RST_DLY_2_.BLIF \
|
|
A1_i.BLIF pos_clk_size_dma_6_0_1__n.BLIF a_13__n.BLIF RST_DLY_3_.BLIF \
|
|
CLK_000_D1_i.BLIF N_100_i.BLIF RST_DLY_4_.BLIF RW_000_i.BLIF \
|
|
pos_clk_size_dma_6_0_0__n.BLIF a_12__n.BLIF RST_DLY_5_.BLIF CLK_030_H_i.BLIF \
|
|
N_245_0.BLIF RST_DLY_6_.BLIF AS_000_DMA_i.BLIF N_108_i.BLIF a_11__n.BLIF \
|
|
RST_DLY_7_.BLIF AS_000_i.BLIF N_109_i.BLIF pos_clk_un8_bg_030_n.BLIF \
|
|
sm_amiga_i_i_7__n.BLIF N_246_0.BLIF a_10__n.BLIF CLK_000_P_SYNC_0_.BLIF \
|
|
RW_i.BLIF un5_ciin_i.BLIF CLK_000_P_SYNC_1_.BLIF \
|
|
AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_247_0.BLIF a_9__n.BLIF \
|
|
CLK_000_P_SYNC_2_.BLIF FPU_SENSE_i.BLIF N_248_0.BLIF CLK_000_P_SYNC_3_.BLIF \
|
|
AS_030_D0_i.BLIF CLK_000_D0_i.BLIF a_8__n.BLIF CLK_000_P_SYNC_4_.BLIF \
|
|
a_i_24__n.BLIF N_249_i.BLIF CLK_000_P_SYNC_5_.BLIF size_dma_i_0__n.BLIF \
|
|
AS_030_000_SYNC_i.BLIF a_7__n.BLIF CLK_000_P_SYNC_6_.BLIF size_dma_i_1__n.BLIF \
|
|
N_251_0.BLIF CLK_000_P_SYNC_7_.BLIF a_i_16__n.BLIF \
|
|
pos_clk_un3_as_030_d0_i_n.BLIF a_6__n.BLIF CLK_000_P_SYNC_8_.BLIF \
|
|
a_i_18__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF CLK_000_N_SYNC_0_.BLIF \
|
|
a_i_19__n.BLIF N_75_i.BLIF a_5__n.BLIF CLK_000_N_SYNC_1_.BLIF a_i_31__n.BLIF \
|
|
N_76_i.BLIF CLK_000_N_SYNC_2_.BLIF a_i_29__n.BLIF N_78_0.BLIF a_4__n.BLIF \
|
|
CLK_000_N_SYNC_3_.BLIF a_i_30__n.BLIF N_80_0.BLIF CLK_000_N_SYNC_4_.BLIF \
|
|
a_i_27__n.BLIF CLK_EXP_c_i.BLIF a_3__n.BLIF CLK_000_N_SYNC_5_.BLIF \
|
|
a_i_28__n.BLIF N_258_0.BLIF CLK_000_N_SYNC_6_.BLIF a_i_25__n.BLIF N_283_i.BLIF \
|
|
a_2__n.BLIF CLK_000_N_SYNC_7_.BLIF a_i_26__n.BLIF N_284_i.BLIF \
|
|
CLK_000_N_SYNC_8_.BLIF UDS_000_INT_i.BLIF CLK_000_N_SYNC_9_.BLIF \
|
|
LDS_000_INT_i.BLIF N_290_i.BLIF CLK_000_N_SYNC_10_.BLIF DS_030_i.BLIF \
|
|
N_291_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_224_i.BLIF \
|
|
inst_RW_000_INT.BLIF N_225_i.BLIF N_279_i.BLIF inst_RW_000_DMA.BLIF \
|
|
N_226_i.BLIF N_293_i.BLIF inst_A0_DMA.BLIF inst_CLK_030_H.BLIF N_82_i.BLIF \
|
|
SM_AMIGA_1_.BLIF N_83_i.BLIF SM_AMIGA_4_.BLIF N_104_i.BLIF N_259_0.BLIF \
|
|
SM_AMIGA_2_.BLIF N_103_i.BLIF N_84_i.BLIF pos_clk_un3_as_030_d0_n.BLIF \
|
|
N_282_i.BLIF N_115_0.BLIF inst_DS_000_ENABLE.BLIF N_92_i.BLIF N_85_i.BLIF \
|
|
AS_000_INT_1_sqmuxa.BLIF un6_lds_000_i.BLIF N_294_i.BLIF \
|
|
DS_000_ENABLE_1_sqmuxa_1.BLIF un6_uds_000_i.BLIF N_296_i.BLIF \
|
|
pos_clk_a0_dma_3_n.BLIF un6_ds_030_i.BLIF pos_clk_cpu_est_11_0_3__n.BLIF \
|
|
pos_clk_ds_000_dma_4_n.BLIF DS_000_DMA_i.BLIF N_91_i.BLIF N_3.BLIF \
|
|
un4_as_000_i.BLIF N_260_0.BLIF AS_000_INT_i.BLIF N_301_i.BLIF \
|
|
un6_as_030_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF N_6.BLIF \
|
|
AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_305_i.BLIF N_8.BLIF DS_030_D0_i.BLIF \
|
|
N_306_i.BLIF N_9.BLIF AS_030_c.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_10.BLIF \
|
|
N_307_i.BLIF N_11.BLIF AS_000_c.BLIF N_12.BLIF N_13.BLIF RW_000_c.BLIF \
|
|
N_15.BLIF N_265_0.BLIF N_16.BLIF DS_030_c.BLIF N_269_i.BLIF N_19.BLIF \
|
|
pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_20.BLIF UDS_000_c.BLIF N_62_0.BLIF \
|
|
N_21.BLIF N_276_0.BLIF N_23.BLIF LDS_000_c.BLIF N_277_0.BLIF N_24.BLIF \
|
|
N_286_i.BLIF N_25.BLIF size_c_0__n.BLIF N_288_i.BLIF N_289_i.BLIF \
|
|
size_c_1__n.BLIF pos_clk_un11_ds_030_d0_i_n.BLIF A0_c_i.BLIF \
|
|
size_c_i_1__n.BLIF N_25_i.BLIF N_32_0.BLIF N_24_i.BLIF N_31_0.BLIF N_23_i.BLIF \
|
|
N_30_0.BLIF ipl_c_i_2__n.BLIF N_54_0.BLIF ipl_c_i_1__n.BLIF N_53_0.BLIF \
|
|
ipl_c_i_0__n.BLIF N_52_0.BLIF nEXP_SPACE_c_i.BLIF N_55_0.BLIF N_50_0.BLIF \
|
|
N_3_i.BLIF N_49_0.BLIF N_6_i.BLIF N_48_0.BLIF N_8_i.BLIF N_46_0.BLIF \
|
|
N_9_i.BLIF N_45_0.BLIF N_12_i.BLIF SM_AMIGA_i_7_.BLIF N_43_0.BLIF N_115.BLIF \
|
|
N_13_i.BLIF pos_clk_size_dma_6_0__n.BLIF a_c_16__n.BLIF N_42_0.BLIF \
|
|
pos_clk_size_dma_6_1__n.BLIF N_15_i.BLIF pos_clk_cpu_est_11_3__n.BLIF \
|
|
a_c_17__n.BLIF N_40_0.BLIF G_165.BLIF N_16_i.BLIF G_166.BLIF a_c_18__n.BLIF \
|
|
N_39_0.BLIF G_167.BLIF N_19_i.BLIF un6_uds_000_1.BLIF a_c_19__n.BLIF \
|
|
N_36_0.BLIF pos_clk_un24_bgack_030_int_i_0_n.BLIF N_20_i.BLIF N_245.BLIF \
|
|
a_c_20__n.BLIF N_35_0.BLIF N_246.BLIF N_21_i.BLIF N_247.BLIF a_c_21__n.BLIF \
|
|
N_34_0.BLIF N_248.BLIF BG_030_c_i.BLIF N_89.BLIF a_c_22__n.BLIF \
|
|
pos_clk_un6_bg_030_i_n.BLIF N_92.BLIF pos_clk_un8_bg_030_0_n.BLIF N_102.BLIF \
|
|
a_c_23__n.BLIF N_127_i_1.BLIF N_103.BLIF N_127_i_2.BLIF N_104.BLIF \
|
|
a_c_24__n.BLIF pos_clk_un24_bgack_030_int_i_0_i_1_n.BLIF N_112.BLIF \
|
|
N_80_0_1.BLIF N_256.BLIF a_c_25__n.BLIF N_75_i_1.BLIF N_258.BLIF \
|
|
N_251_0_1.BLIF a_c_26__n.BLIF pos_clk_un11_ds_030_d0_i_1_n.BLIF N_260.BLIF \
|
|
N_340_1.BLIF N_265.BLIF a_c_27__n.BLIF N_340_2.BLIF N_282.BLIF N_340_3.BLIF \
|
|
N_71.BLIF a_c_28__n.BLIF N_340_4.BLIF cpu_est_0_0_x2_0_.BLIF un5_ciin_1.BLIF \
|
|
pos_clk_un11_clk_000_n_sync_n.BLIF a_c_29__n.BLIF un5_ciin_2.BLIF N_76.BLIF \
|
|
un5_ciin_3.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF a_c_30__n.BLIF un5_ciin_4.BLIF \
|
|
pos_clk_CYCLE_DMA_5_0_i_x2.BLIF un5_ciin_5.BLIF \
|
|
pos_clk_un24_bgack_030_int_i_0_x2.BLIF a_c_31__n.BLIF un5_ciin_6.BLIF \
|
|
pos_clk_un22_bgack_030_int_n.BLIF un5_ciin_7.BLIF N_268.BLIF A0_c.BLIF \
|
|
un5_ciin_8.BLIF N_270.BLIF un5_ciin_9.BLIF N_73.BLIF A1_c.BLIF \
|
|
un5_ciin_10.BLIF N_75.BLIF un5_ciin_11.BLIF N_251.BLIF nEXP_SPACE_c.BLIF \
|
|
un22_berr_1_0.BLIF un22_berr_1.BLIF un21_fpu_cs_1.BLIF N_95.BLIF BERR_c.BLIF \
|
|
pos_clk_un6_bg_030_1_n.BLIF N_94.BLIF N_131_i_1.BLIF N_288.BLIF BG_030_c.BLIF \
|
|
N_131_i_2.BLIF N_289.BLIF N_131_i_3.BLIF N_286.BLIF BG_000DFFreg.BLIF \
|
|
N_96_1.BLIF N_279.BLIF N_96_2.BLIF N_277.BLIF N_96_3.BLIF N_276.BLIF \
|
|
BGACK_000_c.BLIF pos_clk_cpu_est_11_0_1_1__n.BLIF N_62.BLIF \
|
|
pos_clk_cpu_est_11_0_2_1__n.BLIF N_274.BLIF N_310_1.BLIF N_313.BLIF \
|
|
N_310_2.BLIF N_307.BLIF N_310_3.BLIF N_305.BLIF CLK_OSZI_c.BLIF N_310_4.BLIF \
|
|
N_306.BLIF N_309_1.BLIF N_303.BLIF N_309_2.BLIF N_304.BLIF CLK_EXP_c.BLIF \
|
|
N_308_1.BLIF N_301.BLIF N_308_2.BLIF N_91.BLIF RESET_OUT_0_sqmuxa_5_1.BLIF \
|
|
N_85.BLIF FPU_SENSE_c.BLIF RESET_OUT_0_sqmuxa_7_1.BLIF N_294.BLIF \
|
|
RESET_OUT_0_sqmuxa_7_2.BLIF N_296.BLIF IPL_030DFF_0_reg.BLIF \
|
|
RESET_OUT_0_sqmuxa_7_3.BLIF N_84.BLIF N_94_1.BLIF N_82.BLIF \
|
|
IPL_030DFF_1_reg.BLIF N_95_1.BLIF N_83.BLIF N_119_i_1.BLIF N_293.BLIF \
|
|
IPL_030DFF_2_reg.BLIF N_82_1.BLIF N_290.BLIF N_83_1.BLIF N_291.BLIF \
|
|
ipl_c_0__n.BLIF N_296_1.BLIF N_283.BLIF N_303_1.BLIF N_284.BLIF \
|
|
ipl_c_1__n.BLIF N_304_1.BLIF N_86.BLIF N_306_1.BLIF N_80.BLIF ipl_c_2__n.BLIF \
|
|
N_129_i_1.BLIF N_78.BLIF N_125_i_1.BLIF N_108.BLIF N_123_i_1.BLIF N_109.BLIF \
|
|
DTACK_c.BLIF N_115_0_1.BLIF N_100.BLIF pos_clk_cpu_est_11_0_1_3__n.BLIF \
|
|
N_99.BLIF N_260_0_1.BLIF N_93.BLIF N_261_i_1.BLIF \
|
|
pos_clk_un14_clk_000_n_sync_n.BLIF VPA_c.BLIF N_262_i_1.BLIF \
|
|
pos_clk_un9_clk_000_n_sync_n.BLIF N_263_i_1.BLIF N_340.BLIF \
|
|
pos_clk_ipl_1_n.BLIF N_97.BLIF RST_c.BLIF cpu_est_0_3__un3_n.BLIF N_136.BLIF \
|
|
cpu_est_0_3__un1_n.BLIF N_101.BLIF cpu_est_0_3__un0_n.BLIF N_81.BLIF RW_c.BLIF \
|
|
cpu_est_0_2__un3_n.BLIF N_116.BLIF cpu_est_0_2__un1_n.BLIF N_96.BLIF \
|
|
fc_c_0__n.BLIF cpu_est_0_2__un0_n.BLIF N_113.BLIF cpu_est_0_1__un3_n.BLIF \
|
|
N_275.BLIF fc_c_1__n.BLIF cpu_est_0_1__un1_n.BLIF N_273.BLIF \
|
|
cpu_est_0_1__un0_n.BLIF N_88.BLIF bgack_030_int_0_un3_n.BLIF N_272.BLIF \
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AMIGA_BUS_DATA_DIR_c.BLIF bgack_030_int_0_un1_n.BLIF N_299.BLIF \
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bgack_030_int_0_un0_n.BLIF N_90.BLIF vma_int_0_un3_n.BLIF N_311.BLIF \
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vma_int_0_un1_n.BLIF N_312.BLIF vma_int_0_un0_n.BLIF N_267.BLIF \
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un1_as_000_i.BLIF rw_000_int_0_un3_n.BLIF N_264.BLIF \
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un1_rst_dly_i_m_i_3__n.BLIF rw_000_int_0_un1_n.BLIF \
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pos_clk_un7_clk_000_pe_n.BLIF rw_000_int_0_un0_n.BLIF N_308.BLIF \
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un1_rst_dly_i_m_i_4__n.BLIF sm_amiga_srsts_i_0_m2_3__un3_n.BLIF N_309.BLIF \
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sm_amiga_srsts_i_0_m2_3__un1_n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
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RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
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SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
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.outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E \
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VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
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AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_030DFF_2_reg.D \
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IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \
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IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \
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SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D \
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SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \
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SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \
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cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \
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IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \
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CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \
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CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C RST_DLY_0_.D \
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RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D \
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RST_DLY_3_.C RST_DLY_4_.D RST_DLY_4_.C RST_DLY_5_.D RST_DLY_5_.C RST_DLY_6_.D \
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RST_DLY_6_.C RST_DLY_7_.D RST_DLY_7_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \
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CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
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SIZE_DMA_1_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \
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CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \
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CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \
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CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \
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CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \
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CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \
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CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \
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CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \
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CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \
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CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \
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CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \
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CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \
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CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C inst_CLK_030_H.D inst_CLK_030_H.C \
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inst_RESET_OUTreg.D inst_RESET_OUTreg.C inst_DS_000_ENABLE.D \
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inst_DS_000_ENABLE.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_RW_000_DMA.D \
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inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D \
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inst_LDS_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
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inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
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inst_A0_DMA.D inst_A0_DMA.C inst_AS_000_DMA.D inst_AS_000_DMA.C \
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inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_030_D0.D inst_DS_030_D0.C \
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inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \
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inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \
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inst_DTACK_D0.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C BG_000DFFreg.D \
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BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
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inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \
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inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
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inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_PE.D \
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inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \
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inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D \
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inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \
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inst_CLK_000_D0.D inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 RW_000 DS_030 \
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UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_310 un1_rst_dly_i_m_i_5__n \
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sm_amiga_srsts_i_0_m2_3__un0_n N_220 sm_amiga_srsts_i_0_m2_1__un3_n \
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pos_clk_cpu_est_11_1__n un1_rst_dly_i_m_i_6__n sm_amiga_srsts_i_0_m2_1__un1_n \
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N_14 sm_amiga_srsts_i_0_m2_1__un0_n N_18 un1_rst_dly_i_m_i_7__n \
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un1_amiga_bus_enable_dma_high_0_m2_0__un3_n N_22 \
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un1_amiga_bus_enable_dma_high_0_m2_0__un1_n RESET_OUT_0_sqmuxa_1 \
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un1_rst_dly_i_m_i_8__n un1_amiga_bus_enable_dma_high_0_m2_0__un0_n vcc_n_n \
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|
N_205 un1_sm_amiga_7_i_m2_un3_n N_213 un1_rst_dly_i_m_i_2__n \
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un1_sm_amiga_7_i_m2_un1_n un1_sm_amiga_7_i_m2_un0_n N_105 N_98_i \
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size_dma_0_0__un3_n gnd_n_n N_98 size_dma_0_0__un1_n un1_amiga_bus_enable_low \
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RESET_OUT_0_sqmuxa N_105_i size_dma_0_0__un0_n un6_as_030 un1_rst_dly_i_m_2__n \
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size_dma_0_1__un3_n un3_size N_22_i size_dma_0_1__un1_n un4_size \
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un1_rst_dly_i_m_8__n N_33_0 size_dma_0_1__un0_n un5_ciin N_18_i \
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ipl_030_0_0__un3_n un4_as_000 RESET_OUT_0_sqmuxa_5 N_37_0 ipl_030_0_0__un1_n \
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|
un21_fpu_cs RESET_OUT_0_sqmuxa_7 N_14_i ipl_030_0_0__un0_n un22_berr N_41_0 \
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ipl_030_0_1__un3_n un6_ds_030 N_10_i ipl_030_0_1__un1_n un6_uds_000 N_211 \
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N_44_0 ipl_030_0_1__un0_n un6_lds_000 pos_clk_cpu_est_11_0_1__n \
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ipl_030_0_2__un3_n N_209 N_312_i ipl_030_0_2__un1_n N_90_i ipl_030_0_2__un0_n \
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N_88_i amiga_bus_enable_dma_high_0_un3_n un1_rst_dly_i_m_7__n N_299_i \
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amiga_bus_enable_dma_high_0_un1_n un1_rst_dly_i_m_6__n N_275_0 \
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amiga_bus_enable_dma_high_0_un0_n un1_rst_dly_i_m_5__n N_274_0 bg_000_0_un3_n \
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un1_rst_dly_i_m_4__n N_273_i bg_000_0_un1_n un1_rst_dly_i_m_3__n N_272_i \
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bg_000_0_un0_n N_71_i N_270_i ds_000_dma_0_un3_n un1_amiga_bus_enable_low_i \
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|
N_268_i ds_000_dma_0_un1_n un21_fpu_cs_i N_310_i ds_000_dma_0_un0_n \
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|
RESET_OUT_i N_311_i as_000_dma_0_un3_n BGACK_030_INT_i N_267_0 \
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|
as_000_dma_0_un1_n RESET_OUT_0_sqmuxa_i N_309_i as_000_dma_0_un0_n \
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|
un1_rst_dly_i_3__n N_308_i a0_dma_0_un3_n un1_rst_dly_i_4__n \
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|
pos_clk_un7_clk_000_pe_0_n a0_dma_0_un1_n un1_rst_dly_i_5__n N_264_0 \
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|
a0_dma_0_un0_n un1_rst_dly_i_6__n N_304_i dsack1_int_0_un3_n \
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|
un1_rst_dly_i_7__n N_303_i dsack1_int_0_un1_n un1_rst_dly_i_8__n N_186_i \
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|
dsack1_int_0_un0_n un1_rst_dly_i_2__n VPA_c_i as_000_int_0_un3_n N_87_i_i \
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N_56_0 as_000_int_0_un1_n cpu_est_i_3__n DTACK_c_i as_000_int_0_un0_n \
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|
cpu_est_i_0__n N_57_0 ds_000_enable_0_un3_n VPA_D_i N_97_i \
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|
ds_000_enable_0_un1_n VMA_INT_i ds_000_enable_0_un0_n cpu_est_i_1__n N_96_i \
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|
as_030_000_sync_0_un3_n CLK_000_PE_i N_95_i as_030_000_sync_0_un1_n BERR_i \
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|
N_94_i as_030_000_sync_0_un0_n sm_amiga_i_4__n N_313_i lds_000_int_0_un3_n \
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|
cpu_est_i_2__n N_136_i lds_000_int_0_un1_n sm_amiga_i_5__n N_81_0 \
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lds_000_int_0_un0_n DTACK_D0_i N_116_i rw_000_dma_0_un3_n sm_amiga_i_0__n \
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|
N_77_i rw_000_dma_0_un1_n pos_clk_un6_bg_030_n sm_amiga_i_3__n N_73_i \
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|
rw_000_dma_0_un0_n CLK_000_NE_i N_101_i uds_000_int_0_un3_n sm_amiga_i_6__n \
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|
uds_000_int_0_un1_n sm_amiga_i_1__n clk_000_n_sync_i_10__n uds_000_int_0_un0_n \
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|
CLK_OUT_PRE_D_i pos_clk_un9_clk_000_n_sync_i_n \
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|
amiga_bus_enable_dma_low_0_un3_n pos_clk_ipl_n pos_clk_un11_clk_000_n_sync_i_n \
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|
pos_clk_un14_clk_000_n_sync_0_n amiga_bus_enable_dma_low_0_un1_n \
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|
pos_clk_un3_ds_030_d0_n LDS_000_i pos_clk_un22_bgack_030_int_i_n \
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|
amiga_bus_enable_dma_low_0_un0_n UDS_000_i N_86_i a_15__n \
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|
AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa nEXP_SPACE_D0_i N_93_i sm_amiga_i_2__n \
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|
a_14__n AS_030_i N_99_i A1_i pos_clk_size_dma_6_0_1__n a_13__n CLK_000_D1_i \
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|
N_100_i RW_000_i pos_clk_size_dma_6_0_0__n a_12__n CLK_030_H_i N_245_0 \
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|
AS_000_DMA_i N_108_i a_11__n AS_000_i N_109_i pos_clk_un8_bg_030_n \
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|
sm_amiga_i_i_7__n N_246_0 a_10__n RW_i un5_ciin_i AMIGA_BUS_ENABLE_DMA_HIGH_i \
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|
N_247_0 a_9__n FPU_SENSE_i N_248_0 AS_030_D0_i CLK_000_D0_i a_8__n a_i_24__n \
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|
N_249_i size_dma_i_0__n AS_030_000_SYNC_i a_7__n size_dma_i_1__n N_251_0 \
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|
a_i_16__n pos_clk_un3_as_030_d0_i_n a_6__n a_i_18__n \
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|
pos_clk_un5_bgack_030_int_d_i_n a_i_19__n N_75_i a_5__n a_i_31__n N_76_i \
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|
a_i_29__n N_78_0 a_4__n a_i_30__n N_80_0 a_i_27__n CLK_EXP_c_i a_3__n \
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|
a_i_28__n N_258_0 a_i_25__n N_283_i a_2__n a_i_26__n N_284_i UDS_000_INT_i \
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|
LDS_000_INT_i N_290_i DS_030_i N_291_i pos_clk_un5_bgack_030_int_d_n N_224_i \
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|
N_225_i N_279_i N_226_i N_293_i N_82_i N_83_i N_104_i N_259_0 N_103_i N_84_i \
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|
pos_clk_un3_as_030_d0_n N_282_i N_115_0 N_92_i N_85_i AS_000_INT_1_sqmuxa \
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|
un6_lds_000_i N_294_i DS_000_ENABLE_1_sqmuxa_1 un6_uds_000_i N_296_i \
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|
pos_clk_a0_dma_3_n un6_ds_030_i pos_clk_cpu_est_11_0_3__n \
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|
pos_clk_ds_000_dma_4_n DS_000_DMA_i N_91_i N_3 un4_as_000_i N_260_0 \
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|
AS_000_INT_i N_301_i un6_as_030_i pos_clk_ds_000_dma_4_0_n N_6 \
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|
AMIGA_BUS_ENABLE_DMA_LOW_i N_305_i N_8 DS_030_D0_i N_306_i N_9 AS_030_c \
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|
AMIGA_BUS_DATA_DIR_c_0 N_10 N_307_i N_11 AS_000_c N_12 N_13 RW_000_c N_15 \
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|
N_265_0 N_16 DS_030_c N_269_i N_19 pos_clk_un24_bgack_030_int_i_0_i_n N_20 \
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|
UDS_000_c N_62_0 N_21 N_276_0 N_23 LDS_000_c N_277_0 N_24 N_286_i N_25 \
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|
size_c_0__n N_288_i N_289_i size_c_1__n pos_clk_un11_ds_030_d0_i_n A0_c_i \
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|
size_c_i_1__n N_25_i N_32_0 N_24_i N_31_0 N_23_i N_30_0 ipl_c_i_2__n N_54_0 \
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|
ipl_c_i_1__n N_53_0 ipl_c_i_0__n N_52_0 nEXP_SPACE_c_i N_55_0 N_50_0 N_3_i \
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|
N_49_0 N_6_i N_48_0 N_8_i N_46_0 N_9_i N_45_0 N_12_i N_43_0 N_115 N_13_i \
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|
pos_clk_size_dma_6_0__n a_c_16__n N_42_0 pos_clk_size_dma_6_1__n N_15_i \
|
|
pos_clk_cpu_est_11_3__n a_c_17__n N_40_0 N_16_i a_c_18__n N_39_0 N_19_i \
|
|
un6_uds_000_1 a_c_19__n N_36_0 pos_clk_un24_bgack_030_int_i_0_n N_20_i N_245 \
|
|
a_c_20__n N_35_0 N_246 N_21_i N_247 a_c_21__n N_34_0 N_248 BG_030_c_i N_89 \
|
|
a_c_22__n pos_clk_un6_bg_030_i_n N_92 pos_clk_un8_bg_030_0_n N_102 a_c_23__n \
|
|
N_127_i_1 N_103 N_127_i_2 N_104 a_c_24__n pos_clk_un24_bgack_030_int_i_0_i_1_n \
|
|
N_112 N_80_0_1 N_256 a_c_25__n N_75_i_1 N_258 N_251_0_1 a_c_26__n \
|
|
pos_clk_un11_ds_030_d0_i_1_n N_260 N_340_1 N_265 a_c_27__n N_340_2 N_282 \
|
|
N_340_3 N_71 a_c_28__n N_340_4 un5_ciin_1 pos_clk_un11_clk_000_n_sync_n \
|
|
a_c_29__n un5_ciin_2 N_76 un5_ciin_3 a_c_30__n un5_ciin_4 un5_ciin_5 a_c_31__n \
|
|
un5_ciin_6 pos_clk_un22_bgack_030_int_n un5_ciin_7 N_268 A0_c un5_ciin_8 N_270 \
|
|
un5_ciin_9 N_73 A1_c un5_ciin_10 N_75 un5_ciin_11 N_251 nEXP_SPACE_c \
|
|
un22_berr_1_0 un22_berr_1 un21_fpu_cs_1 N_95 BERR_c pos_clk_un6_bg_030_1_n \
|
|
N_94 N_131_i_1 N_288 BG_030_c N_131_i_2 N_289 N_131_i_3 N_286 N_96_1 N_279 \
|
|
N_96_2 N_277 N_96_3 N_276 BGACK_000_c pos_clk_cpu_est_11_0_1_1__n N_62 \
|
|
pos_clk_cpu_est_11_0_2_1__n N_274 N_310_1 N_313 N_310_2 N_307 N_310_3 N_305 \
|
|
CLK_OSZI_c N_310_4 N_306 N_309_1 N_303 N_309_2 N_304 CLK_EXP_c N_308_1 N_301 \
|
|
N_308_2 N_91 RESET_OUT_0_sqmuxa_5_1 N_85 FPU_SENSE_c RESET_OUT_0_sqmuxa_7_1 \
|
|
N_294 RESET_OUT_0_sqmuxa_7_2 N_296 RESET_OUT_0_sqmuxa_7_3 N_84 N_94_1 N_82 \
|
|
N_95_1 N_83 N_119_i_1 N_293 N_82_1 N_290 N_83_1 N_291 ipl_c_0__n N_296_1 N_283 \
|
|
N_303_1 N_284 ipl_c_1__n N_304_1 N_86 N_306_1 N_80 ipl_c_2__n N_129_i_1 N_78 \
|
|
N_125_i_1 N_108 N_123_i_1 N_109 DTACK_c N_115_0_1 N_100 \
|
|
pos_clk_cpu_est_11_0_1_3__n N_99 N_260_0_1 N_93 N_261_i_1 \
|
|
pos_clk_un14_clk_000_n_sync_n VPA_c N_262_i_1 pos_clk_un9_clk_000_n_sync_n \
|
|
N_263_i_1 N_340 pos_clk_ipl_1_n N_97 RST_c cpu_est_0_3__un3_n N_136 \
|
|
cpu_est_0_3__un1_n N_101 cpu_est_0_3__un0_n N_81 RW_c cpu_est_0_2__un3_n N_116 \
|
|
cpu_est_0_2__un1_n N_96 fc_c_0__n cpu_est_0_2__un0_n N_113 cpu_est_0_1__un3_n \
|
|
N_275 fc_c_1__n cpu_est_0_1__un1_n N_273 cpu_est_0_1__un0_n N_88 \
|
|
bgack_030_int_0_un3_n N_272 AMIGA_BUS_DATA_DIR_c bgack_030_int_0_un1_n N_299 \
|
|
bgack_030_int_0_un0_n N_90 vma_int_0_un3_n N_311 vma_int_0_un1_n N_312 \
|
|
vma_int_0_un0_n N_267 un1_as_000_i rw_000_int_0_un3_n N_264 \
|
|
un1_rst_dly_i_m_i_3__n rw_000_int_0_un1_n pos_clk_un7_clk_000_pe_n \
|
|
rw_000_int_0_un0_n N_308 un1_rst_dly_i_m_i_4__n sm_amiga_srsts_i_0_m2_3__un3_n \
|
|
N_309 sm_amiga_srsts_i_0_m2_3__un1_n AS_030.OE AS_000.OE RW_000.OE DS_030.OE \
|
|
UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE \
|
|
DSACK1.OE CIIN.OE pos_clk_RST_DLY_5_iv_0_x2_0_ G_137 G_149 G_147 G_145 G_143 \
|
|
G_141 G_139 G_165 G_166 G_167 cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 \
|
|
pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_un24_bgack_030_int_i_0_x2
|
|
.names N_32_0.BLIF IPL_030DFF_2_reg.D
|
|
0 1
|
|
.names N_52_0.BLIF IPL_D0_0_.D
|
|
0 1
|
|
.names N_53_0.BLIF IPL_D0_1_.D
|
|
0 1
|
|
.names N_54_0.BLIF IPL_D0_2_.D
|
|
0 1
|
|
.names N_131_i_3.BLIF N_96_i.BLIF SM_AMIGA_i_7_.D
|
|
11 1
|
|
.names N_129_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D
|
|
11 1
|
|
.names N_127_i_1.BLIF N_127_i_2.BLIF SM_AMIGA_5_.D
|
|
11 1
|
|
.names N_125_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D
|
|
11 1
|
|
.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D
|
|
11 1
|
|
.names N_259_0.BLIF SM_AMIGA_2_.D
|
|
0 1
|
|
.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D
|
|
11 1
|
|
.names N_77_i.BLIF N_101_i.BLIF SM_AMIGA_0_.D
|
|
11 1
|
|
.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D
|
|
1- 1
|
|
-1 1
|
|
.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D
|
|
1- 1
|
|
-1 1
|
|
.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D
|
|
1- 1
|
|
-1 1
|
|
.names N_30_0.BLIF IPL_030DFF_0_reg.D
|
|
0 1
|
|
.names N_31_0.BLIF IPL_030DFF_1_reg.D
|
|
0 1
|
|
.names N_98_i.BLIF RST_c.BLIF RST_DLY_0_.D
|
|
11 1
|
|
.names RST_c.BLIF un1_rst_dly_i_m_i_2__n.BLIF RST_DLY_1_.D
|
|
11 1
|
|
.names RST_c.BLIF un1_rst_dly_i_m_i_3__n.BLIF RST_DLY_2_.D
|
|
11 1
|
|
.names RST_c.BLIF un1_rst_dly_i_m_i_4__n.BLIF RST_DLY_3_.D
|
|
11 1
|
|
.names RST_c.BLIF un1_rst_dly_i_m_i_5__n.BLIF RST_DLY_4_.D
|
|
11 1
|
|
.names RST_c.BLIF un1_rst_dly_i_m_i_6__n.BLIF RST_DLY_5_.D
|
|
11 1
|
|
.names RST_c.BLIF un1_rst_dly_i_m_i_7__n.BLIF RST_DLY_6_.D
|
|
11 1
|
|
.names RST_c.BLIF un1_rst_dly_i_m_i_8__n.BLIF RST_DLY_7_.D
|
|
11 1
|
|
.names N_263_i_1.BLIF RST_c.BLIF CYCLE_DMA_0_.D
|
|
11 1
|
|
.names N_262_i_1.BLIF RST_c.BLIF CYCLE_DMA_1_.D
|
|
11 1
|
|
.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D
|
|
1- 1
|
|
-1 1
|
|
.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D
|
|
1- 1
|
|
-1 1
|
|
.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D
|
|
11 1
|
|
.names N_261_i_1.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF inst_CLK_030_H.D
|
|
11 1
|
|
.names N_105_i.BLIF RST_c.BLIF inst_RESET_OUTreg.D
|
|
11 1
|
|
.names N_11.BLIF RST_c.BLIF inst_DS_000_ENABLE.D
|
|
11 1
|
|
.names N_39_0.BLIF inst_UDS_000_INT.D
|
|
0 1
|
|
.names N_40_0.BLIF inst_RW_000_DMA.D
|
|
0 1
|
|
.names N_41_0.BLIF inst_RW_000_INT.D
|
|
0 1
|
|
.names N_42_0.BLIF inst_LDS_000_INT.D
|
|
0 1
|
|
.names N_43_0.BLIF inst_AS_030_000_SYNC.D
|
|
0 1
|
|
.names N_44_0.BLIF inst_AS_000_INT.D
|
|
0 1
|
|
.names N_45_0.BLIF inst_DSACK1_INTreg.D
|
|
0 1
|
|
.names N_46_0.BLIF inst_A0_DMA.D
|
|
0 1
|
|
.names N_48_0.BLIF inst_AS_000_DMA.D
|
|
0 1
|
|
.names N_49_0.BLIF inst_DS_000_DMA.D
|
|
0 1
|
|
.names N_50_0.BLIF inst_DS_030_D0.D
|
|
0 1
|
|
.names N_102.BLIF inst_AS_030_D0.D
|
|
0 1
|
|
.names N_55_0.BLIF inst_nEXP_SPACE_D0reg.D
|
|
0 1
|
|
.names N_56_0.BLIF inst_VPA_D.D
|
|
0 1
|
|
.names N_57_0.BLIF inst_DTACK_D0.D
|
|
0 1
|
|
.names N_33_0.BLIF inst_BGACK_030_INTreg.D
|
|
0 1
|
|
.names N_34_0.BLIF BG_000DFFreg.D
|
|
0 1
|
|
.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D
|
|
0 1
|
|
.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D
|
|
0 1
|
|
.names N_37_0.BLIF inst_VMA_INTreg.D
|
|
0 1
|
|
.names AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa.BLIF inst_BGACK_030_INT_D.D
|
|
0 1
|
|
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
|
|
0 1
|
|
.names N_310_4.BLIF N_310_3.BLIF N_310
|
|
11 1
|
|
.names un1_rst_dly_i_m_5__n.BLIF un1_rst_dly_i_m_i_5__n
|
|
0 1
|
|
.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_3__un3_n.BLIF \
|
|
sm_amiga_srsts_i_0_m2_3__un0_n
|
|
11 1
|
|
.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_220
|
|
11 1
|
|
.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n
|
|
0 1
|
|
.names pos_clk_cpu_est_11_0_1__n.BLIF pos_clk_cpu_est_11_1__n
|
|
0 1
|
|
.names un1_rst_dly_i_m_6__n.BLIF un1_rst_dly_i_m_i_6__n
|
|
0 1
|
|
.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n
|
|
11 1
|
|
.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_14
|
|
1- 1
|
|
-1 1
|
|
.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \
|
|
sm_amiga_srsts_i_0_m2_1__un0_n
|
|
11 1
|
|
.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_18
|
|
1- 1
|
|
-1 1
|
|
.names un1_rst_dly_i_m_7__n.BLIF un1_rst_dly_i_m_i_7__n
|
|
0 1
|
|
.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n
|
|
0 1
|
|
.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_22
|
|
1- 1
|
|
-1 1
|
|
.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF \
|
|
un1_amiga_bus_enable_dma_high_0_m2_0__un1_n
|
|
11 1
|
|
.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RESET_OUT_0_sqmuxa_1
|
|
11 1
|
|
.names un1_rst_dly_i_m_8__n.BLIF un1_rst_dly_i_m_i_8__n
|
|
0 1
|
|
.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \
|
|
un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \
|
|
un1_amiga_bus_enable_dma_high_0_m2_0__un0_n
|
|
11 1
|
|
.names vcc_n_n
|
|
1
|
|
.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF N_205
|
|
11 1
|
|
.names SM_AMIGA_5_.BLIF un1_sm_amiga_7_i_m2_un3_n
|
|
0 1
|
|
.names N_211.BLIF RST_DLY_5_.BLIF N_213
|
|
11 1
|
|
.names un1_rst_dly_i_m_2__n.BLIF un1_rst_dly_i_m_i_2__n
|
|
0 1
|
|
.names RW_i.BLIF SM_AMIGA_5_.BLIF un1_sm_amiga_7_i_m2_un1_n
|
|
11 1
|
|
.names sm_amiga_i_3__n.BLIF un1_sm_amiga_7_i_m2_un3_n.BLIF \
|
|
un1_sm_amiga_7_i_m2_un0_n
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_i.BLIF RESET_OUT_i.BLIF N_105
|
|
11 1
|
|
.names N_98.BLIF N_98_i
|
|
0 1
|
|
.names N_248.BLIF size_dma_0_0__un3_n
|
|
0 1
|
|
.names gnd_n_n
|
|
.names N_87_i_i.BLIF RESET_OUT_0_sqmuxa_i.BLIF N_98
|
|
11 1
|
|
.names pos_clk_size_dma_6_0__n.BLIF N_248.BLIF size_dma_0_0__un1_n
|
|
11 1
|
|
.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \
|
|
un1_amiga_bus_enable_low
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF RESET_OUT_0_sqmuxa
|
|
11 1
|
|
.names N_105.BLIF N_105_i
|
|
0 1
|
|
.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n
|
|
11 1
|
|
.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_2__n.BLIF un1_rst_dly_i_m_2__n
|
|
11 1
|
|
.names N_248.BLIF size_dma_0_1__un3_n
|
|
0 1
|
|
.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size
|
|
11 1
|
|
.names N_22.BLIF N_22_i
|
|
0 1
|
|
.names pos_clk_size_dma_6_1__n.BLIF N_248.BLIF size_dma_0_1__un1_n
|
|
11 1
|
|
.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_8__n.BLIF un1_rst_dly_i_m_8__n
|
|
11 1
|
|
.names N_22_i.BLIF RST_c.BLIF N_33_0
|
|
11 1
|
|
.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n
|
|
11 1
|
|
.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin
|
|
11 1
|
|
.names N_18.BLIF N_18_i
|
|
0 1
|
|
.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n
|
|
0 1
|
|
.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_5_1.BLIF RST_DLY_2_.BLIF RESET_OUT_0_sqmuxa_5
|
|
11 1
|
|
.names N_18_i.BLIF RST_c.BLIF N_37_0
|
|
11 1
|
|
.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n
|
|
11 1
|
|
.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_7_3.BLIF RST_DLY_6_.BLIF RESET_OUT_0_sqmuxa_7
|
|
11 1
|
|
.names N_14.BLIF N_14_i
|
|
0 1
|
|
.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
|
|
11 1
|
|
.names un22_berr_1_0.BLIF N_340.BLIF un22_berr
|
|
11 1
|
|
.names N_14_i.BLIF RST_c.BLIF N_41_0
|
|
11 1
|
|
.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n
|
|
0 1
|
|
.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030
|
|
11 1
|
|
.names N_10.BLIF N_10_i
|
|
0 1
|
|
.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n
|
|
11 1
|
|
.names UDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_uds_000
|
|
11 1
|
|
.names N_209.BLIF RST_DLY_4_.BLIF N_211
|
|
11 1
|
|
.names N_10_i.BLIF RST_c.BLIF N_44_0
|
|
11 1
|
|
.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
|
|
11 1
|
|
.names LDS_000_INT_i.BLIF un6_uds_000_1.BLIF un6_lds_000
|
|
11 1
|
|
.names pos_clk_cpu_est_11_0_1_1__n.BLIF pos_clk_cpu_est_11_0_2_1__n.BLIF \
|
|
pos_clk_cpu_est_11_0_1__n
|
|
11 1
|
|
.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n
|
|
0 1
|
|
.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF N_209
|
|
11 1
|
|
.names N_312.BLIF N_312_i
|
|
0 1
|
|
.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n
|
|
11 1
|
|
.names N_90.BLIF N_90_i
|
|
0 1
|
|
.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
|
|
11 1
|
|
.names N_88.BLIF N_88_i
|
|
0 1
|
|
.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n
|
|
0 1
|
|
.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_7__n.BLIF un1_rst_dly_i_m_7__n
|
|
11 1
|
|
.names N_299.BLIF N_299_i
|
|
0 1
|
|
.names N_104_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \
|
|
amiga_bus_enable_dma_high_0_un1_n
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_6__n.BLIF un1_rst_dly_i_m_6__n
|
|
11 1
|
|
.names N_268_i.BLIF SM_AMIGA_4_.BLIF N_275_0
|
|
11 1
|
|
.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \
|
|
amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_5__n.BLIF un1_rst_dly_i_m_5__n
|
|
11 1
|
|
.names N_268.BLIF sm_amiga_i_3__n.BLIF N_274_0
|
|
11 1
|
|
.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n
|
|
0 1
|
|
.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_4__n.BLIF un1_rst_dly_i_m_4__n
|
|
11 1
|
|
.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_273_i
|
|
11 1
|
|
.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_i.BLIF un1_rst_dly_i_3__n.BLIF un1_rst_dly_i_m_3__n
|
|
11 1
|
|
.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_272_i
|
|
11 1
|
|
.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
|
|
11 1
|
|
.names N_71.BLIF N_71_i
|
|
0 1
|
|
.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_270_i
|
|
11 1
|
|
.names N_260.BLIF ds_000_dma_0_un3_n
|
|
0 1
|
|
.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i
|
|
0 1
|
|
.names BERR_c.BLIF CLK_000_PE_i.BLIF N_268_i
|
|
11 1
|
|
.names pos_clk_ds_000_dma_4_n.BLIF N_260.BLIF ds_000_dma_0_un1_n
|
|
11 1
|
|
.names un21_fpu_cs.BLIF un21_fpu_cs_i
|
|
0 1
|
|
.names N_310.BLIF N_310_i
|
|
0 1
|
|
.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
|
|
11 1
|
|
.names inst_RESET_OUTreg.BLIF RESET_OUT_i
|
|
0 1
|
|
.names N_311.BLIF N_311_i
|
|
0 1
|
|
.names N_258.BLIF as_000_dma_0_un3_n
|
|
0 1
|
|
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
|
|
0 1
|
|
.names N_310_i.BLIF N_311_i.BLIF N_267_0
|
|
11 1
|
|
.names pos_clk_un24_bgack_030_int_i_0_n.BLIF N_258.BLIF as_000_dma_0_un1_n
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa.BLIF RESET_OUT_0_sqmuxa_i
|
|
0 1
|
|
.names N_309.BLIF N_309_i
|
|
0 1
|
|
.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
|
|
11 1
|
|
.names G_139.BLIF un1_rst_dly_i_3__n
|
|
0 1
|
|
.names N_308.BLIF N_308_i
|
|
0 1
|
|
.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n
|
|
0 1
|
|
.names G_141.BLIF un1_rst_dly_i_4__n
|
|
0 1
|
|
.names N_308_i.BLIF N_309_i.BLIF pos_clk_un7_clk_000_pe_0_n
|
|
11 1
|
|
.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \
|
|
a0_dma_0_un1_n
|
|
11 1
|
|
.names G_143.BLIF un1_rst_dly_i_5__n
|
|
0 1
|
|
.names RW_i.BLIF SM_AMIGA_5_.BLIF N_264_0
|
|
11 1
|
|
.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n
|
|
11 1
|
|
.names G_145.BLIF un1_rst_dly_i_6__n
|
|
0 1
|
|
.names N_304.BLIF N_304_i
|
|
0 1
|
|
.names N_245.BLIF dsack1_int_0_un3_n
|
|
0 1
|
|
.names G_147.BLIF un1_rst_dly_i_7__n
|
|
0 1
|
|
.names N_303.BLIF N_303_i
|
|
0 1
|
|
.names N_92_i.BLIF N_245.BLIF dsack1_int_0_un1_n
|
|
11 1
|
|
.names G_149.BLIF un1_rst_dly_i_8__n
|
|
0 1
|
|
.names N_303_i.BLIF N_304_i.BLIF N_186_i
|
|
11 1
|
|
.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
|
|
11 1
|
|
.names G_137.BLIF un1_rst_dly_i_2__n
|
|
0 1
|
|
.names VPA_c.BLIF VPA_c_i
|
|
0 1
|
|
.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
|
|
0 1
|
|
.names pos_clk_RST_DLY_5_iv_0_x2_0_.BLIF N_87_i_i
|
|
0 1
|
|
.names RST_c.BLIF VPA_c_i.BLIF N_56_0
|
|
11 1
|
|
.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n
|
|
11 1
|
|
.names cpu_est_3_reg.BLIF cpu_est_i_3__n
|
|
0 1
|
|
.names DTACK_c.BLIF DTACK_c_i
|
|
0 1
|
|
.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
|
|
11 1
|
|
.names cpu_est_0_.BLIF cpu_est_i_0__n
|
|
0 1
|
|
.names DTACK_c_i.BLIF RST_c.BLIF N_57_0
|
|
11 1
|
|
.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n
|
|
0 1
|
|
.names inst_VPA_D.BLIF VPA_D_i
|
|
0 1
|
|
.names N_97.BLIF N_97_i
|
|
0 1
|
|
.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \
|
|
ds_000_enable_0_un1_n
|
|
11 1
|
|
.names inst_VMA_INTreg.BLIF VMA_INT_i
|
|
0 1
|
|
.names N_282_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n
|
|
11 1
|
|
.names cpu_est_1_.BLIF cpu_est_i_1__n
|
|
0 1
|
|
.names N_96.BLIF N_96_i
|
|
0 1
|
|
.names N_246.BLIF as_030_000_sync_0_un3_n
|
|
0 1
|
|
.names inst_CLK_000_PE.BLIF CLK_000_PE_i
|
|
0 1
|
|
.names N_95.BLIF N_95_i
|
|
0 1
|
|
.names inst_AS_030_000_SYNC.BLIF N_246.BLIF as_030_000_sync_0_un1_n
|
|
11 1
|
|
.names BERR_c.BLIF BERR_i
|
|
0 1
|
|
.names N_94.BLIF N_94_i
|
|
0 1
|
|
.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \
|
|
as_030_000_sync_0_un0_n
|
|
11 1
|
|
.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
|
|
0 1
|
|
.names N_313.BLIF N_313_i
|
|
0 1
|
|
.names pos_clk_un3_ds_030_d0_n.BLIF lds_000_int_0_un3_n
|
|
0 1
|
|
.names cpu_est_2_.BLIF cpu_est_i_2__n
|
|
0 1
|
|
.names N_313_i.BLIF SM_AMIGA_3_.BLIF N_136_i
|
|
11 1
|
|
.names pos_clk_un11_ds_030_d0_i_n.BLIF pos_clk_un3_ds_030_d0_n.BLIF \
|
|
lds_000_int_0_un1_n
|
|
11 1
|
|
.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
|
|
0 1
|
|
.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_81_0
|
|
11 1
|
|
.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n
|
|
11 1
|
|
.names inst_DTACK_D0.BLIF DTACK_D0_i
|
|
0 1
|
|
.names N_116.BLIF N_116_i
|
|
0 1
|
|
.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n
|
|
0 1
|
|
.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
|
|
0 1
|
|
.names N_116_i.BLIF RST_c.BLIF N_77_i
|
|
11 1
|
|
.names N_265.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n
|
|
11 1
|
|
.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n
|
|
11 1
|
|
.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
|
|
0 1
|
|
.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_73_i
|
|
11 1
|
|
.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n
|
|
11 1
|
|
.names inst_CLK_000_NE.BLIF CLK_000_NE_i
|
|
0 1
|
|
.names N_101.BLIF N_101_i
|
|
0 1
|
|
.names pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un3_n
|
|
0 1
|
|
.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
|
|
0 1
|
|
.names A0_c.BLIF pos_clk_un3_ds_030_d0_n.BLIF uds_000_int_0_un1_n
|
|
11 1
|
|
.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
|
|
0 1
|
|
.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n
|
|
0 1
|
|
.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
|
|
11 1
|
|
.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i
|
|
0 1
|
|
.names pos_clk_un9_clk_000_n_sync_n.BLIF pos_clk_un9_clk_000_n_sync_i_n
|
|
0 1
|
|
.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n
|
|
0 1
|
|
.names pos_clk_ipl_1_n.BLIF N_225_i.BLIF pos_clk_ipl_n
|
|
11 1
|
|
.names pos_clk_un11_clk_000_n_sync_n.BLIF pos_clk_un11_clk_000_n_sync_i_n
|
|
0 1
|
|
.names clk_000_n_sync_i_10__n.BLIF pos_clk_un9_clk_000_n_sync_i_n.BLIF \
|
|
pos_clk_un14_clk_000_n_sync_0_n
|
|
11 1
|
|
.names N_103_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \
|
|
amiga_bus_enable_dma_low_0_un1_n
|
|
11 1
|
|
.names DS_030_D0_i.BLIF SM_AMIGA_6_.BLIF pos_clk_un3_ds_030_d0_n
|
|
11 1
|
|
.names LDS_000_c.BLIF LDS_000_i
|
|
0 1
|
|
.names LDS_000_c.BLIF UDS_000_c.BLIF pos_clk_un22_bgack_030_int_i_n
|
|
11 1
|
|
.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \
|
|
amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n
|
|
11 1
|
|
.names UDS_000_c.BLIF UDS_000_i
|
|
0 1
|
|
.names N_86.BLIF N_86_i
|
|
0 1
|
|
.names BGACK_030_INT_i.BLIF RST_c.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa
|
|
11 1
|
|
.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i
|
|
0 1
|
|
.names N_93.BLIF N_93_i
|
|
0 1
|
|
.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
|
|
0 1
|
|
.names AS_030_c.BLIF AS_030_i
|
|
0 1
|
|
.names N_99.BLIF N_99_i
|
|
0 1
|
|
.names A1_c.BLIF A1_i
|
|
0 1
|
|
.names N_99_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n
|
|
11 1
|
|
.names inst_CLK_000_D1.BLIF CLK_000_D1_i
|
|
0 1
|
|
.names N_100.BLIF N_100_i
|
|
0 1
|
|
.names RW_000_c.BLIF RW_000_i
|
|
0 1
|
|
.names N_100_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n
|
|
11 1
|
|
.names inst_CLK_030_H.BLIF CLK_030_H_i
|
|
0 1
|
|
.names N_92_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_245_0
|
|
11 1
|
|
.names inst_AS_000_DMA.BLIF AS_000_DMA_i
|
|
0 1
|
|
.names N_108.BLIF N_108_i
|
|
0 1
|
|
.names AS_000_c.BLIF AS_000_i
|
|
0 1
|
|
.names N_109.BLIF N_109_i
|
|
0 1
|
|
.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n
|
|
0 1
|
|
.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n
|
|
0 1
|
|
.names N_108_i.BLIF N_109_i.BLIF N_246_0
|
|
11 1
|
|
.names RW_c.BLIF RW_i
|
|
0 1
|
|
.names un5_ciin.BLIF un5_ciin_i
|
|
0 1
|
|
.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i
|
|
0 1
|
|
.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_247_0
|
|
11 1
|
|
.names FPU_SENSE_c.BLIF FPU_SENSE_i
|
|
0 1
|
|
.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_248_0
|
|
11 1
|
|
.names inst_AS_030_D0.BLIF AS_030_D0_i
|
|
0 1
|
|
.names inst_CLK_000_D0.BLIF CLK_000_D0_i
|
|
0 1
|
|
.names a_c_24__n.BLIF a_i_24__n
|
|
0 1
|
|
.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_249_i
|
|
11 1
|
|
.names SIZE_DMA_0_.BLIF size_dma_i_0__n
|
|
0 1
|
|
.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
|
|
0 1
|
|
.names SIZE_DMA_1_.BLIF size_dma_i_1__n
|
|
0 1
|
|
.names N_251_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_251_0
|
|
11 1
|
|
.names a_c_16__n.BLIF a_i_16__n
|
|
0 1
|
|
.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n
|
|
11 1
|
|
.names a_c_18__n.BLIF a_i_18__n
|
|
0 1
|
|
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
|
pos_clk_un5_bgack_030_int_d_i_n
|
|
11 1
|
|
.names a_c_19__n.BLIF a_i_19__n
|
|
0 1
|
|
.names N_75_i_1.BLIF sm_amiga_i_4__n.BLIF N_75_i
|
|
11 1
|
|
.names a_c_31__n.BLIF a_i_31__n
|
|
0 1
|
|
.names LDS_000_i.BLIF UDS_000_i.BLIF N_76_i
|
|
11 1
|
|
.names a_c_29__n.BLIF a_i_29__n
|
|
0 1
|
|
.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_78_0
|
|
11 1
|
|
.names a_c_30__n.BLIF a_i_30__n
|
|
0 1
|
|
.names N_80_0_1.BLIF sm_amiga_i_i_7__n.BLIF N_80_0
|
|
11 1
|
|
.names a_c_27__n.BLIF a_i_27__n
|
|
0 1
|
|
.names CLK_EXP_c.BLIF CLK_EXP_c_i
|
|
0 1
|
|
.names a_c_28__n.BLIF a_i_28__n
|
|
0 1
|
|
.names CLK_EXP_c_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_258_0
|
|
11 1
|
|
.names a_c_25__n.BLIF a_i_25__n
|
|
0 1
|
|
.names N_283.BLIF N_283_i
|
|
0 1
|
|
.names a_c_26__n.BLIF a_i_26__n
|
|
0 1
|
|
.names N_284.BLIF N_284_i
|
|
0 1
|
|
.names inst_UDS_000_INT.BLIF UDS_000_INT_i
|
|
0 1
|
|
.names inst_LDS_000_INT.BLIF LDS_000_INT_i
|
|
0 1
|
|
.names N_290.BLIF N_290_i
|
|
0 1
|
|
.names DS_030_c.BLIF DS_030_i
|
|
0 1
|
|
.names N_291.BLIF N_291_i
|
|
0 1
|
|
.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n
|
|
0 1
|
|
.names G_165.BLIF N_224_i
|
|
0 1
|
|
.names G_166.BLIF N_225_i
|
|
0 1
|
|
.names N_279.BLIF N_279_i
|
|
0 1
|
|
.names G_167.BLIF N_226_i
|
|
0 1
|
|
.names N_293.BLIF N_293_i
|
|
0 1
|
|
.names N_82.BLIF N_82_i
|
|
0 1
|
|
.names N_83.BLIF N_83_i
|
|
0 1
|
|
.names N_104.BLIF N_104_i
|
|
0 1
|
|
.names N_82_i.BLIF N_83_i.BLIF N_259_0
|
|
11 1
|
|
.names N_103.BLIF N_103_i
|
|
0 1
|
|
.names N_84.BLIF N_84_i
|
|
0 1
|
|
.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n
|
|
0 1
|
|
.names N_282.BLIF N_282_i
|
|
0 1
|
|
.names N_115_0_1.BLIF SM_AMIGA_i_7_.BLIF N_115_0
|
|
11 1
|
|
.names N_92.BLIF N_92_i
|
|
0 1
|
|
.names N_85.BLIF N_85_i
|
|
0 1
|
|
.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF AS_000_INT_1_sqmuxa
|
|
11 1
|
|
.names un6_lds_000.BLIF un6_lds_000_i
|
|
0 1
|
|
.names N_294.BLIF N_294_i
|
|
0 1
|
|
.names N_282.BLIF pos_clk_un3_as_030_d0_i_n.BLIF DS_000_ENABLE_1_sqmuxa_1
|
|
11 1
|
|
.names un6_uds_000.BLIF un6_uds_000_i
|
|
0 1
|
|
.names N_296.BLIF N_296_i
|
|
0 1
|
|
.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n
|
|
11 1
|
|
.names un6_ds_030.BLIF un6_ds_030_i
|
|
0 1
|
|
.names pos_clk_cpu_est_11_0_1_3__n.BLIF N_294_i.BLIF pos_clk_cpu_est_11_0_3__n
|
|
11 1
|
|
.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n
|
|
0 1
|
|
.names inst_DS_000_DMA.BLIF DS_000_DMA_i
|
|
0 1
|
|
.names N_91.BLIF N_91_i
|
|
0 1
|
|
.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3
|
|
1- 1
|
|
-1 1
|
|
.names un4_as_000.BLIF un4_as_000_i
|
|
0 1
|
|
.names N_260_0_1.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF N_260_0
|
|
11 1
|
|
.names inst_AS_000_INT.BLIF AS_000_INT_i
|
|
0 1
|
|
.names N_301.BLIF N_301_i
|
|
0 1
|
|
.names un6_as_030.BLIF un6_as_030_i
|
|
0 1
|
|
.names N_301_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_n.BLIF \
|
|
pos_clk_ds_000_dma_4_0_n
|
|
11 1
|
|
.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_6
|
|
1- 1
|
|
-1 1
|
|
.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i
|
|
0 1
|
|
.names N_305.BLIF N_305_i
|
|
0 1
|
|
.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_8
|
|
1- 1
|
|
-1 1
|
|
.names inst_DS_030_D0.BLIF DS_030_D0_i
|
|
0 1
|
|
.names N_306.BLIF N_306_i
|
|
0 1
|
|
.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_9
|
|
1- 1
|
|
-1 1
|
|
.names N_305_i.BLIF N_306_i.BLIF AMIGA_BUS_DATA_DIR_c_0
|
|
11 1
|
|
.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_10
|
|
1- 1
|
|
-1 1
|
|
.names N_307.BLIF N_307_i
|
|
0 1
|
|
.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_11
|
|
1- 1
|
|
-1 1
|
|
.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_12
|
|
1- 1
|
|
-1 1
|
|
.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_13
|
|
1- 1
|
|
-1 1
|
|
.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_15
|
|
1- 1
|
|
-1 1
|
|
.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_265_0
|
|
11 1
|
|
.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_16
|
|
1- 1
|
|
-1 1
|
|
.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_269_i
|
|
11 1
|
|
.names amiga_bus_enable_dma_low_0_un1_n.BLIF \
|
|
amiga_bus_enable_dma_low_0_un0_n.BLIF N_19
|
|
1- 1
|
|
-1 1
|
|
.names pos_clk_un24_bgack_030_int_i_0_i_1_n.BLIF \
|
|
pos_clk_un22_bgack_030_int_n.BLIF pos_clk_un24_bgack_030_int_i_0_i_n
|
|
11 1
|
|
.names amiga_bus_enable_dma_high_0_un1_n.BLIF \
|
|
amiga_bus_enable_dma_high_0_un0_n.BLIF N_20
|
|
1- 1
|
|
-1 1
|
|
.names N_268_i.BLIF SM_AMIGA_6_.BLIF N_62_0
|
|
11 1
|
|
.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_21
|
|
1- 1
|
|
-1 1
|
|
.names inst_CLK_000_PE.BLIF SM_AMIGA_6_.BLIF N_276_0
|
|
11 1
|
|
.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_23
|
|
1- 1
|
|
-1 1
|
|
.names AS_000_DMA_i.BLIF CLK_EXP_c_i.BLIF N_277_0
|
|
11 1
|
|
.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_24
|
|
1- 1
|
|
-1 1
|
|
.names N_286.BLIF N_286_i
|
|
0 1
|
|
.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_25
|
|
1- 1
|
|
-1 1
|
|
.names N_288.BLIF N_288_i
|
|
0 1
|
|
.names N_289.BLIF N_289_i
|
|
0 1
|
|
.names pos_clk_un11_ds_030_d0_i_1_n.BLIF size_c_0__n.BLIF \
|
|
pos_clk_un11_ds_030_d0_i_n
|
|
11 1
|
|
.names A0_c.BLIF A0_c_i
|
|
0 1
|
|
.names size_c_1__n.BLIF size_c_i_1__n
|
|
0 1
|
|
.names N_25.BLIF N_25_i
|
|
0 1
|
|
.names N_25_i.BLIF RST_c.BLIF N_32_0
|
|
11 1
|
|
.names N_24.BLIF N_24_i
|
|
0 1
|
|
.names N_24_i.BLIF RST_c.BLIF N_31_0
|
|
11 1
|
|
.names N_23.BLIF N_23_i
|
|
0 1
|
|
.names N_23_i.BLIF RST_c.BLIF N_30_0
|
|
11 1
|
|
.names ipl_c_2__n.BLIF ipl_c_i_2__n
|
|
0 1
|
|
.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0
|
|
11 1
|
|
.names ipl_c_1__n.BLIF ipl_c_i_1__n
|
|
0 1
|
|
.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0
|
|
11 1
|
|
.names ipl_c_0__n.BLIF ipl_c_i_0__n
|
|
0 1
|
|
.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0
|
|
11 1
|
|
.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i
|
|
0 1
|
|
.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0
|
|
11 1
|
|
.names DS_030_i.BLIF RST_c.BLIF N_50_0
|
|
11 1
|
|
.names N_3.BLIF N_3_i
|
|
0 1
|
|
.names N_3_i.BLIF RST_c.BLIF N_49_0
|
|
11 1
|
|
.names N_6.BLIF N_6_i
|
|
0 1
|
|
.names N_6_i.BLIF RST_c.BLIF N_48_0
|
|
11 1
|
|
.names N_8.BLIF N_8_i
|
|
0 1
|
|
.names N_8_i.BLIF RST_c.BLIF N_46_0
|
|
11 1
|
|
.names N_9.BLIF N_9_i
|
|
0 1
|
|
.names N_9_i.BLIF RST_c.BLIF N_45_0
|
|
11 1
|
|
.names N_12.BLIF N_12_i
|
|
0 1
|
|
.names N_12_i.BLIF RST_c.BLIF N_43_0
|
|
11 1
|
|
.names N_115_0.BLIF N_115
|
|
0 1
|
|
.names N_13.BLIF N_13_i
|
|
0 1
|
|
.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n
|
|
0 1
|
|
.names N_13_i.BLIF RST_c.BLIF N_42_0
|
|
11 1
|
|
.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n
|
|
0 1
|
|
.names N_15.BLIF N_15_i
|
|
0 1
|
|
.names pos_clk_cpu_est_11_0_3__n.BLIF pos_clk_cpu_est_11_3__n
|
|
0 1
|
|
.names N_15_i.BLIF RST_c.BLIF N_40_0
|
|
11 1
|
|
.names N_16.BLIF N_16_i
|
|
0 1
|
|
.names N_16_i.BLIF RST_c.BLIF N_39_0
|
|
11 1
|
|
.names N_19.BLIF N_19_i
|
|
0 1
|
|
.names inst_DS_000_ENABLE.BLIF DS_030_i.BLIF un6_uds_000_1
|
|
11 1
|
|
.names N_19_i.BLIF RST_c.BLIF N_36_0
|
|
11 1
|
|
.names pos_clk_un24_bgack_030_int_i_0_i_n.BLIF \
|
|
pos_clk_un24_bgack_030_int_i_0_n
|
|
0 1
|
|
.names N_20.BLIF N_20_i
|
|
0 1
|
|
.names N_245_0.BLIF N_245
|
|
0 1
|
|
.names N_20_i.BLIF RST_c.BLIF N_35_0
|
|
11 1
|
|
.names N_246_0.BLIF N_246
|
|
0 1
|
|
.names N_21.BLIF N_21_i
|
|
0 1
|
|
.names N_247_0.BLIF N_247
|
|
0 1
|
|
.names N_21_i.BLIF RST_c.BLIF N_34_0
|
|
11 1
|
|
.names N_248_0.BLIF N_248
|
|
0 1
|
|
.names BG_030_c.BLIF BG_030_c_i
|
|
0 1
|
|
.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF N_89
|
|
11 1
|
|
.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n
|
|
0 1
|
|
.names SM_AMIGA_1_.BLIF pos_clk_un14_clk_000_n_sync_n.BLIF N_92
|
|
11 1
|
|
.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n
|
|
11 1
|
|
.names AS_030_i.BLIF RST_c.BLIF N_102
|
|
11 1
|
|
.names N_286_i.BLIF RST_c.BLIF N_127_i_1
|
|
11 1
|
|
.names A1_c.BLIF BGACK_030_INT_i.BLIF N_103
|
|
11 1
|
|
.names N_288_i.BLIF N_289_i.BLIF N_127_i_2
|
|
11 1
|
|
.names A1_i.BLIF BGACK_030_INT_i.BLIF N_104
|
|
11 1
|
|
.names pos_clk_un24_bgack_030_int_i_0_x2.BLIF N_269_i.BLIF \
|
|
pos_clk_un24_bgack_030_int_i_0_i_1_n
|
|
11 1
|
|
.names N_256.BLIF nEXP_SPACE_D0_i.BLIF N_112
|
|
11 1
|
|
.names inst_nEXP_SPACE_D0reg.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF \
|
|
N_80_0_1
|
|
11 1
|
|
.names BGACK_030_INT_i.BLIF inst_RESET_OUTreg.BLIF N_256
|
|
11 1
|
|
.names sm_amiga_i_2__n.BLIF sm_amiga_i_6__n.BLIF N_75_i_1
|
|
11 1
|
|
.names N_258_0.BLIF N_258
|
|
0 1
|
|
.names N_249_i.BLIF AS_030_000_SYNC_i.BLIF N_251_0_1
|
|
11 1
|
|
.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un11_ds_030_d0_i_1_n
|
|
11 1
|
|
.names N_260_0.BLIF N_260
|
|
0 1
|
|
.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_340_1
|
|
11 1
|
|
.names N_265_0.BLIF N_265
|
|
0 1
|
|
.names a_c_17__n.BLIF a_i_16__n.BLIF N_340_2
|
|
11 1
|
|
.names un1_sm_amiga_7_i_m2_un1_n.BLIF un1_sm_amiga_7_i_m2_un0_n.BLIF N_282
|
|
1- 1
|
|
-1 1
|
|
.names a_i_18__n.BLIF a_i_19__n.BLIF N_340_3
|
|
11 1
|
|
.names un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF \
|
|
un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF N_71
|
|
1- 1
|
|
-1 1
|
|
.names N_340_1.BLIF N_340_2.BLIF N_340_4
|
|
11 1
|
|
.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1
|
|
11 1
|
|
.names CLK_EXP_c.BLIF CLK_OUT_PRE_D_i.BLIF pos_clk_un11_clk_000_n_sync_n
|
|
11 1
|
|
.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2
|
|
11 1
|
|
.names N_76_i.BLIF N_76
|
|
0 1
|
|
.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3
|
|
11 1
|
|
.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4
|
|
11 1
|
|
.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5
|
|
11 1
|
|
.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6
|
|
11 1
|
|
.names pos_clk_un22_bgack_030_int_i_n.BLIF pos_clk_un22_bgack_030_int_n
|
|
0 1
|
|
.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7
|
|
11 1
|
|
.names N_268_i.BLIF N_268
|
|
0 1
|
|
.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8
|
|
11 1
|
|
.names N_270_i.BLIF N_270
|
|
0 1
|
|
.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9
|
|
11 1
|
|
.names N_73_i.BLIF N_73
|
|
0 1
|
|
.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10
|
|
11 1
|
|
.names N_75_i.BLIF N_75
|
|
0 1
|
|
.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11
|
|
11 1
|
|
.names N_251_0.BLIF N_251
|
|
0 1
|
|
.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0
|
|
11 1
|
|
.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1
|
|
11 1
|
|
.names FPU_SENSE_i.BLIF N_340.BLIF un21_fpu_cs_1
|
|
11 1
|
|
.names N_95_1.BLIF CLK_000_NE_i.BLIF N_95
|
|
11 1
|
|
.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n
|
|
11 1
|
|
.names N_94_1.BLIF CLK_000_PE_i.BLIF N_94
|
|
11 1
|
|
.names N_97_i.BLIF N_77_i.BLIF N_131_i_1
|
|
11 1
|
|
.names BERR_i.BLIF SM_AMIGA_5_.BLIF N_288
|
|
11 1
|
|
.names N_94_i.BLIF N_95_i.BLIF N_131_i_2
|
|
11 1
|
|
.names inst_CLK_000_NE.BLIF sm_amiga_i_6__n.BLIF N_289
|
|
11 1
|
|
.names N_131_i_1.BLIF N_131_i_2.BLIF N_131_i_3
|
|
11 1
|
|
.names N_276.BLIF sm_amiga_i_5__n.BLIF N_286
|
|
11 1
|
|
.names N_73_i.BLIF N_75_i.BLIF N_96_1
|
|
11 1
|
|
.names sm_amiga_srsts_i_0_m2_3__un1_n.BLIF sm_amiga_srsts_i_0_m2_3__un0_n.BLIF \
|
|
N_279
|
|
1- 1
|
|
-1 1
|
|
.names N_251.BLIF sm_amiga_i_0__n.BLIF N_96_2
|
|
11 1
|
|
.names N_277_0.BLIF N_277
|
|
0 1
|
|
.names N_96_1.BLIF N_96_2.BLIF N_96_3
|
|
11 1
|
|
.names N_276_0.BLIF N_276
|
|
0 1
|
|
.names N_88_i.BLIF N_90_i.BLIF pos_clk_cpu_est_11_0_1_1__n
|
|
11 1
|
|
.names N_62_0.BLIF N_62
|
|
0 1
|
|
.names N_299_i.BLIF N_312_i.BLIF pos_clk_cpu_est_11_0_2_1__n
|
|
11 1
|
|
.names N_274_0.BLIF N_274
|
|
0 1
|
|
.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_310_1
|
|
11 1
|
|
.names inst_CLK_000_NE_D0.BLIF N_267.BLIF N_313
|
|
11 1
|
|
.names VMA_INT_i.BLIF VPA_D_i.BLIF N_310_2
|
|
11 1
|
|
.names CLK_030_H_i.BLIF N_277.BLIF N_307
|
|
11 1
|
|
.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_310_3
|
|
11 1
|
|
.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_305
|
|
11 1
|
|
.names N_310_1.BLIF N_310_2.BLIF N_310_4
|
|
11 1
|
|
.names N_306_1.BLIF nEXP_SPACE_D0_i.BLIF N_306
|
|
11 1
|
|
.names inst_CLK_000_NE.BLIF N_312.BLIF N_309_1
|
|
11 1
|
|
.names N_303_1.BLIF cpu_est_i_3__n.BLIF N_303
|
|
11 1
|
|
.names VPA_D_i.BLIF cpu_est_2_.BLIF N_309_2
|
|
11 1
|
|
.names N_304_1.BLIF cpu_est_i_2__n.BLIF N_304
|
|
11 1
|
|
.names inst_CLK_000_PE.BLIF N_270_i.BLIF N_308_1
|
|
11 1
|
|
.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_301
|
|
11 1
|
|
.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_308_2
|
|
11 1
|
|
.names inst_CLK_030_H.BLIF CLK_EXP_c.BLIF N_91
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF RESET_OUT_0_sqmuxa_5_1
|
|
11 1
|
|
.names N_273.BLIF cpu_est_3_reg.BLIF N_85
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF RESET_OUT_0_sqmuxa_7_1
|
|
11 1
|
|
.names N_273_i.BLIF cpu_est_i_2__n.BLIF N_294
|
|
11 1
|
|
.names RST_DLY_4_.BLIF RST_DLY_5_.BLIF RESET_OUT_0_sqmuxa_7_2
|
|
11 1
|
|
.names N_296_1.BLIF cpu_est_i_2__n.BLIF N_296
|
|
11 1
|
|
.names RESET_OUT_0_sqmuxa_7_1.BLIF RESET_OUT_0_sqmuxa_7_2.BLIF \
|
|
RESET_OUT_0_sqmuxa_7_3
|
|
11 1
|
|
.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_84
|
|
11 1
|
|
.names N_75.BLIF BERR_i.BLIF N_94_1
|
|
11 1
|
|
.names N_82_1.BLIF SM_AMIGA_2_.BLIF N_82
|
|
11 1
|
|
.names N_73.BLIF BERR_i.BLIF N_95_1
|
|
11 1
|
|
.names N_83_1.BLIF SM_AMIGA_3_.BLIF N_83
|
|
11 1
|
|
.names N_86_i.BLIF N_93_i.BLIF N_119_i_1
|
|
11 1
|
|
.names N_136.BLIF sm_amiga_i_4__n.BLIF N_293
|
|
11 1
|
|
.names N_274.BLIF RST_c.BLIF N_82_1
|
|
11 1
|
|
.names N_275.BLIF sm_amiga_i_5__n.BLIF N_290
|
|
11 1
|
|
.names N_313.BLIF RST_c.BLIF N_83_1
|
|
11 1
|
|
.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_291
|
|
11 1
|
|
.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_296_1
|
|
11 1
|
|
.names N_62.BLIF SM_AMIGA_i_7_.BLIF N_283
|
|
11 1
|
|
.names N_270.BLIF cpu_est_0_.BLIF N_303_1
|
|
11 1
|
|
.names N_251.BLIF sm_amiga_i_6__n.BLIF N_284
|
|
11 1
|
|
.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_304_1
|
|
11 1
|
|
.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \
|
|
N_86
|
|
1- 1
|
|
-1 1
|
|
.names N_269_i.BLIF RW_000_c.BLIF N_306_1
|
|
11 1
|
|
.names N_80_0.BLIF N_80
|
|
0 1
|
|
.names N_283_i.BLIF N_284_i.BLIF N_129_i_1
|
|
11 1
|
|
.names N_78_0.BLIF N_78
|
|
0 1
|
|
.names N_290_i.BLIF N_291_i.BLIF N_125_i_1
|
|
11 1
|
|
.names N_80.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_108
|
|
11 1
|
|
.names N_279_i.BLIF N_293_i.BLIF N_123_i_1
|
|
11 1
|
|
.names N_340.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_109
|
|
11 1
|
|
.names N_84_i.BLIF sm_amiga_i_5__n.BLIF N_115_0_1
|
|
11 1
|
|
.names BGACK_030_INT_i.BLIF N_76.BLIF N_100
|
|
11 1
|
|
.names N_296_i.BLIF N_85_i.BLIF pos_clk_cpu_est_11_0_1_3__n
|
|
11 1
|
|
.names BGACK_030_INT_i.BLIF N_76_i.BLIF N_99
|
|
11 1
|
|
.names N_91_i.BLIF RW_000_i.BLIF N_260_0_1
|
|
11 1
|
|
.names N_78.BLIF sm_amiga_i_2__n.BLIF N_93
|
|
11 1
|
|
.names N_307_i.BLIF RST_c.BLIF N_261_i_1
|
|
11 1
|
|
.names pos_clk_un14_clk_000_n_sync_0_n.BLIF pos_clk_un14_clk_000_n_sync_n
|
|
0 1
|
|
.names pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_269_i.BLIF N_262_i_1
|
|
11 1
|
|
.names CLK_000_N_SYNC_9_.BLIF pos_clk_un11_clk_000_n_sync_i_n.BLIF \
|
|
pos_clk_un9_clk_000_n_sync_n
|
|
11 1
|
|
.names pos_clk_CYCLE_DMA_5_0_i_x2.BLIF N_269_i.BLIF N_263_i_1
|
|
11 1
|
|
.names N_340_4.BLIF N_340_3.BLIF N_340
|
|
11 1
|
|
.names N_226_i.BLIF N_224_i.BLIF pos_clk_ipl_1_n
|
|
11 1
|
|
.names BERR_i.BLIF N_136_i.BLIF N_97
|
|
11 1
|
|
.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n
|
|
0 1
|
|
.names N_136_i.BLIF N_136
|
|
0 1
|
|
.names pos_clk_cpu_est_11_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n
|
|
11 1
|
|
.names N_81.BLIF sm_amiga_i_0__n.BLIF N_101
|
|
11 1
|
|
.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n
|
|
11 1
|
|
.names N_81_0.BLIF N_81
|
|
0 1
|
|
.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n
|
|
0 1
|
|
.names N_268.BLIF SM_AMIGA_0_.BLIF N_116
|
|
11 1
|
|
.names N_186_i.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n
|
|
11 1
|
|
.names N_96_3.BLIF sm_amiga_i_3__n.BLIF N_96
|
|
11 1
|
|
.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n
|
|
11 1
|
|
.names BGACK_000_c.BLIF CLK_000_PE_i.BLIF N_113
|
|
11 1
|
|
.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n
|
|
0 1
|
|
.names N_275_0.BLIF N_275
|
|
0 1
|
|
.names pos_clk_cpu_est_11_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n
|
|
11 1
|
|
.names N_273_i.BLIF N_273
|
|
0 1
|
|
.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n
|
|
11 1
|
|
.names N_272.BLIF cpu_est_i_0__n.BLIF N_88
|
|
11 1
|
|
.names N_113.BLIF bgack_030_int_0_un3_n
|
|
0 1
|
|
.names N_272_i.BLIF N_272
|
|
0 1
|
|
.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
|
|
0 1
|
|
.names inst_BGACK_030_INTreg.BLIF N_113.BLIF bgack_030_int_0_un1_n
|
|
11 1
|
|
.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_299
|
|
11 1
|
|
.names BGACK_000_c.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n
|
|
11 1
|
|
.names N_270_i.BLIF cpu_est_3_reg.BLIF N_90
|
|
11 1
|
|
.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n
|
|
0 1
|
|
.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_311
|
|
11 1
|
|
.names cpu_est_1_.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n
|
|
11 1
|
|
.names N_272_i.BLIF cpu_est_0_.BLIF N_312
|
|
11 1
|
|
.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
|
|
11 1
|
|
.names N_267_0.BLIF N_267
|
|
0 1
|
|
.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUTreg.BLIF un1_as_000_i
|
|
11 1
|
|
.names N_115.BLIF rw_000_int_0_un3_n
|
|
0 1
|
|
.names N_264_0.BLIF N_264
|
|
0 1
|
|
.names un1_rst_dly_i_m_3__n.BLIF un1_rst_dly_i_m_i_3__n
|
|
0 1
|
|
.names N_264.BLIF N_115.BLIF rw_000_int_0_un1_n
|
|
11 1
|
|
.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n
|
|
0 1
|
|
.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n
|
|
11 1
|
|
.names N_308_1.BLIF N_308_2.BLIF N_308
|
|
11 1
|
|
.names un1_rst_dly_i_m_4__n.BLIF un1_rst_dly_i_m_i_4__n
|
|
0 1
|
|
.names SM_AMIGA_3_.BLIF sm_amiga_srsts_i_0_m2_3__un3_n
|
|
0 1
|
|
.names N_309_1.BLIF N_309_2.BLIF N_309
|
|
11 1
|
|
.names BERR_i.BLIF SM_AMIGA_3_.BLIF sm_amiga_srsts_i_0_m2_3__un1_n
|
|
11 1
|
|
.names inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF pos_clk_RST_DLY_5_iv_0_x2_0_
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names RESET_OUT_0_sqmuxa_1.BLIF RST_DLY_1_.BLIF G_137
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names RESET_OUT_0_sqmuxa_7.BLIF RST_DLY_7_.BLIF G_149
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names N_213.BLIF RST_DLY_6_.BLIF G_147
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names N_211.BLIF RST_DLY_5_.BLIF G_145
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names N_209.BLIF RST_DLY_4_.BLIF G_143
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names RESET_OUT_0_sqmuxa_5.BLIF RST_DLY_3_.BLIF G_141
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names N_205.BLIF RST_DLY_2_.BLIF G_139
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_165
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_166
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_167
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names N_220.BLIF CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_x2
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un24_bgack_030_int_i_0_x2
|
|
01 1
|
|
10 1
|
|
11 0
|
|
00 0
|
|
.names IPL_030DFF_2_reg.BLIF IPL_030_2_
|
|
1 1
|
|
0 0
|
|
.names BG_000DFFreg.BLIF BG_000
|
|
1 1
|
|
0 0
|
|
.names inst_BGACK_030_INTreg.BLIF BGACK_030
|
|
1 1
|
|
0 0
|
|
.names gnd_n_n.BLIF CLK_DIV_OUT
|
|
1 1
|
|
0 0
|
|
.names CLK_EXP_c.BLIF CLK_EXP
|
|
1 1
|
|
0 0
|
|
.names un21_fpu_cs_i.BLIF FPU_CS
|
|
1 1
|
|
0 0
|
|
.names inst_DSACK1_INTreg.BLIF DSACK1
|
|
1 1
|
|
0 0
|
|
.names vcc_n_n.BLIF AVEC
|
|
1 1
|
|
0 0
|
|
.names cpu_est_3_reg.BLIF E
|
|
1 1
|
|
0 0
|
|
.names inst_VMA_INTreg.BLIF VMA
|
|
1 1
|
|
0 0
|
|
.names inst_RESET_OUTreg.BLIF RESET
|
|
1 1
|
|
0 0
|
|
.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE
|
|
1 1
|
|
0 0
|
|
.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
|
|
1 1
|
|
0 0
|
|
.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW
|
|
1 1
|
|
0 0
|
|
.names N_71_i.BLIF AMIGA_BUS_ENABLE_HIGH
|
|
1 1
|
|
0 0
|
|
.names un5_ciin.BLIF CIIN
|
|
1 1
|
|
0 0
|
|
.names IPL_030DFF_1_reg.BLIF IPL_030_1_
|
|
1 1
|
|
0 0
|
|
.names IPL_030DFF_0_reg.BLIF IPL_030_0_
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF IPL_D0_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF IPL_D0_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF IPL_D0_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
|
|
1 1
|
|
0 0
|
|
.names cpu_est_0_0_x2_0_.BLIF cpu_est_0_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF cpu_est_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF cpu_est_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF cpu_est_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF cpu_est_3_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF RST_DLY_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF RST_DLY_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF RST_DLY_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF RST_DLY_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF RST_DLY_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF RST_DLY_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF RST_DLY_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF RST_DLY_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C
|
|
1 1
|
|
0 0
|
|
.names N_249_i.BLIF CLK_000_N_SYNC_0_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_RESET_OUTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_RW_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_A0_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_DS_030_D0.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_AS_030_D0.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_VPA_D.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_DTACK_D0.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF BG_000DFFreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000.BLIF inst_CLK_000_D0.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
|
|
1 1
|
|
0 0
|
|
.names un3_size.BLIF SIZE_1_
|
|
1 1
|
|
0 0
|
|
.names un6_as_030_i.BLIF AS_030
|
|
1 1
|
|
0 0
|
|
.names un4_as_000_i.BLIF AS_000
|
|
1 1
|
|
0 0
|
|
.names inst_RW_000_INT.BLIF RW_000
|
|
1 1
|
|
0 0
|
|
.names un6_ds_030_i.BLIF DS_030
|
|
1 1
|
|
0 0
|
|
.names un6_uds_000_i.BLIF UDS_000
|
|
1 1
|
|
0 0
|
|
.names un6_lds_000_i.BLIF LDS_000
|
|
1 1
|
|
0 0
|
|
.names inst_A0_DMA.BLIF A0
|
|
1 1
|
|
0 0
|
|
.names gnd_n_n.BLIF BERR
|
|
1 1
|
|
0 0
|
|
.names inst_RW_000_DMA.BLIF RW
|
|
1 1
|
|
0 0
|
|
.names un4_size.BLIF SIZE_0_
|
|
1 1
|
|
0 0
|
|
.names A_15_.BLIF a_15__n
|
|
1 1
|
|
0 0
|
|
.names A_14_.BLIF a_14__n
|
|
1 1
|
|
0 0
|
|
.names A_13_.BLIF a_13__n
|
|
1 1
|
|
0 0
|
|
.names A_12_.BLIF a_12__n
|
|
1 1
|
|
0 0
|
|
.names A_11_.BLIF a_11__n
|
|
1 1
|
|
0 0
|
|
.names A_10_.BLIF a_10__n
|
|
1 1
|
|
0 0
|
|
.names A_9_.BLIF a_9__n
|
|
1 1
|
|
0 0
|
|
.names A_8_.BLIF a_8__n
|
|
1 1
|
|
0 0
|
|
.names A_7_.BLIF a_7__n
|
|
1 1
|
|
0 0
|
|
.names A_6_.BLIF a_6__n
|
|
1 1
|
|
0 0
|
|
.names A_5_.BLIF a_5__n
|
|
1 1
|
|
0 0
|
|
.names A_4_.BLIF a_4__n
|
|
1 1
|
|
0 0
|
|
.names A_3_.BLIF a_3__n
|
|
1 1
|
|
0 0
|
|
.names A_2_.BLIF a_2__n
|
|
1 1
|
|
0 0
|
|
.names AS_030.PIN.BLIF AS_030_c
|
|
1 1
|
|
0 0
|
|
.names AS_000.PIN.BLIF AS_000_c
|
|
1 1
|
|
0 0
|
|
.names RW_000.PIN.BLIF RW_000_c
|
|
1 1
|
|
0 0
|
|
.names DS_030.PIN.BLIF DS_030_c
|
|
1 1
|
|
0 0
|
|
.names UDS_000.PIN.BLIF UDS_000_c
|
|
1 1
|
|
0 0
|
|
.names LDS_000.PIN.BLIF LDS_000_c
|
|
1 1
|
|
0 0
|
|
.names SIZE_0_.PIN.BLIF size_c_0__n
|
|
1 1
|
|
0 0
|
|
.names SIZE_1_.PIN.BLIF size_c_1__n
|
|
1 1
|
|
0 0
|
|
.names A_16_.BLIF a_c_16__n
|
|
1 1
|
|
0 0
|
|
.names A_17_.BLIF a_c_17__n
|
|
1 1
|
|
0 0
|
|
.names A_18_.BLIF a_c_18__n
|
|
1 1
|
|
0 0
|
|
.names A_19_.BLIF a_c_19__n
|
|
1 1
|
|
0 0
|
|
.names A_20_.BLIF a_c_20__n
|
|
1 1
|
|
0 0
|
|
.names A_21_.BLIF a_c_21__n
|
|
1 1
|
|
0 0
|
|
.names A_22_.BLIF a_c_22__n
|
|
1 1
|
|
0 0
|
|
.names A_23_.BLIF a_c_23__n
|
|
1 1
|
|
0 0
|
|
.names A_24_.BLIF a_c_24__n
|
|
1 1
|
|
0 0
|
|
.names A_25_.BLIF a_c_25__n
|
|
1 1
|
|
0 0
|
|
.names A_26_.BLIF a_c_26__n
|
|
1 1
|
|
0 0
|
|
.names A_27_.BLIF a_c_27__n
|
|
1 1
|
|
0 0
|
|
.names A_28_.BLIF a_c_28__n
|
|
1 1
|
|
0 0
|
|
.names A_29_.BLIF a_c_29__n
|
|
1 1
|
|
0 0
|
|
.names A_30_.BLIF a_c_30__n
|
|
1 1
|
|
0 0
|
|
.names A_31_.BLIF a_c_31__n
|
|
1 1
|
|
0 0
|
|
.names A0.PIN.BLIF A0_c
|
|
1 1
|
|
0 0
|
|
.names A1.BLIF A1_c
|
|
1 1
|
|
0 0
|
|
.names nEXP_SPACE.BLIF nEXP_SPACE_c
|
|
1 1
|
|
0 0
|
|
.names BERR.PIN.BLIF BERR_c
|
|
1 1
|
|
0 0
|
|
.names BG_030.BLIF BG_030_c
|
|
1 1
|
|
0 0
|
|
.names BGACK_000.BLIF BGACK_000_c
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_OSZI_c
|
|
1 1
|
|
0 0
|
|
.names CLK_030.BLIF CLK_EXP_c
|
|
1 1
|
|
0 0
|
|
.names FPU_SENSE.BLIF FPU_SENSE_c
|
|
1 1
|
|
0 0
|
|
.names IPL_0_.BLIF ipl_c_0__n
|
|
1 1
|
|
0 0
|
|
.names IPL_1_.BLIF ipl_c_1__n
|
|
1 1
|
|
0 0
|
|
.names IPL_2_.BLIF ipl_c_2__n
|
|
1 1
|
|
0 0
|
|
.names DTACK.BLIF DTACK_c
|
|
1 1
|
|
0 0
|
|
.names VPA.BLIF VPA_c
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF RST_c
|
|
1 1
|
|
0 0
|
|
.names RW.PIN.BLIF RW_c
|
|
1 1
|
|
0 0
|
|
.names FC_0_.BLIF fc_c_0__n
|
|
1 1
|
|
0 0
|
|
.names FC_1_.BLIF fc_c_1__n
|
|
1 1
|
|
0 0
|
|
.names N_112.BLIF AS_030.OE
|
|
1 1
|
|
0 0
|
|
.names un1_as_000_i.BLIF AS_000.OE
|
|
1 1
|
|
0 0
|
|
.names un1_as_000_i.BLIF RW_000.OE
|
|
1 1
|
|
0 0
|
|
.names N_112.BLIF DS_030.OE
|
|
1 1
|
|
0 0
|
|
.names un1_as_000_i.BLIF UDS_000.OE
|
|
1 1
|
|
0 0
|
|
.names un1_as_000_i.BLIF LDS_000.OE
|
|
1 1
|
|
0 0
|
|
.names N_89.BLIF SIZE_0_.OE
|
|
1 1
|
|
0 0
|
|
.names N_89.BLIF SIZE_1_.OE
|
|
1 1
|
|
0 0
|
|
.names N_112.BLIF A0.OE
|
|
1 1
|
|
0 0
|
|
.names un22_berr.BLIF BERR.OE
|
|
1 1
|
|
0 0
|
|
.names N_256.BLIF RW.OE
|
|
1 1
|
|
0 0
|
|
.names gnd_n_n.BLIF CLK_DIV_OUT.OE
|
|
1 1
|
|
0 0
|
|
.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE
|
|
1 1
|
|
0 0
|
|
.names N_247.BLIF CIIN.OE
|
|
1 1
|
|
0 0
|
|
.end
|