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cf62aa3b3f
68030tk/Logic/68030_tk.bl3
MHeinrichs cf62aa3b3f timing enhanced?
2014-05-25 21:20:36 +02:00

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#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Sun May 25 21:18:50 2014
#$ MODULE 68030_tk
#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 SIZE_0_ DS_030 \
# A_30_ UDS_000 A_29_ LDS_000 A_28_ A0 A_27_ nEXP_SPACE A_26_ BERR A_25_ BG_030 A_24_ BG_000 \
# A_23_ BGACK_030 A_22_ BGACK_000 A_21_ CLK_030 A_20_ CLK_000 A_19_ CLK_OSZI A_18_ \
# CLK_DIV_OUT A_17_ CLK_EXP A_16_ FPU_CS IPL_030_1_ DTACK IPL_030_0_ AVEC IPL_1_ AVEC_EXP \
# IPL_0_ E DSACK_0_ VPA FC_0_ VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
# AMIGA_BUS_ENABLE_LOW CIIN
#$ NODES 44 BG_000DFFSHreg inst_BGACK_030_INTreg inst_FPU_CS_INTreg \
# inst_VMA_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_SYNC inst_VPA_D \
# inst_CLK_000_D0 CLK_OUT_INTreg inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 \
# IPL_030DFFSH_0_reg inst_CLK_OUT_PRE inst_BGACK_030_INT_D IPL_030DFFSH_1_reg \
# IPL_030DFFSH_2_reg CLK_CNT_P_0_ SM_AMIGA_5_ inst_CLK_000_D4 SM_AMIGA_7_ SM_AMIGA_1_ \
# SM_AMIGA_0_ SM_AMIGA_6_ inst_AS_000_DMA inst_AS_000_INT inst_UDS_000_INT \
# inst_LDS_000_INT inst_DSACK1_INT inst_CLK_000_D3 SM_AMIGA_3_ inst_DS_000_DMA \
# SIZE_DMA_0_ SIZE_DMA_1_ inst_A0_DMA SM_AMIGA_4_ RESETDFFRHreg SM_AMIGA_2_ \
# AMIGA_BUS_ENABLEDFFSHreg cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_reg
.model bus68030
.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \
RW.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \
A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \
A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF BG_000DFFSHreg.BLIF \
inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF inst_VMA_INTreg.BLIF \
inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \
inst_VPA_D.BLIF inst_CLK_000_D0.BLIF CLK_OUT_INTreg.BLIF inst_CLK_000_D1.BLIF \
inst_CLK_000_D2.BLIF inst_CLK_000_D5.BLIF IPL_030DFFSH_0_reg.BLIF \
inst_CLK_OUT_PRE.BLIF inst_BGACK_030_INT_D.BLIF IPL_030DFFSH_1_reg.BLIF \
IPL_030DFFSH_2_reg.BLIF CLK_CNT_P_0_.BLIF SM_AMIGA_5_.BLIF \
inst_CLK_000_D4.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \
SM_AMIGA_6_.BLIF inst_AS_000_DMA.BLIF inst_AS_000_INT.BLIF \
inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF \
inst_CLK_000_D3.BLIF SM_AMIGA_3_.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF \
SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF SM_AMIGA_4_.BLIF RESETDFFRHreg.BLIF \
SM_AMIGA_2_.BLIF AMIGA_BUS_ENABLEDFFSHreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
cpu_est_2_.BLIF cpu_est_3_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \
AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \
cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C \
cpu_est_2_.AR cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \
SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030DFFSH_0_reg.D \
IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \
IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \
IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \
SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \
SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \
SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \
SM_AMIGA_2_.AR inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP \
inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_VMA_INTreg.D \
inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \
inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D \
inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR SIZE_DMA_0_.D SIZE_DMA_0_.C \
SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP inst_DS_000_DMA.D \
inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \
inst_FPU_CS_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \
inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \
BG_000DFFSHreg.AP inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP \
inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \
AMIGA_BUS_ENABLEDFFSHreg.D AMIGA_BUS_ENABLEDFFSHreg.C \
AMIGA_BUS_ENABLEDFFSHreg.AP inst_UDS_000_INT.D inst_UDS_000_INT.C \
inst_UDS_000_INT.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP \
inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \
inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D5.D \
inst_CLK_000_D5.C inst_CLK_000_D5.AP inst_CLK_000_D3.D inst_CLK_000_D3.C \
inst_CLK_000_D3.AP CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR \
inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D1.D \
inst_CLK_000_D1.C inst_CLK_000_D1.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
CLK_OUT_INTreg.AR inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \
inst_BGACK_030_INT_D.AP inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP \
inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP RESETDFFRHreg.D RESETDFFRHreg.C \
RESETDFFRHreg.AR SIZE_1_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 \
DTACK SIZE_0_ DSACK_0_ AS_030.OE AS_000.OE DS_030.OE UDS_000.OE LDS_000.OE \
SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE DSACK_0_.OE \
AVEC_EXP.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF cpu_est_0_.D
100 1
-11 1
0-1 1
101 0
-10 0
0-0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_1_.D
1010-- 1
--01-- 1
10--00 1
10--11 1
-1-1-- 1
0--1-- 1
101110 0
101101 0
--0010 0
--0001 0
-1-0-- 0
0--0-- 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_2_.D
1000-- 1
---11- 1
101--1 1
-1--1- 1
0---1- 1
--1-00 0
1010-0 0
--010- 0
-1--0- 0
0---0- 0
.names inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D5.BLIF \
inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D
--011- 1
11---1 1
0---1- 1
-1--1- 1
10-0-- 0
101--- 0
0---0- 0
-0--0- 0
----00 0
.names inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D5.BLIF \
inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF inst_AS_000_INT.BLIF \
SM_AMIGA_0_.D
10-01-- 1
101-1-- 1
0----1- 1
-0---1- 1
-----10 1
--01-0- 0
11----1 0
----00- 0
0----0- 0
-1---0- 0
.names IPL_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_0_reg.D
110- 1
--11 1
-0-1 1
010- 0
--10 0
-0-0 0
.names IPL_1_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_1_reg.D
110- 1
--11 1
-0-1 1
010- 0
--10 0
-0-0 0
.names IPL_2_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
IPL_030DFFSH_2_reg.BLIF IPL_030DFFSH_2_reg.D
110- 1
--11 1
-0-1 1
010- 0
--10 0
-0-0 0
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_0_.BLIF \
SM_AMIGA_6_.BLIF inst_AS_000_INT.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_7_.D
-1-1--1-1- 1
01-0---1-- 1
----11---- 1
--1--1---- 1
-0---1---- 1
-----1---0 1
-1010---01 0
-1000--0-1 0
-1010-0--1 0
11000----1 0
---1-0--0- 0
---0-0-0-- 0
---1-00--- 0
1--0-0---- 0
-0---0---- 0
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF \
inst_CLK_000_D3.BLIF SM_AMIGA_6_.D
-10-01-1 1
1--0--1- 1
-0----1- 1
-1-1-0-- 0
01---0-- 0
-1-11--- 0
01--1--- 0
-111---- 0
011----- 0
-1-1---0 0
01-----0 0
-0----0- 0
-----00- 0
----1-0- 0
--1---0- 0
------00 0
.names inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_5_.D
11-1 1
0-1- 1
-11- 1
0-0- 0
10-- 0
--00 0
.names inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF \
SM_AMIGA_4_.BLIF SM_AMIGA_4_.D
101- 1
0--1 1
-0-1 1
11-- 0
--00 0
0--0 0
.names inst_BGACK_030_INTreg.BLIF inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \
inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.D
-11-1- 1
1--1-1 1
0---1- 1
---11- 1
1-00-- 0
10-0-- 0
0---0- 0
---00- 0
----00 0
.names inst_BGACK_030_INTreg.BLIF inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \
inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_2_.D
1-001- 1
10-01- 1
0----1 1
---0-1 1
1--1-- 0
-11--0 0
----00 0
0----0 0
.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_D4.BLIF \
inst_AS_000_INT.BLIF AS_030.PIN.BLIF inst_AS_000_INT.D
--01- 1
-0-1- 1
0--1- 1
--0-1 1
-0--1 1
0---1 1
111-- 0
---00 0
.names inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF inst_VPA_SYNC.BLIF \
inst_VPA_D.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF cpu_est_1_.BLIF \
cpu_est_3_reg.BLIF AS_030.PIN.BLIF inst_VPA_SYNC.D
--1----0- 1
--1---1-- 1
--1--0--- 1
--1-0---- 1
--11----- 1
-11------ 1
0-1------ 1
-------01 1
------1-1 1
-----0--1 1
----0---1 1
---1----1 1
-1------1 1
0-------1 1
10-01101- 0
--0-----0 0
.names inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF \
inst_CLK_000_D0.BLIF SM_AMIGA_7_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
inst_VMA_INTreg.D
1---1-- 1
-1---0- 1
-1-1--- 1
-11---- 1
-1----1 1
--00010 0
0-00-10 0
-0--0-- 0
00----- 0
.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D
1-10 1
11-- 1
-00- 0
0--- 0
-0-1 0
.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
SIZE_DMA_0_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
SIZE_DMA_0_.D
-1-1--- 1
-0---1- 1
-0--1-- 1
10----- 1
-10---- 1
-0----1 1
00--000 0
-110--- 0
.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
SIZE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
SIZE_DMA_1_.D
-1-1--- 1
-0---00 1
-0---11 1
-0--1-- 1
10----- 1
-10---- 1
00--010 0
00--001 0
-110--- 0
.names CLK_030.BLIF RW.BLIF inst_BGACK_030_INTreg.BLIF \
inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF \
AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_DS_000_DMA.D
--1--1--- 1
-00-1---- 1
--0---1-- 1
1-0------ 1
--0----11 1
--10----- 1
0-0-0-00- 0
010---00- 0
--11-0--- 0
0-0-0-0-0 0
010---0-0 0
.names FC_1_.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \
A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF AS_030.PIN.BLIF \
inst_FPU_CS_INTreg.D
-------01- 1
------1-1- 1
-----0--1- 1
----1---1- 1
---1----1- 1
--0-----1- 1
-0------1- 1
0-------1- 1
---------1 1
11100101-0 0
--------00 0
.names inst_BGACK_030_INTreg.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \
inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF AS_030.PIN.BLIF DTACK.PIN.BLIF \
inst_DTACK_SYNC.D
-1--0-- 1
-1-0--- 1
-10---- 1
01----- 1
-1----1 1
----01- 1
---0-1- 1
--0--1- 1
0----1- 1
-----11 1
1-111-0 0
-0---0- 0
.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
inst_A0_DMA.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
inst_A0_DMA.D
00--010 1
-111--- 1
-1-0--- 0
-10---- 0
-0---0- 0
-0--1-- 0
10----- 0
-0----1 0
.names nEXP_SPACE.BLIF BG_030.BLIF CLK_000.BLIF BG_000DFFSHreg.BLIF \
SM_AMIGA_7_.BLIF AS_030.PIN.BLIF BG_000DFFSHreg.D
---10- 1
--01-- 1
0--1-- 1
---1-0 1
-1---- 1
101-11 0
-0-0-- 0
.names inst_BGACK_030_INTreg.BLIF inst_CLK_000_D5.BLIF inst_CLK_000_D4.BLIF \
SM_AMIGA_1_.BLIF inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D
---01- 1
--0-1- 1
-1--1- 1
0---1- 1
---0-1 1
--0--1 1
-1---1 1
0----1 1
1011-- 0
----00 0
.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
inst_AS_000_DMA.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
inst_AS_000_DMA.D
-1-1--- 1
-0--1-- 1
10----- 1
-0---11 1
-10---- 1
00--00- 0
00--0-0 0
-110--- 0
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_6_.BLIF \
AMIGA_BUS_ENABLEDFFSHreg.BLIF AS_030.PIN.BLIF AMIGA_BUS_ENABLEDFFSHreg.D
-1----01- 1
01-----1- 1
11-1--1-- 1
-00----1- 1
-10---0-- 1
010------ 1
-1---10-1 1
-1--1-0-1 1
01---1--1 1
01--1---1 1
11-0--1-- 0
--1-0000- 0
0-1-00-0- 0
--1---000 0
0-1----00 0
-0-----0- 0
-01------ 0
.names RW.BLIF inst_BGACK_030_INTreg.BLIF SM_AMIGA_5_.BLIF \
inst_CLK_000_D4.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF \
DS_030.PIN.BLIF A0.PIN.BLIF inst_UDS_000_INT.D
1111---01 1
01---1-01 1
0---10--- 1
1--01---- 1
1-0-1---- 1
0----01-- 1
1--0--1-- 1
1-0---1-- 1
----1--1- 1
-0--1---- 1
------11- 1
-0----1-- 1
1111---00 0
01---1-00 0
0---000-- 0
1--00-0-- 0
1-0-0-0-- 0
----0-01- 0
-0--0-0-- 0
.names RW.BLIF inst_BGACK_030_INTreg.BLIF SM_AMIGA_5_.BLIF \
inst_CLK_000_D4.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF \
DS_030.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF \
inst_LDS_000_INT.D
1111---0100 1
01---1-0100 1
0---10----- 1
1--01------ 1
1-0-1------ 1
0----01---- 1
----1--1--- 1
-0--1------ 1
1--0--1---- 1
1-0---1---- 1
------11--- 1
-0----1---- 1
1111---0-1- 0
1111---00-- 0
01---1-0-1- 0
01---1-00-- 0
1111---0--1 0
01---1-0--1 0
0---000---- 0
1--00-0---- 0
1-0-0-0---- 0
----0-01--- 0
-0--0-0---- 0
.names FC_1_.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \
A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
inst_AS_030_000_SYNC.BLIF inst_CLK_000_D5.BLIF inst_CLK_000_D4.BLIF \
SM_AMIGA_7_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_6_.BLIF AS_030.PIN.BLIF \
inst_AS_030_000_SYNC.D
1-1-00101-1------ 1
---------1-01-1-- 1
-0-------1-----1- 1
----------1--0--- 1
---0------1------ 1
-0--------1------ 1
----------------1 1
----------0---000 0
----------0-0--00 0
----------01---00 0
-1-1----00---1--0 0
-1-1---1-0---1--0 0
-1-1--0--0---1--0 0
-1-1-1---0---1--0 0
-1-11----0---1--0 0
-101-----0---1--0 0
01-1-----0---1--0 0
-1-1----0----10-0 0
-1-1---1-----10-0 0
-1-1--0------10-0 0
-1-1-1-------10-0 0
-1-11--------10-0 0
-101---------10-0 0
01-1---------10-0 0
-1-1----0---01--0 0
-1-1---1----01--0 0
-1-1--0-----01--0 0
-1-1-1------01--0 0
-1-11-------01--0 0
-101--------01--0 0
01-1--------01--0 0
-1-1----0--1-1--0 0
-1-1---1---1-1--0 0
-1-1--0----1-1--0 0
-1-1-1-----1-1--0 0
-1-11------1-1--0 0
-101-------1-1--0 0
01-1-------1-1--0 0
-1--------0---0-0 0
-1--------0-0---0 0
-1--------01----0 0
---------00-----0 0
.names CLK_CNT_P_0_.BLIF CLK_CNT_P_0_.D
0 1
1 0
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
1 1
0 0
.names BERR
0
.names BG_000DFFSHreg.BLIF BG_000
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF BGACK_030
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_EXP
1 1
0 0
.names inst_FPU_CS_INTreg.BLIF FPU_CS
1 1
0 0
.names AVEC
1
.names AVEC_EXP
0
.names cpu_est_3_reg.BLIF E
1 1
0 0
.names inst_VMA_INTreg.BLIF VMA
1 1
0 0
.names RESETDFFRHreg.BLIF RESET
1 1
0 0
.names AMIGA_BUS_ENABLEDFFSHreg.BLIF AMIGA_BUS_ENABLE
1 1
0 0
.names nEXP_SPACE.BLIF RW.BLIF inst_BGACK_030_INTreg.BLIF AMIGA_BUS_DATA_DIR
010 1
-01 1
1-0 0
-00 0
-11 0
.names AMIGA_BUS_ENABLE_LOW
1
.names A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF CIIN
1111 1
--0- 0
-0-- 0
0--- 0
---0 0
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
1 1
0 0
.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_0_.C
1 1
0 0
.names RST.BLIF cpu_est_0_.AR
0 1
1 0
.names CLK_OSZI.BLIF cpu_est_1_.C
1 1
0 0
.names RST.BLIF cpu_est_1_.AR
0 1
1 0
.names CLK_OSZI.BLIF cpu_est_2_.C
1 1
0 0
.names RST.BLIF cpu_est_2_.AR
0 1
1 0
.names CLK_OSZI.BLIF cpu_est_3_reg.C
1 1
0 0
.names RST.BLIF cpu_est_3_reg.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_1_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_0_.AR
0 1
1 0
.names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C
1 1
0 0
.names RST.BLIF IPL_030DFFSH_0_reg.AP
0 1
1 0
.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C
1 1
0 0
.names RST.BLIF IPL_030DFFSH_1_reg.AP
0 1
1 0
.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C
1 1
0 0
.names RST.BLIF IPL_030DFFSH_2_reg.AP
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_7_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_7_.AP
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_6_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_5_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_4_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_3_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_2_.AR
0 1
1 0
.names CLK_OSZI.BLIF inst_AS_000_INT.C
1 1
0 0
.names RST.BLIF inst_AS_000_INT.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_VPA_SYNC.C
1 1
0 0
.names RST.BLIF inst_VPA_SYNC.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_VMA_INTreg.C
1 1
0 0
.names RST.BLIF inst_VMA_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names RST.BLIF inst_BGACK_030_INTreg.AP
0 1
1 0
.names inst_CLK_OUT_PRE.BLIF CLK_CNT_P_0_.BLIF inst_CLK_OUT_PRE.D
10 1
01 1
00 0
11 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C
1 1
0 0
.names RST.BLIF inst_CLK_OUT_PRE.AR
0 1
1 0
.names CLK_OSZI.BLIF SIZE_DMA_0_.C
1 1
0 0
.names RST.BLIF SIZE_DMA_0_.AP
0 1
1 0
.names CLK_OSZI.BLIF SIZE_DMA_1_.C
1 1
0 0
.names RST.BLIF SIZE_DMA_1_.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_DS_000_DMA.C
1 1
0 0
.names RST.BLIF inst_DS_000_DMA.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_FPU_CS_INTreg.C
1 1
0 0
.names RST.BLIF inst_FPU_CS_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_DTACK_SYNC.C
1 1
0 0
.names RST.BLIF inst_DTACK_SYNC.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_A0_DMA.C
1 1
0 0
.names RST.BLIF inst_A0_DMA.AP
0 1
1 0
.names CLK_OSZI.BLIF BG_000DFFSHreg.C
1 1
0 0
.names RST.BLIF BG_000DFFSHreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_DSACK1_INT.C
1 1
0 0
.names RST.BLIF inst_DSACK1_INT.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
1 1
0 0
.names RST.BLIF inst_AS_000_DMA.AP
0 1
1 0
.names CLK_OSZI.BLIF AMIGA_BUS_ENABLEDFFSHreg.C
1 1
0 0
.names RST.BLIF AMIGA_BUS_ENABLEDFFSHreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_UDS_000_INT.C
1 1
0 0
.names RST.BLIF inst_UDS_000_INT.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
1 1
0 0
.names RST.BLIF inst_LDS_000_INT.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names RST.BLIF inst_AS_030_000_SYNC.AP
0 1
1 0
.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D4.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D4.AP
0 1
1 0
.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D5.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D5.AP
0 1
1 0
.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D3.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D3.AP
0 1
1 0
.names CLK_OSZI.BLIF CLK_CNT_P_0_.C
1 1
0 0
.names RST.BLIF CLK_CNT_P_0_.AR
0 1
1 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D2.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D2.AP
0 1
1 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D1.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D1.AP
0 1
1 0
.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names RST.BLIF CLK_OUT_INTreg.AR
0 1
1 0
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
1 1
0 0
.names RST.BLIF inst_BGACK_030_INT_D.AP
0 1
1 0
.names CLK_000.BLIF inst_CLK_000_D0.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D0.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D0.AP
0 1
1 0
.names VPA.BLIF inst_VPA_D.D
1 1
0 0
.names CLK_OSZI.BLIF inst_VPA_D.C
1 1
0 0
.names RST.BLIF inst_VPA_D.AP
0 1
1 0
.names RESETDFFRHreg.D
1
.names CLK_OSZI.BLIF RESETDFFRHreg.C
1 1
0 0
.names RST.BLIF RESETDFFRHreg.AR
0 1
1 0
.names SIZE_DMA_1_.BLIF SIZE_1_
1 1
0 0
.names inst_DSACK1_INT.BLIF DSACK_1_
1 1
0 0
.names inst_AS_000_DMA.BLIF AS_030
1 1
0 0
.names inst_AS_000_INT.BLIF AS_000
1 1
0 0
.names inst_DS_000_DMA.BLIF DS_030
1 1
0 0
.names inst_UDS_000_INT.BLIF UDS_000
1 1
0 0
.names inst_LDS_000_INT.BLIF LDS_000
1 1
0 0
.names inst_A0_DMA.BLIF A0
1 1
0 0
.names DSACK_1_.PIN.BLIF DTACK
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_0_
1 1
0 0
.names DSACK_0_
1
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
AS_030.OE
000 1
-1- 0
1-- 0
--1 0
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
0 0
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
DS_030.OE
000 1
-1- 0
1-- 0
--1 0
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
1 1
0 0
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
SIZE_0_.OE
000 1
-1- 0
1-- 0
--1 0
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
SIZE_1_.OE
000 1
-1- 0
1-- 0
--1 0
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF A0.OE
000 1
-1- 0
1-- 0
--1 0
.names nEXP_SPACE.BLIF DSACK_1_.OE
1 1
0 0
.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
DTACK.OE
000 1
-1- 0
1-- 0
--1 0
.names inst_FPU_CS_INTreg.BLIF BERR.OE
0 1
1 0
.names nEXP_SPACE.BLIF DSACK_0_.OE
1 1
0 0
.names inst_FPU_CS_INTreg.BLIF AVEC_EXP.OE
0 1
1 0
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
A_25_.BLIF A_24_.BLIF CIIN.OE
00000000 1
------1- 0
-----1-- 0
----1--- 0
---1---- 0
--1----- 0
-1------ 0
1------- 0
-------1 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_1_.BLIF \
cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_3_reg.D.X1
10111 1
0---- 0
-1--- 0
--0-- 0
---0- 0
----0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_3_reg.D.X2
-----1 1
101-0- 1
10-00- 1
0----0 0
-1---0 0
----10 0
--01-0 0
.end
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