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d187b3fa35
68030tk/Logic/68030_tk.bl3
MHeinrichs d187b3fa35 33MHz @100MHz basis working
2014-05-24 16:03:26 +02:00

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#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Sat May 24 15:48:50 2014
#$ MODULE 68030_tk
#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ SIZE_0_ IPL_2_ A_30_ A_29_ DSACK_1_ A_28_ A_27_ \
# FC_1_ A_26_ AS_030 A_25_ AS_000 A_24_ DS_030 A_23_ UDS_000 A_22_ LDS_000 A_21_ nEXP_SPACE \
# A_20_ BERR A_19_ BG_030 A_18_ BG_000 A_17_ BGACK_030 A_16_ BGACK_000 CLK_030 CLK_000 \
# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW A_0_ \
# AMIGA_BUS_ENABLE IPL_030_1_ AMIGA_BUS_DATA_DIR IPL_030_0_ AMIGA_BUS_ENABLE_LOW \
# IPL_1_ CIIN IPL_0_ DSACK_0_ FC_0_
#$ NODES 42 CLK_OUT_INTreg IPL_030DFFSH_0_reg inst_BGACK_030_INTreg \
# inst_FPU_CS_INTreg IPL_030DFFSH_1_reg inst_VMA_INTreg inst_AS_000_INTreg \
# IPL_030DFFSH_2_reg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC \
# inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 SM_AMIGA_5_ \
# SM_AMIGA_6_ inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ inst_CLK_000_D3 \
# SM_AMIGA_4_ RESETDFFRHreg inst_CLK_000_D4 inst_DTACK_DMA SM_AMIGA_7_ SM_AMIGA_3_ \
# SM_AMIGA_1_ AMIGA_BUS_ENABLEDFFreg CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ \
# CLK_CNT_P_1_ SM_AMIGA_2_ SM_AMIGA_0_ inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ \
# cpu_est_2_ cpu_est_3_reg BG_000DFFSHreg
.model bus68030
.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \
nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \
A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \
A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \
IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \
inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF \
inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF IPL_030DFFSH_2_reg.BLIF \
inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \
inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
inst_CLK_000_D2.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_6_.BLIF \
inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF \
inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF RESETDFFRHreg.BLIF inst_CLK_000_D4.BLIF \
inst_DTACK_DMA.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_1_.BLIF \
AMIGA_BUS_ENABLEDFFreg.BLIF CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF \
CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \
inst_CLK_OUT_PRE.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
cpu_est_3_reg.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \
CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_2_.D cpu_est_2_.C \
cpu_est_2_.AR cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C \
cpu_est_0_.AR cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR SM_AMIGA_3_.D \
SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR \
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C \
SM_AMIGA_0_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D \
CLK_CNT_N_1_.C CLK_CNT_N_1_.AR CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR \
CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR IPL_030DFFSH_0_reg.D \
IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \
IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \
IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \
SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \
SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \
inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP \
inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP \
inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_VMA_INTreg.C \
inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \
inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C \
inst_AS_000_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \
inst_CLK_OUT_PRE.AR CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR \
inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \
inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \
inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C \
DSACK_INT_1_.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C \
inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D5.D \
inst_CLK_000_D5.C inst_CLK_000_D5.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \
BG_000DFFSHreg.AP inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP \
inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.D \
inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \
inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP RESETDFFRHreg.D \
RESETDFFRHreg.C RESETDFFRHreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C \
inst_CLK_000_D1.AP DSACK_1_ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE \
UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE \
inst_VMA_INTreg.D.X1 inst_VMA_INTreg.D.X2 cpu_est_3_reg.D.X1 \
cpu_est_3_reg.D.X2
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_2_.D
1000-- 1
---11- 1
101--1 1
-1--1- 1
0---1- 1
--1-00 0
1010-0 0
--010- 0
-1--0- 0
0---0- 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF cpu_est_0_.D
100 1
-11 1
0-1 1
101 0
-10 0
0-0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_1_.D
1010-- 1
--01-- 1
10--00 1
10--11 1
-1-1-- 1
0--1-- 1
101110 0
101101 0
--0010 0
--0001 0
-1-0-- 0
0--0-- 0
.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \
SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D
--11- 1
11--1 1
--1-1 1
-00-- 0
0-0-- 0
---00 0
--0-0 0
.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \
SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_2_.D
-001- 1
0-01- 1
--0-1 1
11--0 0
--1-- 0
---00 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D5.BLIF inst_CLK_000_D4.BLIF \
SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D
-011- 1
1--1- 1
1---1 1
0-0-- 0
01--- 0
0--0- 0
---00 0
.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D5.BLIF \
inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D
-0-01- 1
-01-1- 1
0----1 1
-0---1 1
11---- 0
--01-0 0
----00 0
-1---0 0
.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF CLK_CNT_N_0_.D
00 1
11 1
10 0
01 0
.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF CLK_CNT_P_0_.D
00 1
11 1
10 0
01 0
.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF IPL_030DFFSH_0_reg.D
1-10 1
-10- 1
-1-1 1
0-10 0
-00- 0
-0-1 0
.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF IPL_030DFFSH_1_reg.D
1-10 1
-10- 1
-1-1 1
0-10 0
-00- 0
-0-1 0
.names IPL_2_.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.D
1-10 1
-10- 1
-1-1 1
0-10 0
-00- 0
-0-1 0
.names nEXP_SPACE.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF \
inst_CLK_000_D3.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.D
0--0-1--- 1
-1-1----1 1
------01- 1
----1--1- 1
--1----1- 1
-0010-1-- 0
--00001-- 0
1-000-1-- 0
--010-1-0 0
-0-1---0- 0
---0-0-0- 0
1--0---0- 0
---1---00 0
.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_7_.BLIF \
SM_AMIGA_6_.D
1-0-1-0 1
-0-0-11 1
----0-0 0
--1---0 0
0-----0 0
-----01 0
---1--1 0
-1----1 0
.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.D
11- 1
1-1 1
-00 0
0-- 0
.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_4_.D
01- 1
0-1 1
-00 0
1-- 0
.names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF SM_AMIGA_5_.BLIF \
inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D
-0111-- 1
--1-01- 1
-001--1 1
--0--10 1
-1---1- 1
1-1-0-- 1
1-0---0 1
11----- 1
-0101-- 0
0-1-00- 0
-000--1 0
0-0--00 0
01---0- 0
.names SIZE_1_.BLIF AS_030.BLIF DS_030.BLIF RW.BLIF SIZE_0_.BLIF A_0_.BLIF \
SM_AMIGA_5_.BLIF inst_LDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \
inst_LDS_000_INTreg.D
0-01101-- 1
0-0010--1 1
---1--01- 1
-1-1--0-- 1
---0---10 1
-1-0----0 1
--1----1- 1
-11------ 1
-0-1--00- 0
-01----0- 0
--01-11-- 0
--010-1-- 0
1-01--1-- 0
-0-0---00 0
--00-1--1 0
--000---1 0
1-00----1 0
.names AS_030.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF \
inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF cpu_est_1_.BLIF cpu_est_3_reg.BLIF \
inst_VPA_SYNC.D
---1--1- 1
---1-0-- 1
---10--- 1
--11---- 1
-1-1---- 1
---1---0 1
1-----1- 1
1----0-- 1
1---0--- 1
1-1----- 1
11------ 1
1------0 1
-00-1101 0
0--0---- 0
.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D
1-10 1
11-- 1
-00- 0
0--- 0
-0-1 0
.names AS_030.BLIF inst_AS_000_INTreg.BLIF SM_AMIGA_5_.BLIF \
inst_AS_000_INTreg.D
-10 1
1-0 1
00- 0
--1 0
.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF \
inst_CLK_OUT_PRE.D
1010 1
0110 1
1001 1
0101 1
00-- 0
11-- 0
--00 0
--11 0
.names FC_1_.BLIF AS_030.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \
A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \
inst_AS_030_000_SYNC.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_6_.BLIF \
inst_CLK_000_D4.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_1_.BLIF inst_AS_030_000_SYNC.D
1--1-001011----- 1
-----------0-1-1 1
--0---------1--- 1
----------1---0- 1
----0-----1----- 1
--0-------1----- 1
-1-------------- 1
-0--------0-00-- 0
-0--------010--- 0
-01-1----0---01- 0
-01-1---1----01- 0
-01-1--0-----01- 0
-01-1-1------01- 0
-01-11-------01- 0
-0101--------01- 0
001-1--------01- 0
-01-1----0-1--1- 0
-01-1---1--1--1- 0
-01-1--0---1--1- 0
-01-1-1----1--1- 0
-01-11-----1--1- 0
-0101------1--1- 0
001-1------1--1- 0
-0--------0-0--0 0
-01-1----0----10 0
-01-1---1-----10 0
-01-1--0------10 0
-01-1-1-------10 0
-01-11--------10 0
-0101---------10 0
001-1---------10 0
-01-------0--0-- 0
-01-------01---- 0
-01-------0----0 0
.names AS_030.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \
SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D
-1--0- 1
-1-0-- 1
-10--- 1
-1---1 1
1---0- 1
1--0-- 1
1-0--- 1
1----1 1
--1110 0
00---- 0
.names FC_1_.BLIF AS_030.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \
A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF \
inst_FPU_CS_INTreg.D
-1-------- 1
--------01 1
-------1-1 1
------0--1 1
-----1---1 1
----1----1 1
---0-----1 1
--0------1 1
0--------1 1
101100101- 0
-0-------0 0
.names AS_030.BLIF inst_CLK_000_D5.BLIF DSACK_INT_1_.BLIF inst_CLK_000_D4.BLIF \
SM_AMIGA_1_.BLIF DSACK_INT_1_.D
--10- 1
-11-- 1
--1-0 1
1--0- 1
11--- 1
1---0 1
-0-11 0
0-0-- 0
.names AS_030.BLIF nEXP_SPACE.BLIF RST.BLIF SM_AMIGA_6_.BLIF \
AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D
1-10- 1
-011- 1
---01 1
--0-1 1
-111- 0
0--00 0
--0-0 0
.names inst_AS_000_INTreg.BLIF DSACK_1_.PIN.BLIF inst_DTACK_DMA.D
1- 1
-1 1
00 0
.names AS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF SM_AMIGA_7_.BLIF BG_000DFFSHreg.D
----1- 1
---0-- 1
--1--- 1
-1---- 1
0----- 1
-----0 1
100101 0
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
1 1
0 0
.names inst_AS_000_INTreg.BLIF AS_000
1 1
0 0
.names inst_UDS_000_INTreg.BLIF UDS_000
1 1
0 0
.names inst_LDS_000_INTreg.BLIF LDS_000
1 1
0 0
.names BERR
0
.names BG_000DFFSHreg.BLIF BG_000
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF BGACK_030
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_EXP
1 1
0 0
.names inst_FPU_CS_INTreg.BLIF FPU_CS
1 1
0 0
.names AVEC
1
.names AVEC_EXP
0
.names cpu_est_3_reg.BLIF E
1 1
0 0
.names inst_VMA_INTreg.BLIF VMA
1 1
0 0
.names RESETDFFRHreg.BLIF RESET
1 1
0 0
.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE
1 1
0 0
.names RW.BLIF AMIGA_BUS_DATA_DIR
0 1
1 0
.names AMIGA_BUS_ENABLE_LOW
1
.names A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF CIIN
1111 1
--0- 0
-0-- 0
0--- 0
---0 0
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
1 1
0 0
.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_2_.C
1 1
0 0
.names RST.BLIF cpu_est_2_.AR
0 1
1 0
.names CLK_OSZI.BLIF cpu_est_3_reg.C
1 1
0 0
.names RST.BLIF cpu_est_3_reg.AR
0 1
1 0
.names CLK_OSZI.BLIF cpu_est_0_.C
1 1
0 0
.names RST.BLIF cpu_est_0_.AR
0 1
1 0
.names CLK_OSZI.BLIF cpu_est_1_.C
1 1
0 0
.names RST.BLIF cpu_est_1_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_3_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_2_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_1_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_0_.AR
0 1
1 0
.names CLK_OSZI.BLIF CLK_CNT_N_0_.C
0 1
1 0
.names RST.BLIF CLK_CNT_N_0_.AR
0 1
1 0
.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_CNT_N_1_.C
0 1
1 0
.names RST.BLIF CLK_CNT_N_1_.AR
0 1
1 0
.names CLK_OSZI.BLIF CLK_CNT_P_0_.C
1 1
0 0
.names RST.BLIF CLK_CNT_P_0_.AR
0 1
1 0
.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_CNT_P_1_.C
1 1
0 0
.names RST.BLIF CLK_CNT_P_1_.AR
0 1
1 0
.names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C
1 1
0 0
.names RST.BLIF IPL_030DFFSH_0_reg.AP
0 1
1 0
.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C
1 1
0 0
.names RST.BLIF IPL_030DFFSH_1_reg.AP
0 1
1 0
.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C
1 1
0 0
.names RST.BLIF IPL_030DFFSH_2_reg.AP
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_7_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_7_.AP
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_6_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_5_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_4_.AR
0 1
1 0
.names CLK_OSZI.BLIF inst_UDS_000_INTreg.C
1 1
0 0
.names RST.BLIF inst_UDS_000_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_LDS_000_INTreg.C
1 1
0 0
.names RST.BLIF inst_LDS_000_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_VPA_SYNC.C
1 1
0 0
.names RST.BLIF inst_VPA_SYNC.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_VMA_INTreg.C
1 1
0 0
.names RST.BLIF inst_VMA_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names RST.BLIF inst_BGACK_030_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_AS_000_INTreg.C
1 1
0 0
.names RST.BLIF inst_AS_000_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C
1 1
0 0
.names RST.BLIF inst_CLK_OUT_PRE.AR
0 1
1 0
.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names RST.BLIF CLK_OUT_INTreg.AR
0 1
1 0
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names RST.BLIF inst_AS_030_000_SYNC.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_DTACK_SYNC.C
1 1
0 0
.names RST.BLIF inst_DTACK_SYNC.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_FPU_CS_INTreg.C
1 1
0 0
.names RST.BLIF inst_FPU_CS_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF DSACK_INT_1_.C
1 1
0 0
.names RST.BLIF DSACK_INT_1_.AP
0 1
1 0
.names CLK_OSZI.BLIF AMIGA_BUS_ENABLEDFFreg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_DTACK_DMA.C
1 1
0 0
.names RST.BLIF inst_DTACK_DMA.AP
0 1
1 0
.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D5.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D5.AP
0 1
1 0
.names CLK_OSZI.BLIF BG_000DFFSHreg.C
1 1
0 0
.names RST.BLIF BG_000DFFSHreg.AP
0 1
1 0
.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D4.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D4.AP
0 1
1 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D2.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D2.AP
0 1
1 0
.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D3.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D3.AP
0 1
1 0
.names VPA.BLIF inst_VPA_D.D
1 1
0 0
.names CLK_OSZI.BLIF inst_VPA_D.C
1 1
0 0
.names RST.BLIF inst_VPA_D.AP
0 1
1 0
.names CLK_000.BLIF inst_CLK_000_D0.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D0.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D0.AP
0 1
1 0
.names RESETDFFRHreg.D
1
.names CLK_OSZI.BLIF RESETDFFRHreg.C
1 1
0 0
.names RST.BLIF RESETDFFRHreg.AR
0 1
1 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D1.C
1 1
0 0
.names RST.BLIF inst_CLK_000_D1.AP
0 1
1 0
.names DSACK_INT_1_.BLIF DSACK_1_
1 1
0 0
.names inst_DTACK_DMA.BLIF DTACK
1 1
0 0
.names DSACK_0_
1
.names nEXP_SPACE.BLIF DSACK_1_.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF DTACK.OE
0 1
1 0
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
1 1
0 0
.names inst_FPU_CS_INTreg.BLIF BERR.OE
0 1
1 0
.names nEXP_SPACE.BLIF DSACK_0_.OE
1 1
0 0
.names inst_FPU_CS_INTreg.BLIF AVEC_EXP.OE
0 1
1 0
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
A_25_.BLIF A_24_.BLIF CIIN.OE
00000000 1
------1- 0
-----1-- 0
----1--- 0
---1---- 0
--1----- 0
-1------ 0
1------- 0
-------1 0
.names inst_VMA_INTreg.BLIF inst_CLK_000_D0.BLIF inst_VMA_INTreg.D.X1
10 1
0- 0
-1 0
.names inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF \
inst_CLK_000_D0.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \
cpu_est_3_reg.BLIF inst_VMA_INTreg.D.X2
1-0-10-- 1
1--1---- 1
-1-10110 1
00------ 0
--10---- 0
0---1--- 0
---00--- 0
---0-1-- 0
0----0-- 0
0-----0- 0
0------1 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_1_.BLIF \
cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_3_reg.D.X1
10111 1
0---- 0
-1--- 0
--0-- 0
---0- 0
----0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_3_reg.D.X2
-----1 1
101-0- 1
10-00- 1
0----0 0
-1---0 0
----10 0
--01-0 0
.end
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