68030tk/Logic/68030_tk.tt4

#$ TOOL  ispLEVER Classic 1.7.00.05.28.13
#$ DATE  Sat May 24 15:48:50 2014
#$ MODULE  BUS68030
#$ PINS 59 SIZE_1_ A_31_ SIZE_0_ IPL_2_ A_30_ A_29_ A_28_ A_27_ FC_1_ A_26_
 AS_030 A_25_ A_24_ DS_030 A_23_ A_22_ A_21_ nEXP_SPACE A_20_ BERR A_19_ BG_030
 A_18_ A_17_ A_16_ BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT AVEC AVEC_EXP
 VPA RST RW A_0_ AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW IPL_1_ CIIN IPL_0_
 DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030
 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_
#$ NODES 26 inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC
 inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 SM_AMIGA_5_
 SM_AMIGA_6_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 SM_AMIGA_7_ SM_AMIGA_3_
 SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ SM_AMIGA_2_
 SM_AMIGA_0_ inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ cpu_est_2_
.type f
.i 75
.o 147
.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000
 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_
 A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_
 IPL_030_0_.Q BGACK_030.Q FPU_CS.Q IPL_030_1_.Q VMA.Q AS_000.Q IPL_030_2_.Q
 inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q
 inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D5.Q
 SM_AMIGA_5_.Q SM_AMIGA_6_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q
 SM_AMIGA_4_.Q inst_CLK_000_D4.Q SM_AMIGA_7_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q
 AMIGA_BUS_ENABLE.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q
 SM_AMIGA_2_.Q SM_AMIGA_0_.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_1_.Q
 cpu_est_2_.Q E.Q DSACK_1_.PIN DTACK.PIN
.ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR AVEC AVEC_EXP
 AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_
 DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C
 DSACK_1_.AP DSACK_1_.OE AS_000.D AS_000.C AS_000.AP AS_000.OE UDS_000.D%
 UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE
 BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D
 CLK_EXP.C CLK_EXP.AR FPU_CS.D% FPU_CS.C FPU_CS.AP DTACK.D% DTACK.C DTACK.AP
 DTACK.OE E.D.X1 E.D.X2 E.C E.AR VMA.D.X1 VMA.D.X2 VMA.C VMA.AP RESET.D RESET.C
 RESET.AR AMIGA_BUS_ENABLE.D% AMIGA_BUS_ENABLE.C IPL_030_1_.D IPL_030_1_.C
 IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP inst_AS_030_000_SYNC.D
 inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D%
 inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP
 inst_VPA_SYNC.D% inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D
 inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_CLK_000_D1.D inst_CLK_000_D1.C
 inst_CLK_000_D1.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP
 inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP SM_AMIGA_5_.D
 SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR
 inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP SM_AMIGA_4_.D
 SM_AMIGA_4_.C SM_AMIGA_4_.AR inst_CLK_000_D4.D inst_CLK_000_D4.C
 inst_CLK_000_D4.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_3_.D
 SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR
 CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C
 CLK_CNT_N_1_.AR CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.D
 CLK_CNT_P_1_.C CLK_CNT_P_1_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR
 SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C
 inst_CLK_OUT_PRE.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.T
 cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C
 cpu_est_2_.AR
.phase 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
.p 113
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.end