mirror of
https://github.com/kr239/68030tk.git
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788 lines
17 KiB
Plaintext
788 lines
17 KiB
Plaintext
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
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#$ DATE Thu May 15 22:17:27 2014
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#$ MODULE 68030_tk
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#$ PINS 59 FC_0_ SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 \
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# UDS_000 LDS_000 CPU_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 \
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# CLK_OSZI CLK_DIV_OUT SIZE_0_ CLK_EXP A_30_ FPU_CS A_29_ DTACK A_28_ AVEC A_27_ AVEC_EXP \
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# A_26_ E A_25_ VPA A_24_ VMA A_23_ RST A_22_ RESET A_21_ RW A_20_ AMIGA_BUS_ENABLE A_19_ \
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# AMIGA_BUS_DATA_DIR A_18_ AMIGA_BUS_ENABLE_LOW A_17_ CIIN A_16_ A_0_ IPL_030_1_ \
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# IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_
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#$ NODES 42 inst_BGACK_030_INTreg inst_CLK_OUT_INTreg inst_FPU_CS_INTreg \
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# BG_000DFFSHreg cpu_est_3_reg inst_VMA_INTreg cpu_est_0_ cpu_est_1_ cpu_est_d_0_ \
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# cpu_est_d_3_ inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D \
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# inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD IPL_030DFFSH_0_reg inst_CLK_OUT_PRE \
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# IPL_030DFFSH_1_reg cpu_est_d_1_ cpu_est_d_2_ IPL_030DFFSH_2_reg cpu_est_2_ \
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# CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ inst_UDS_000_INTreg inst_LDS_000_INTreg \
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# inst_RISING_CLK_AMIGA SM_AMIGA_1_ DSACK_INT_1_ inst_DTACK_DMA SM_AMIGA_4_ \
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# SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ SM_AMIGA_D_0_ SM_AMIGA_D_1_ \
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# SM_AMIGA_D_2_ RESETDFFreg
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.model bus68030
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.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \
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CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
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CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \
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A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \
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A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \
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IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
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inst_CLK_OUT_INTreg.BLIF inst_FPU_CS_INTreg.BLIF BG_000DFFSHreg.BLIF \
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cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
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cpu_est_d_0_.BLIF cpu_est_d_3_.BLIF inst_AS_000_INTreg.BLIF \
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inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \
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inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
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IPL_030DFFSH_0_reg.BLIF inst_CLK_OUT_PRE.BLIF IPL_030DFFSH_1_reg.BLIF \
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cpu_est_d_1_.BLIF cpu_est_d_2_.BLIF IPL_030DFFSH_2_reg.BLIF cpu_est_2_.BLIF \
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CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \
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inst_LDS_000_INTreg.BLIF inst_RISING_CLK_AMIGA.BLIF SM_AMIGA_1_.BLIF \
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DSACK_INT_1_.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
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SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF \
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SM_AMIGA_D_1_.BLIF SM_AMIGA_D_2_.BLIF RESETDFFreg.BLIF DSACK_1_.PIN.BLIF \
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DTACK.PIN.BLIF
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.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \
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FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
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AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \
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SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \
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SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \
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SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \
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SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030DFFSH_1_reg.D \
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IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \
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IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP cpu_est_0_.D cpu_est_0_.C \
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cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.C \
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SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP cpu_est_d_0_.D cpu_est_d_0_.C \
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cpu_est_d_1_.D cpu_est_d_1_.C cpu_est_d_2_.D cpu_est_d_2_.C cpu_est_d_3_.D \
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cpu_est_d_3_.C SM_AMIGA_D_0_.D SM_AMIGA_D_0_.C SM_AMIGA_D_1_.D SM_AMIGA_D_1_.C \
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SM_AMIGA_D_2_.D SM_AMIGA_D_2_.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C \
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IPL_030DFFSH_0_reg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C \
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inst_AS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \
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inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \
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inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \
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BG_000DFFSHreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP \
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inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \
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inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_UDS_000_INTreg.D \
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inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D \
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inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D \
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inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \
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inst_FPU_CS_INTreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP \
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inst_RISING_CLK_AMIGA.D inst_RISING_CLK_AMIGA.C CLK_CNT_0_.D CLK_CNT_0_.C \
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inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D \
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RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C inst_CLK_OUT_INTreg.D \
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inst_CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE \
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UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_EXP.X1 \
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CLK_EXP.X2 cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 inst_VMA_INTreg.D.X1 \
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inst_VMA_INTreg.D.X2
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.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
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SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.D
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--110 1
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1--10 1
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-0--1 1
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-0-1- 1
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010-- 0
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---00 0
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-1--1 0
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.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
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SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D
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0101- 1
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-1--1 1
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-0--- 0
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---00 0
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--1-0 0
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1---0 0
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.names inst_CLK_000_D.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.D
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01- 1
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0-1 1
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-00 0
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1-- 0
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.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \
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SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D
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--11- 1
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11--1 1
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--1-1 1
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-00-- 0
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0-0-- 0
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---00 0
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--0-0 0
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.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \
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SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_2_.D
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-001- 1
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0-01- 1
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--0-1 1
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11--0 0
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--1-- 0
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---00 0
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.names inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_1_.BLIF \
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SM_AMIGA_2_.BLIF SM_AMIGA_1_.D
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-01- 1
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1-1- 1
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1--1 1
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01-- 0
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0-0- 0
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--00 0
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.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF \
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SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D
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-011- 1
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0---1 1
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-0--1 1
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11--- 0
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---00 0
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--0-0 0
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-1--0 0
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.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_RISING_CLK_AMIGA.BLIF \
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IPL_030DFFSH_1_reg.D
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-10 1
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1-1 1
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-00 0
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0-1 0
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.names IPL_2_.BLIF IPL_030DFFSH_2_reg.BLIF inst_RISING_CLK_AMIGA.BLIF \
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IPL_030DFFSH_2_reg.D
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-10 1
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1-1 1
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-00 0
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0-1 0
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.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \
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inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_1_.D
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0--100 1
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01010- 1
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10-10- 1
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-01--- 1
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1-1--1 1
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--1-1- 1
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--10-- 1
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011101 0
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11-100 0
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000--1 0
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110--- 0
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--0-1- 0
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--00-- 0
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.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \
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inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_2_.D
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-0010- 1
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11-10- 1
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--1--1 1
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----11 1
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---0-1 1
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0-1--0 0
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01010- 0
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-01--0 0
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----10 0
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---0-0 0
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.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF SM_AMIGA_7_.BLIF \
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SM_AMIGA_0_.BLIF SM_AMIGA_7_.D
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-11- 1
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11-1 1
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0-0- 0
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--00 0
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-0-- 0
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.names RST.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_2_.BLIF \
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SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_0_.D
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1---1- 1
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1--1-- 1
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1-1--- 1
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11---- 1
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0----1 1
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10000- 0
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0----0 0
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.names RST.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF \
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SM_AMIGA_0_.BLIF SM_AMIGA_D_1_.BLIF SM_AMIGA_D_1_.D
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1---1- 1
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1--1-- 1
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1-1--- 1
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11---- 1
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0----1 1
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10000- 0
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0----0 0
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.names RST.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
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SM_AMIGA_0_.BLIF SM_AMIGA_D_2_.BLIF SM_AMIGA_D_2_.D
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1---1- 1
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1--1-- 1
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1-1--- 1
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11---- 1
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0----1 1
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10000- 0
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0----0 0
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.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_RISING_CLK_AMIGA.BLIF \
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IPL_030DFFSH_0_reg.D
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-10 1
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1-1 1
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-00 0
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0-1 0
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.names AS_030.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
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inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D
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-1--1- 1
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-1-0-- 1
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-11--- 1
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-1---0 1
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1---1- 1
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1--0-- 1
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1-1--- 1
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1----0 1
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--0101 0
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00---- 0
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.names AS_030.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \
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cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \
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cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D
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------1-0- 1
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------10-- 1
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-----11--- 1
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----1-1--- 1
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---1--1--- 1
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--1---1--- 1
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-0----1--- 1
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------1--0 1
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1-------0- 1
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1------0-- 1
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1----1---- 1
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1---1----- 1
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1--1------ 1
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1-1------- 1
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10-------- 1
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1--------0 1
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-10000-111 0
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0-----0--- 0
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.names FC_1_.BLIF AS_030.BLIF CPU_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \
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A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \
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inst_AS_030_000_SYNC.BLIF inst_AS_030_000_SYNC.D
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1--1100101- 1
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----0-----1 1
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--1-1------ 1
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-1--------- 1
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-00-1----0- 0
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-00-1---1-- 0
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-00-1--0--- 0
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-00-1-1---- 0
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-00-11----- 0
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-0001------ 0
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000-1------ 0
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-0--0-----0 0
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.names AS_030.BLIF CPU_SPACE.BLIF BG_030.BLIF CLK_030.BLIF BG_000DFFSHreg.BLIF \
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SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF BG_000DFFSHreg.D
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---11-- 1
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---0-00 1
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-1-0--- 1
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0--0--- 1
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--1---- 1
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1000-1- 0
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1000--1 0
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--010-- 0
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.names AS_030.BLIF inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_1_.BLIF \
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DSACK_INT_1_.BLIF DSACK_INT_1_.D
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1--0- 1
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1-0-- 1
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11--- 1
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---01 1
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--0-1 1
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-1--1 1
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-011- 0
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0---0 0
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.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_RISING_CLK_AMIGA.BLIF \
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inst_BGACK_030_INTreg.D
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11- 1
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1-1 1
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-00 0
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0-- 0
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.names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF inst_AS_030_000_SYNC.BLIF \
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inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF \
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inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D
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-0110101-- 1
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-001-1---1 1
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--1----01- 1
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--1---1-1- 1
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--1-1---1- 1
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1-1----0-- 1
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1-1---1--- 1
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1-1-1----- 1
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--0-----10 1
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-----0--1- 1
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-1------1- 1
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1-0------0 1
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1----0---- 1
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11-------- 1
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-0100101-- 0
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-000-1---1 0
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0-1----00- 0
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0-1---1-0- 0
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0-1-1---0- 0
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0----0--0- 0
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0-0-----00 0
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01------0- 0
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.names SIZE_1_.BLIF AS_030.BLIF DS_030.BLIF RW.BLIF SIZE_0_.BLIF A_0_.BLIF \
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inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
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SM_AMIGA_6_.BLIF inst_LDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \
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inst_LDS_000_INTreg.D
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0-01100101-- 1
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0-0010-1---1 1
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---1-----01- 1
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---1----1-1- 1
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---1--1---1- 1
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-1-1-----0-- 1
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-1-1----1--- 1
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-1-1--1----- 1
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---0------10 1
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-1-0-------0 1
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-------0--1- 1
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--1-------1- 1
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-1-----0---- 1
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-11--------- 1
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--01-10101-- 0
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--010-0101-- 0
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1-01--0101-- 0
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--00-1-1---1 0
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--000--1---1 0
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1-00---1---1 0
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-0-1-----00- 0
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-0-1----1-0- 0
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-0-1--1---0- 0
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-0-----0--0- 0
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-01-------0- 0
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-0-0------00 0
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.names AS_030.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_CLK_000_D.BLIF \
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SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D
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-1--0- 1
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-1-0-- 1
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-10--- 1
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-1---1 1
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1---0- 1
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1--0-- 1
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1-0--- 1
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1----1 1
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|
--1110 0
|
|
00---- 0
|
|
.names FC_1_.BLIF AS_030.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \
|
|
A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF \
|
|
inst_FPU_CS_INTreg.D
|
|
---0-----1 1
|
|
---1----0- 1
|
|
---1---1-- 1
|
|
---1--0--- 1
|
|
---1-1---- 1
|
|
---11----- 1
|
|
--01------ 1
|
|
0--1------ 1
|
|
-1-------- 1
|
|
101100101- 0
|
|
-0-0-----0 0
|
|
.names inst_AS_000_INTreg.BLIF DSACK_1_.PIN.BLIF inst_DTACK_DMA.D
|
|
1- 1
|
|
-1 1
|
|
00 0
|
|
.names CLK_000.BLIF inst_CLK_000_D.BLIF inst_RISING_CLK_AMIGA.D
|
|
10 1
|
|
0- 0
|
|
-1 0
|
|
.names CLK_CNT_0_.BLIF CLK_CNT_0_.D
|
|
0 1
|
|
1 0
|
|
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
|
|
1 1
|
|
0 0
|
|
.names inst_AS_000_INTreg.BLIF AS_000
|
|
1 1
|
|
0 0
|
|
.names inst_UDS_000_INTreg.BLIF UDS_000
|
|
1 1
|
|
0 0
|
|
.names inst_LDS_000_INTreg.BLIF LDS_000
|
|
1 1
|
|
0 0
|
|
.names BERR
|
|
0
|
|
.names BG_000DFFSHreg.BLIF BG_000
|
|
1 1
|
|
0 0
|
|
.names inst_BGACK_030_INTreg.BLIF BGACK_030
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_OUT_INTreg.BLIF CLK_DIV_OUT
|
|
1 1
|
|
0 0
|
|
.names inst_FPU_CS_INTreg.BLIF FPU_CS
|
|
1 1
|
|
0 0
|
|
.names AVEC
|
|
1
|
|
.names AVEC_EXP
|
|
0
|
|
.names cpu_est_3_reg.BLIF E
|
|
1 1
|
|
0 0
|
|
.names inst_VMA_INTreg.BLIF VMA
|
|
1 1
|
|
0 0
|
|
.names RESETDFFreg.BLIF RESET
|
|
1 1
|
|
0 0
|
|
.names AMIGA_BUS_ENABLE
|
|
0
|
|
.names RW.BLIF AMIGA_BUS_DATA_DIR
|
|
0 1
|
|
1 0
|
|
.names AMIGA_BUS_ENABLE_LOW
|
|
1
|
|
.names A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF CIIN
|
|
1111 1
|
|
--0- 0
|
|
-0-- 0
|
|
0--- 0
|
|
---0 0
|
|
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
|
|
1 1
|
|
0 0
|
|
.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_6_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_5_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_4_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_3_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_2_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_1_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_0_.AR
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF IPL_030DFFSH_1_reg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF IPL_030DFFSH_2_reg.AP
|
|
0 1
|
|
1 0
|
|
.names cpu_est_0_.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF cpu_est_0_.D
|
|
010 1
|
|
10- 1
|
|
1-1 1
|
|
110 0
|
|
00- 0
|
|
0-1 0
|
|
.names CLK_OSZI.BLIF cpu_est_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_3_reg.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_7_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF SM_AMIGA_7_.AP
|
|
0 1
|
|
1 0
|
|
.names cpu_est_0_.BLIF cpu_est_d_0_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_d_0_.C
|
|
1 1
|
|
0 0
|
|
.names cpu_est_1_.BLIF cpu_est_d_1_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_d_1_.C
|
|
1 1
|
|
0 0
|
|
.names cpu_est_2_.BLIF cpu_est_d_2_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_d_2_.C
|
|
1 1
|
|
0 0
|
|
.names cpu_est_3_reg.BLIF cpu_est_d_3_.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF cpu_est_d_3_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_D_0_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_D_1_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF SM_AMIGA_D_2_.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF IPL_030DFFSH_0_reg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_AS_000_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_AS_000_INTreg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_VPA_SYNC.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_VPA_SYNC.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_AS_030_000_SYNC.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_VMA_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_VMA_INTreg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF BG_000DFFSHreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF BG_000DFFSHreg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF DSACK_INT_1_.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF DSACK_INT_1_.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_BGACK_030_INTreg.AP
|
|
0 1
|
|
1 0
|
|
.names inst_CLK_OUT_PRE.BLIF CLK_CNT_0_.BLIF inst_CLK_OUT_PRE.D
|
|
10 1
|
|
01 1
|
|
00 0
|
|
11 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_UDS_000_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_UDS_000_INTreg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_LDS_000_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_LDS_000_INTreg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_DTACK_SYNC.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_DTACK_SYNC.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_FPU_CS_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_FPU_CS_INTreg.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_DTACK_DMA.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF inst_DTACK_DMA.AP
|
|
0 1
|
|
1 0
|
|
.names CLK_OSZI.BLIF inst_RISING_CLK_AMIGA.C
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF CLK_CNT_0_.C
|
|
1 1
|
|
0 0
|
|
.names VPA.BLIF inst_VPA_D.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_VPA_D.C
|
|
1 1
|
|
0 0
|
|
.names CLK_000.BLIF inst_CLK_000_D.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_D.C
|
|
1 1
|
|
0 0
|
|
.names RST.BLIF RESETDFFreg.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF RESETDFFreg.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_000_D.BLIF inst_CLK_000_DD.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_000_DD.C
|
|
1 1
|
|
0 0
|
|
.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_INTreg.D
|
|
1 1
|
|
0 0
|
|
.names CLK_OSZI.BLIF inst_CLK_OUT_INTreg.C
|
|
1 1
|
|
0 0
|
|
.names DSACK_INT_1_.BLIF DSACK_1_
|
|
1 1
|
|
0 0
|
|
.names inst_DTACK_DMA.BLIF DTACK
|
|
1 1
|
|
0 0
|
|
.names DSACK_0_
|
|
1
|
|
.names CPU_SPACE.BLIF DSACK_1_.OE
|
|
0 1
|
|
1 0
|
|
.names inst_BGACK_030_INTreg.BLIF DTACK.OE
|
|
0 1
|
|
1 0
|
|
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
|
|
1 1
|
|
0 0
|
|
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
|
|
1 1
|
|
0 0
|
|
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
|
|
1 1
|
|
0 0
|
|
.names inst_FPU_CS_INTreg.BLIF BERR.OE
|
|
0 1
|
|
1 0
|
|
.names CPU_SPACE.BLIF DSACK_0_.OE
|
|
0 1
|
|
1 0
|
|
.names inst_FPU_CS_INTreg.BLIF AVEC_EXP.OE
|
|
0 1
|
|
1 0
|
|
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
|
|
A_25_.BLIF A_24_.BLIF CIIN.OE
|
|
00000000 1
|
|
------1- 0
|
|
-----1-- 0
|
|
----1--- 0
|
|
---1---- 0
|
|
--1----- 0
|
|
-1------ 0
|
|
1------- 0
|
|
-------1 0
|
|
.names SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF SM_AMIGA_D_1_.BLIF \
|
|
SM_AMIGA_D_2_.BLIF CLK_EXP.X1
|
|
1111 1
|
|
0--- 0
|
|
-0-- 0
|
|
--0- 0
|
|
---0 0
|
|
.names SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
|
|
SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_D_0_.BLIF \
|
|
SM_AMIGA_D_1_.BLIF SM_AMIGA_D_2_.BLIF CLK_EXP.X2
|
|
0-0--0-1-- 1
|
|
-00-0---1- 1
|
|
-0-0-0---1 1
|
|
----1---0- 1
|
|
---1-----0 1
|
|
1------0-- 1
|
|
-----1-0-- 1
|
|
-----1---0 1
|
|
--1----0-- 1
|
|
--1-----0- 1
|
|
-1------0- 1
|
|
-1-------0 1
|
|
------1--- 1
|
|
11----0111 0
|
|
-11---0111 0
|
|
--11--0111 0
|
|
-1---10111 0
|
|
--1--10111 0
|
|
----110111 0
|
|
1--11-0111 0
|
|
010--00011 0
|
|
-00-010101 0
|
|
-010-00110 0
|
|
0-01100011 0
|
|
10010-0101 0
|
|
10-0100110 0
|
|
0001000001 0
|
|
0000100010 0
|
|
1000000100 0
|
|
0000000000 0
|
|
.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_3_reg.D.X1
|
|
11 1
|
|
0- 0
|
|
-0 0
|
|
.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \
|
|
inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_3_reg.D.X2
|
|
10---- 1
|
|
-00100 1
|
|
011100 1
|
|
1-1101 1
|
|
-10--- 0
|
|
0--0-- 0
|
|
-1-0-- 0
|
|
0---1- 0
|
|
-1--1- 0
|
|
0----1 0
|
|
001--- 0
|
|
11---0 0
|
|
.names inst_VMA_INTreg.BLIF inst_CLK_000_D.BLIF inst_VMA_INTreg.D.X1
|
|
10 1
|
|
0- 0
|
|
-1 0
|
|
.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
|
cpu_est_d_0_.BLIF cpu_est_d_3_.BLIF inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF \
|
|
inst_CLK_000_D.BLIF cpu_est_d_1_.BLIF cpu_est_d_2_.BLIF cpu_est_2_.BLIF \
|
|
inst_VMA_INTreg.D.X2
|
|
0110---0---1 1
|
|
-1------1--- 1
|
|
----001-111- 1
|
|
-0--1------- 0
|
|
-0---1------ 0
|
|
-0----0----- 0
|
|
1-------0--- 0
|
|
-0------0--- 0
|
|
--0-----0--- 0
|
|
---1----0--- 0
|
|
-------10--- 0
|
|
-0-------0-- 0
|
|
-0--------0- 0
|
|
--------0--0 0
|
|
.end
|