68030tk/Logic/68030_tk.bl3
2014-05-24 15:17:08 +02:00

756 lines
16 KiB
Plaintext

#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Sat May 24 11:44:09 2014
#$ MODULE 68030_tk
#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 \
# LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 SIZE_0_ \
# CLK_OSZI A_30_ CLK_DIV_OUT A_29_ CLK_EXP A_28_ FPU_CS A_27_ DTACK A_26_ AVEC A_25_ \
# AVEC_EXP A_24_ E A_23_ VPA A_22_ VMA A_21_ RST A_20_ RESET A_19_ RW A_18_ AMIGA_BUS_ENABLE \
# A_17_ AMIGA_BUS_DATA_DIR A_16_ AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_030_1_ IPL_030_0_ \
# IPL_1_ IPL_0_ DSACK_0_ FC_0_
#$ NODES 41 inst_BGACK_030_INTreg inst_FPU_CS_INTreg cpu_est_3_reg \
# inst_VMA_INTreg cpu_est_0_ CLK_OUT_INTreg cpu_est_1_ inst_AS_000_INTreg \
# inst_AS_030_000_SYNC IPL_030DFFSH_0_reg inst_DTACK_SYNC inst_VPA_D \
# IPL_030DFFSH_1_reg inst_VPA_SYNC inst_CLK_000_D0 IPL_030DFFSH_2_reg \
# inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D5 inst_CLK_OUT_PRE SM_AMIGA_6_ \
# SM_AMIGA_5_ cpu_est_2_ CLK_REF_1_ inst_UDS_000_INTreg inst_LDS_000_INTreg \
# DSACK_INT_1_ SM_AMIGA_7_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D4 RESETDFFreg \
# inst_DTACK_DMA CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_1_ SM_AMIGA_2_ \
# AMIGA_BUS_ENABLEDFFreg SM_AMIGA_0_ BG_000DFFSHreg
.model bus68030
.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \
nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \
A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \
A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \
IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF \
cpu_est_0_.BLIF CLK_OUT_INTreg.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF \
inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF inst_DTACK_SYNC.BLIF \
inst_VPA_D.BLIF IPL_030DFFSH_1_reg.BLIF inst_VPA_SYNC.BLIF \
inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D1.BLIF \
inst_CLK_000_D2.BLIF inst_CLK_000_D5.BLIF inst_CLK_OUT_PRE.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF cpu_est_2_.BLIF CLK_REF_1_.BLIF \
inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF \
SM_AMIGA_7_.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF inst_CLK_000_D4.BLIF \
RESETDFFreg.BLIF inst_DTACK_DMA.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \
SM_AMIGA_3_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF \
SM_AMIGA_0_.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \
CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ IPL_030DFFSH_0_reg.D \
IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \
IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \
IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \
SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \
SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \
SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \
SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \
SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D \
CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \
cpu_est_2_.C cpu_est_3_reg.C inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \
inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \
inst_LDS_000_INTreg.AP inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D \
BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_CLK_OUT_PRE.C inst_BGACK_030_INTreg.D \
inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D \
inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_AS_030_000_SYNC.D \
inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D \
inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \
inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP \
inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP AMIGA_BUS_ENABLEDFFreg.D \
AMIGA_BUS_ENABLEDFFreg.C inst_CLK_000_D5.D inst_CLK_000_D5.C inst_DTACK_DMA.D \
inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D2.D inst_CLK_000_D2.C \
inst_CLK_000_D3.D inst_CLK_000_D3.C inst_VPA_D.D inst_VPA_D.C \
inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C \
inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR \
DSACK_1_ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE \
BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 \
inst_VMA_INTreg.D.X1 inst_VMA_INTreg.D.X2 inst_CLK_OUT_PRE.D.X1 \
inst_CLK_OUT_PRE.D.X2
.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF IPL_030DFFSH_0_reg.D
1-10 1
-10- 1
-1-1 1
0-10 0
-00- 0
-0-1 0
.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF IPL_030DFFSH_1_reg.D
1-10 1
-10- 1
-1-1 1
0-10 0
-00- 0
-0-1 0
.names IPL_2_.BLIF inst_CLK_000_D0.BLIF IPL_030DFFSH_2_reg.BLIF \
inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.D
11-0 1
-01- 1
--11 1
01-0 0
-00- 0
--01 0
.names nEXP_SPACE.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF \
inst_CLK_000_D3.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.D
0--0-1--- 1
-1-1----1 1
------10- 1
----1-1-- 1
--1---1-- 1
-0010--1- 0
--0000-1- 0
1-000--1- 0
--010--10 0
-0-1--0-- 0
---0-00-- 0
1--0--0-- 0
---1--0-0 0
.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF inst_CLK_000_D3.BLIF \
SM_AMIGA_6_.D
-0-0-11 1
1-0-10- 1
---1-1- 0
-1---1- 0
----00- 0
--1--0- 0
0----0- 0
-----10 0
.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D
11- 1
1-1 1
-00 0
0-- 0
.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_4_.D
01- 1
0-1 1
-00 0
1-- 0
.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \
SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D
--11- 1
11--1 1
--1-1 1
-00-- 0
0-0-- 0
---00 0
--0-0 0
.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \
SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_2_.D
-001- 1
0-01- 1
--0-1 1
11--0 0
--1-- 0
---00 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D5.BLIF inst_CLK_000_D4.BLIF \
SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D
-011- 1
1--1- 1
1---1 1
0-0-- 0
01--- 0
0--0- 0
---00 0
.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D5.BLIF \
inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D
-0-01- 1
-01-1- 1
0----1 1
-0---1 1
11---- 0
--01-0 0
----00 0
-1---0 0
.names CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF CLK_CNT_0_.D
100 1
001 1
0-0 0
1-1 0
-1- 0
.names CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF CLK_CNT_1_.D
001 1
-10 1
1-1 0
-00 0
-11 0
.names cpu_est_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.D
010 1
10- 1
1-1 1
110 0
00- 0
0-1 0
.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_1_.D
0--100 1
01010- 1
10-10- 1
-01--- 1
1-1--1 1
--1-1- 1
--10-- 1
011101 0
11-100 0
000--1 0
110--- 0
--0-1- 0
--00-- 0
.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_2_.D
-0010- 1
11-10- 1
--1--1 1
----11 1
---0-1 1
0-1--0 0
01010- 0
-01--0 0
----10 0
---0-0 0
.names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF SM_AMIGA_5_.BLIF \
inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D
-0111-- 1
--1-01- 1
-001--1 1
--0--10 1
-1---1- 1
1-1-0-- 1
1-0---0 1
11----- 1
-0101-- 0
0-1-00- 0
-000--1 0
0-0--00 0
01---0- 0
.names SIZE_1_.BLIF AS_030.BLIF DS_030.BLIF RW.BLIF SIZE_0_.BLIF A_0_.BLIF \
SM_AMIGA_5_.BLIF inst_LDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \
inst_LDS_000_INTreg.D
0-01101-- 1
0-0010--1 1
---1--01- 1
-1-1--0-- 1
---0---10 1
-1-0----0 1
--1----1- 1
-11------ 1
-0-1--00- 0
-01----0- 0
--01-11-- 0
--010-1-- 0
1-01--1-- 0
-0-0---00 0
--00-1--1 0
--000---1 0
1-00----1 0
.names AS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF CLK_030.BLIF SM_AMIGA_7_.BLIF \
BG_000DFFSHreg.BLIF BG_000DFFSHreg.D
---1-1 1
---00- 1
-1-0-- 1
0--0-- 1
--1--- 1
10001- 0
--01-0 0
.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D
1-10 1
11-- 1
-00- 0
0--- 0
-0-1 0
.names AS_030.BLIF inst_AS_000_INTreg.BLIF SM_AMIGA_5_.BLIF \
inst_AS_000_INTreg.D
-10 1
1-0 1
00- 0
--1 0
.names FC_1_.BLIF AS_030.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \
A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \
inst_AS_030_000_SYNC.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_6_.BLIF \
SM_AMIGA_7_.BLIF inst_CLK_000_D4.BLIF SM_AMIGA_1_.BLIF inst_AS_030_000_SYNC.D
1--1-001011----- 1
-----------0--11 1
--0---------1--- 1
----------1--0-- 1
----0-----1----- 1
--0-------1----- 1
-1-------------- 1
-0--------0-0-0- 0
-0--------010--- 0
-01-1----0---10- 0
-01-1---1----10- 0
-01-1--0-----10- 0
-01-1-1------10- 0
-01-11-------10- 0
-0101--------10- 0
001-1--------10- 0
-01-1----0-1-1-- 0
-01-1---1--1-1-- 0
-01-1--0---1-1-- 0
-01-1-1----1-1-- 0
-01-11-----1-1-- 0
-0101------1-1-- 0
001-1------1-1-- 0
-0--------0-0--0 0
-01-1----0---1-0 0
-01-1---1----1-0 0
-01-1--0-----1-0 0
-01-1-1------1-0 0
-01-11-------1-0 0
-0101--------1-0 0
001-1--------1-0 0
-01-------0---0- 0
-01-------01---- 0
-01-------0----0 0
.names AS_030.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \
SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D
-1--0- 1
-1-0-- 1
-10--- 1
-1---1 1
1---0- 1
1--0-- 1
1-0--- 1
1----1 1
--1110 0
00---- 0
.names FC_1_.BLIF AS_030.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \
A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF \
inst_FPU_CS_INTreg.D
-1-------- 1
--------01 1
-------1-1 1
------0--1 1
-----1---1 1
----1----1 1
---0-----1 1
--0------1 1
0--------1 1
101100101- 0
-0-------0 0
.names AS_030.BLIF inst_CLK_000_D5.BLIF DSACK_INT_1_.BLIF inst_CLK_000_D4.BLIF \
SM_AMIGA_1_.BLIF DSACK_INT_1_.D
--10- 1
-11-- 1
--1-0 1
1--0- 1
11--- 1
1---0 1
-0-11 0
0-0-- 0
.names AS_030.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \
cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \
cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D
------1-0- 1
------10-- 1
-----11--- 1
----1-1--- 1
---1--1--- 1
--1---1--- 1
-0----1--- 1
------1--0 1
1-------0- 1
1------0-- 1
1----1---- 1
1---1----- 1
1--1------ 1
1-1------- 1
10-------- 1
1--------0 1
-10000-111 0
0-----0--- 0
.names AS_030.BLIF nEXP_SPACE.BLIF RST.BLIF SM_AMIGA_6_.BLIF \
AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D
1-10- 1
-011- 1
---01 1
--0-1 1
-111- 0
0--00 0
--0-0 0
.names inst_AS_000_INTreg.BLIF DSACK_1_.PIN.BLIF inst_DTACK_DMA.D
1- 1
-1 1
00 0
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
1 1
0 0
.names inst_AS_000_INTreg.BLIF AS_000
1 1
0 0
.names inst_UDS_000_INTreg.BLIF UDS_000
1 1
0 0
.names inst_LDS_000_INTreg.BLIF LDS_000
1 1
0 0
.names BERR
0
.names BG_000DFFSHreg.BLIF BG_000
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF BGACK_030
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_EXP
1 1
0 0
.names inst_FPU_CS_INTreg.BLIF FPU_CS
1 1
0 0
.names AVEC
1
.names AVEC_EXP
0
.names cpu_est_3_reg.BLIF E
1 1
0 0
.names inst_VMA_INTreg.BLIF VMA
1 1
0 0
.names RESETDFFreg.BLIF RESET
1 1
0 0
.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE
1 1
0 0
.names RW.BLIF AMIGA_BUS_DATA_DIR
0 1
1 0
.names AMIGA_BUS_ENABLE_LOW
1
.names A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF CIIN
1111 1
--0- 0
-0-- 0
0--- 0
---0 0
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
1 1
0 0
.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
1 1
0 0
.names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C
1 1
0 0
.names RST.BLIF IPL_030DFFSH_0_reg.AP
0 1
1 0
.names CLK_OSZI.BLIF IPL_030DFFSH_1_reg.C
1 1
0 0
.names RST.BLIF IPL_030DFFSH_1_reg.AP
0 1
1 0
.names CLK_OSZI.BLIF IPL_030DFFSH_2_reg.C
1 1
0 0
.names RST.BLIF IPL_030DFFSH_2_reg.AP
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_7_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_7_.AP
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_6_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_5_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_4_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_4_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_3_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_3_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_2_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_2_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_1_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_1_.AR
0 1
1 0
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
1 1
0 0
.names RST.BLIF SM_AMIGA_0_.AR
0 1
1 0
.names CLK_OSZI.BLIF CLK_CNT_0_.C
1 1
0 0
.names CLK_OSZI.BLIF CLK_CNT_1_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_0_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_1_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_2_.C
1 1
0 0
.names CLK_OSZI.BLIF cpu_est_3_reg.C
1 1
0 0
.names CLK_OSZI.BLIF inst_UDS_000_INTreg.C
1 1
0 0
.names RST.BLIF inst_UDS_000_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_LDS_000_INTreg.C
1 1
0 0
.names RST.BLIF inst_LDS_000_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_VMA_INTreg.C
1 1
0 0
.names RST.BLIF inst_VMA_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF BG_000DFFSHreg.C
1 1
0 0
.names RST.BLIF BG_000DFFSHreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C
1 1
0 0
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names RST.BLIF inst_BGACK_030_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_AS_000_INTreg.C
1 1
0 0
.names RST.BLIF inst_AS_000_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names RST.BLIF inst_AS_030_000_SYNC.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_DTACK_SYNC.C
1 1
0 0
.names RST.BLIF inst_DTACK_SYNC.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_FPU_CS_INTreg.C
1 1
0 0
.names RST.BLIF inst_FPU_CS_INTreg.AP
0 1
1 0
.names CLK_OSZI.BLIF DSACK_INT_1_.C
1 1
0 0
.names RST.BLIF DSACK_INT_1_.AP
0 1
1 0
.names CLK_OSZI.BLIF inst_VPA_SYNC.C
1 1
0 0
.names RST.BLIF inst_VPA_SYNC.AP
0 1
1 0
.names CLK_OSZI.BLIF AMIGA_BUS_ENABLEDFFreg.C
1 1
0 0
.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D5.C
1 1
0 0
.names CLK_OSZI.BLIF inst_DTACK_DMA.C
1 1
0 0
.names RST.BLIF inst_DTACK_DMA.AP
0 1
1 0
.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D
1 1
0 0
.names CLK_OSZI.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D4.C
1 1
0 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D2.C
1 1
0 0
.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D3.C
1 1
0 0
.names VPA.BLIF inst_VPA_D.D
1 1
0 0
.names CLK_OSZI.BLIF inst_VPA_D.C
1 1
0 0
.names CLK_000.BLIF inst_CLK_000_D0.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D0.C
1 1
0 0
.names RST.BLIF RESETDFFreg.D
1 1
0 0
.names CLK_OSZI.BLIF RESETDFFreg.C
1 1
0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
.names CLK_OSZI.BLIF inst_CLK_000_D1.C
1 1
0 0
.names CLK_REF_1_.D
0
.names CLK_REF_1_.LH
0
.names RST.BLIF CLK_REF_1_.AR
0 1
1 0
.names DSACK_INT_1_.BLIF DSACK_1_
1 1
0 0
.names inst_DTACK_DMA.BLIF DTACK
1 1
0 0
.names DSACK_0_
1
.names nEXP_SPACE.BLIF DSACK_1_.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF DTACK.OE
0 1
1 0
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
1 1
0 0
.names inst_FPU_CS_INTreg.BLIF BERR.OE
0 1
1 0
.names nEXP_SPACE.BLIF DSACK_0_.OE
1 1
0 0
.names inst_FPU_CS_INTreg.BLIF AVEC_EXP.OE
0 1
1 0
.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
A_25_.BLIF A_24_.BLIF CIIN.OE
00000000 1
------1- 0
-----1-- 0
----1--- 0
---1---- 0
--1----- 0
-1------ 0
1------- 0
-------1 0
.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_3_reg.D.X1
11 1
0- 0
-0 0
.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \
inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_3_reg.D.X2
10---- 1
-00100 1
011100 1
1-1101 1
-10--- 0
0--0-- 0
-1-0-- 0
0---1- 0
-1--1- 0
0----1 0
001--- 0
11---0 0
.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF inst_VMA_INTreg.D.X1
01 1
1- 0
-0 0
.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF cpu_est_2_.BLIF \
inst_VMA_INTreg.D.X2
00011-11 1
-110-001 1
11------ 1
10------ 0
-01----- 0
-0-0---- 0
-0--0--- 0
-0----0- 0
0------0 0
-0-----0 0
010----- 0
01-1---- 0
01---1-- 0
01----1- 0
.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE.D.X1
1 1
0 0
.names inst_CLK_OUT_PRE.BLIF CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \
inst_CLK_OUT_PRE.D.X2
-000 1
-101 1
--1- 0
-0-1 0
-1-0 0
.end