68030tk/Logic/synwork/BUS68030_compiler.tlg
2014-05-24 15:17:08 +02:00

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@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:7:112:15|Signal clk_030_d is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Pruning register cpu_est_d(3 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":118:32:118:34|Pruning register CLK_000_D6
@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization
@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement.
@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1
@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0)
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":119:32:119:34|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
001
010
011
100
101
110
111
@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":185:2:185:3|Initial value is not supported on state machine SM_AMIGA