mirror of https://github.com/kr239/68030tk.git
46 lines
1.8 KiB
Plaintext
46 lines
1.8 KiB
Plaintext
Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
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Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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Product Version G-2012.09LC-SP1
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@N: MF248 |Running in 64-bit mode.
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Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
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original code -> new code
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000 -> 00000001
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001 -> 00000010
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010 -> 00000100
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011 -> 00001000
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100 -> 00010000
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101 -> 00100000
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110 -> 01000000
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111 -> 10000000
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@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":218:4:218:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
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@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
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@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
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---------------------------------------
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Resource Usage Report
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Simple gate primitives:
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DFFRH 17 uses
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DFF 33 uses
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DFFSH 28 uses
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BI_DIR 11 uses
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IBUF 32 uses
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OBUF 16 uses
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BUFTH 2 uses
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AND2 241 uses
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INV 181 uses
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DLATRH 1 use
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XOR2 10 uses
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OR2 28 uses
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@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
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G-2012.09LC-SP1
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Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Fri Feb 13 14:39:11 2015
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###########################################################]
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