mirror of https://github.com/kr239/68030tk.git
136 lines
3.9 KiB
Modula-2
136 lines
3.9 KiB
Modula-2
MODEL
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MODEL_VERSION "1.0";
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DESIGN "68030_tk";
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DATE "Sun Feb 01 21:13:56 2015";
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VENDOR "Lattice Semiconductor Corporation";
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PROGRAM "STAMP Model Generator";
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/* port name and type */
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INPUT A1;
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INPUT A_16;
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INPUT A_17;
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INPUT A_18;
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INPUT A_19;
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INPUT A_20;
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INPUT A_21;
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INPUT A_22;
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INPUT A_23;
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INPUT A_24;
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INPUT A_25;
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INPUT A_26;
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INPUT A_27;
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INPUT A_28;
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INPUT A_29;
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INPUT A_30;
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INPUT A_31;
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INPUT BGACK_000;
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INPUT BG_030;
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INPUT CLK_000;
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INPUT CLK_030;
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INPUT CLK_OSZI;
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INPUT DTACK;
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INPUT FC_0;
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INPUT FC_1;
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INPUT FPU_SENSE;
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INPUT IPL_0;
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INPUT IPL_1;
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INPUT IPL_2;
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INPUT RST;
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INPUT VPA;
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INPUT nEXP_SPACE;
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OUTPUT AMIGA_ADDR_ENABLE;
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OUTPUT AMIGA_BUS_DATA_DIR;
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OUTPUT AMIGA_BUS_ENABLE_HIGH;
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OUTPUT AMIGA_BUS_ENABLE_LOW;
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OUTPUT AVEC;
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OUTPUT BGACK_030;
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OUTPUT BG_000;
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OUTPUT CIIN;
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OUTPUT CLK_DIV_OUT;
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OUTPUT CLK_EXP;
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OUTPUT DSACK1;
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OUTPUT E;
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OUTPUT FPU_CS;
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OUTPUT IPL_030_0;
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OUTPUT IPL_030_1;
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OUTPUT IPL_030_2;
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OUTPUT RESET;
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OUTPUT VMA;
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INOUT A0;
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INOUT AS_000;
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INOUT AS_030;
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INOUT BERR;
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INOUT DS_030;
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INOUT LDS_000;
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INOUT RW;
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INOUT RW_000;
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INOUT SIZE_0;
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INOUT SIZE_1;
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INOUT UDS_000;
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/* timing arc definitions */
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AS_030_AS_000_delay: DELAY AS_030 AS_000;
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A_20_CIIN_delay: DELAY A_20 CIIN;
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A_21_CIIN_delay: DELAY A_21 CIIN;
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A_22_CIIN_delay: DELAY A_22 CIIN;
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A_23_CIIN_delay: DELAY A_23 CIIN;
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A_24_CIIN_delay: DELAY A_24 CIIN;
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A_25_CIIN_delay: DELAY A_25 CIIN;
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A_26_CIIN_delay: DELAY A_26 CIIN;
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A_27_CIIN_delay: DELAY A_27 CIIN;
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A_28_CIIN_delay: DELAY A_28 CIIN;
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A_29_CIIN_delay: DELAY A_29 CIIN;
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A_30_CIIN_delay: DELAY A_30 CIIN;
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A_31_CIIN_delay: DELAY A_31 CIIN;
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DS_030_LDS_000_delay: DELAY DS_030 LDS_000;
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DS_030_UDS_000_delay: DELAY DS_030 UDS_000;
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AS_000_AMIGA_BUS_DATA_DIR_delay: DELAY AS_000 AMIGA_BUS_DATA_DIR;
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AS_030_FPU_CS_delay: DELAY AS_030 FPU_CS;
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A_16_FPU_CS_delay: DELAY A_16 FPU_CS;
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A_17_FPU_CS_delay: DELAY A_17 FPU_CS;
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A_18_FPU_CS_delay: DELAY A_18 FPU_CS;
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A_19_FPU_CS_delay: DELAY A_19 FPU_CS;
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BGACK_000_FPU_CS_delay: DELAY BGACK_000 FPU_CS;
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FC_0_FPU_CS_delay: DELAY FC_0 FPU_CS;
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FC_1_FPU_CS_delay: DELAY FC_1 FPU_CS;
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FPU_SENSE_FPU_CS_delay: DELAY FPU_SENSE FPU_CS;
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RW_000_AMIGA_BUS_DATA_DIR_delay: DELAY RW_000 AMIGA_BUS_DATA_DIR;
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CLK_OSZI_AS_000_delay: DELAY CLK_OSZI AS_000;
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CLK_OSZI_CIIN_delay: DELAY CLK_OSZI CIIN;
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CLK_OSZI_LDS_000_delay: DELAY CLK_OSZI LDS_000;
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CLK_OSZI_LDS_000_delay: DELAY CLK_OSZI LDS_000;
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CLK_OSZI_SIZE_0_delay: DELAY CLK_OSZI SIZE_0;
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CLK_OSZI_SIZE_0_delay: DELAY CLK_OSZI SIZE_0;
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CLK_OSZI_SIZE_1_delay: DELAY CLK_OSZI SIZE_1;
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CLK_OSZI_SIZE_1_delay: DELAY CLK_OSZI SIZE_1;
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CLK_OSZI_UDS_000_delay: DELAY CLK_OSZI UDS_000;
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CLK_OSZI_UDS_000_delay: DELAY CLK_OSZI UDS_000;
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CLK_OSZI_AMIGA_BUS_DATA_DIR_delay: DELAY CLK_OSZI AMIGA_BUS_DATA_DIR;
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CLK_OSZI_AMIGA_BUS_DATA_DIR_delay: DELAY CLK_OSZI AMIGA_BUS_DATA_DIR;
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CLK_OSZI_AMIGA_BUS_ENABLE_HIGH_delay: DELAY CLK_OSZI AMIGA_BUS_ENABLE_HIGH;
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CLK_OSZI_AMIGA_BUS_ENABLE_HIGH_delay: DELAY CLK_OSZI AMIGA_BUS_ENABLE_HIGH;
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CLK_OSZI_AMIGA_BUS_ENABLE_HIGH_delay: DELAY CLK_OSZI AMIGA_BUS_ENABLE_HIGH;
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CLK_OSZI_AMIGA_BUS_ENABLE_LOW_delay: DELAY CLK_OSZI AMIGA_BUS_ENABLE_LOW;
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CLK_OSZI_AMIGA_BUS_ENABLE_LOW_delay: DELAY CLK_OSZI AMIGA_BUS_ENABLE_LOW;
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CLK_OSZI_CLK_DIV_OUT_delay: DELAY CLK_OSZI CLK_DIV_OUT;
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CLK_OSZI_CLK_EXP_delay: DELAY CLK_OSZI CLK_EXP;
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CLK_OSZI_A0_delay: DELAY CLK_OSZI A0;
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CLK_OSZI_AS_030_delay: DELAY CLK_OSZI AS_030;
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CLK_OSZI_BGACK_030_delay: DELAY CLK_OSZI BGACK_030;
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CLK_OSZI_BG_000_delay: DELAY CLK_OSZI BG_000;
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CLK_OSZI_DSACK1_delay: DELAY CLK_OSZI DSACK1;
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CLK_OSZI_DS_030_delay: DELAY CLK_OSZI DS_030;
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CLK_OSZI_E_delay: DELAY CLK_OSZI E;
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CLK_OSZI_IPL_030_0_delay: DELAY CLK_OSZI IPL_030_0;
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CLK_OSZI_IPL_030_1_delay: DELAY CLK_OSZI IPL_030_1;
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CLK_OSZI_IPL_030_2_delay: DELAY CLK_OSZI IPL_030_2;
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CLK_OSZI_RESET_delay: DELAY CLK_OSZI RESET;
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CLK_OSZI_RW_delay: DELAY CLK_OSZI RW;
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CLK_OSZI_RW_000_delay: DELAY CLK_OSZI RW_000;
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CLK_OSZI_VMA_delay: DELAY CLK_OSZI VMA;
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CLK_OSZI_AMIGA_ADDR_ENABLE_delay: DELAY CLK_OSZI AMIGA_ADDR_ENABLE;
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/* timing check arc definitions */
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ENDMODEL
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