mirror of https://github.com/kr239/68030tk.git
1938 lines
76 KiB
Plaintext
1938 lines
76 KiB
Plaintext
|--------------------------------------------|
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|- ispLEVER Fitter Report File -|
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|- Version 1.7.00.05.28.13 -|
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|- (c)Copyright, Lattice Semiconductor 2002 -|
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|--------------------------------------------|
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Project_Summary
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~~~~~~~~~~~~~~~
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Project Name : 68030_tk
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Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
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Project Fitted on : Mon Jun 09 20:20:36 2014
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Device : M4A5-128/64
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Package : 100TQFP
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Speed : -10
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Partnumber : M4A5-128/64-10VC
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Source Format : Pure_VHDL
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// Project '68030_tk' was Fitted Successfully! //
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Compilation_Times
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~~~~~~~~~~~~~~~~~
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Reading/DRC 0 sec
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Partition 0 sec
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Place 0 sec
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Route 0 sec
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Jedec/Report generation 0 sec
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--------
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Fitter 00:00:00
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Design_Summary
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~~~~~~~~~~~~~~
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Total Input Pins : 30
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Total Output Pins : 17
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Total Bidir I/O Pins : 12
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Total Flip-Flops : 76
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Total Product Terms : 173
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Total Reserved Pins : 0
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Total Reserved Blocks : 0
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Device_Resource_Summary
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~~~~~~~~~~~~~~~~~~~~~~~
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Total
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Available Used Available Utilization
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Dedicated Pins
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Input-Only Pins 2 2 0 --> 100%
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Clock/Input Pins 4 4 0 --> 100%
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I/O Pins 64 53 11 --> 82%
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Logic Macrocells 128 85 43 --> 66%
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Input Registers 64 0 64 --> 0%
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Unusable Macrocells .. 0 ..
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CSM Outputs/Total Block Inputs 264 192 72 --> 72%
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Logical Product Terms 640 174 466 --> 27%
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Product Term Clusters 128 45 83 --> 35%
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Blocks_Resource_Summary
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~~~~~~~~~~~~~~~~~~~~~~~
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# of PT
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I/O Inp Macrocells Macrocells logic clusters
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Fanin Pins Reg Used Unusable available PTs available Pwr
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---------------------------------------------------------------------------------
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Maximum 33 8 8 -- -- 16 80 16 -
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---------------------------------------------------------------------------------
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Block A 24 7 0 11 0 5 22 12 Hi
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Block B 20 8 0 11 0 5 16 12 Hi
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Block C 19 8 0 11 0 5 15 13 Hi
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Block D 31 8 0 11 0 5 24 9 Hi
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Block E 27 3 0 9 0 7 16 11 Hi
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Block F 22 4 0 10 0 6 36 5 Hi
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Block G 21 7 0 11 0 5 21 13 Hi
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Block H 28 8 0 11 0 5 24 9 Hi
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---------------------------------------------------------------------------------
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<Note> Four rightmost columns above reflect last status of the placement process.
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<Note> Pwr (Power) : Hi = High
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Lo = Low.
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Optimizer_and_Fitter_Options
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Pin Assignment : Yes
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Group Assignment : No
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Pin Reservation : No (1)
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Block Reservation : No
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@Ignore_Project_Constraints :
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Pin Assignments : No
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Keep Block Assignment --
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Keep Segment Assignment --
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Group Assignments : No
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Macrocell Assignment : No
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Keep Block Assignment --
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Keep Segment Assignment --
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@Backannotate_Project_Constraints
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Pin Assignments : No
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Pin And Block Assignments : No
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Pin, Macrocell and Block : No
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@Timing_Constraints : No
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@Global_Project_Optimization :
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Balanced Partitioning : Yes
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Spread Placement : Yes
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Note :
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Pack Design :
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Balanced Partitioning = No
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Spread Placement = No
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Spread Design :
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Balanced Partitioning = Yes
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Spread Placement = Yes
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@Logic_Synthesis :
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Logic Reduction : Yes
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Node Collapsing : Yes
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D/T Synthesis : Yes
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Clock Optimization : No
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Input Register Optimization : Yes
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XOR Synthesis : Yes
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Max. P-Term for Collapsing : 16
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Max. P-Term for Splitting : 16
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Max. Equation Fanin : 32
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Keep Xor : Yes
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@Utilization_options
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Max. % of macrocells used : 100
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Max. % of block inputs used : 100
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Max. % of segment lines used : ---
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Max. % of macrocells used : ---
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@Import_Source_Constraint_Option No
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@Zero_Hold_Time Yes
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@Pull_up Yes
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@User_Signature #H0
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@Output_Slew_Rate Default = Slow(2)
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@Power Default = High(2)
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Device Options:
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<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
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follow the drive level set for the Global Configure Unused I/O Option.
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<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
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Bidir and Burried Signal Lists.
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Pinout_Listing
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~~~~~~~~~~~~~~
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| Pin |Blk |Assigned|
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Pin No| Type |Pad |Pin | Signal name
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---------------------------------------------------------------
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1 | GND | | |
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2 | JTAG | | |
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3 | I_O | B7 | * |RESET
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4 | I_O | B6 | * |A_31_
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5 | I_O | B5 | * |A_30_
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6 | I_O | B4 | * |A_29_
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7 | I_O | B3 | * |IPL_030_1_
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8 | I_O | B2 | * |IPL_030_0_
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9 | I_O | B1 | * |IPL_030_2_
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10 | I_O | B0 | * |CLK_EXP
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11 | CkIn | | * |CLK_000
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12 | Vcc | | |
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13 | GND | | |
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14 | CkIn | | * |nEXP_SPACE
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15 | I_O | C0 | * |A_28_
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16 | I_O | C1 | * |A_27_
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17 | I_O | C2 | * |A_26_
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18 | I_O | C3 | * |A_25_
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19 | I_O | C4 | * |A_24_
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20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW
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21 | I_O | C6 | * |BG_030
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22 | I_O | C7 | * |AVEC_EXP
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23 | JTAG | | |
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24 | JTAG | | |
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25 | GND | | |
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26 | GND | | |
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27 | GND | | |
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28 | I_O | D7 | * |BGACK_000
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29 | I_O | D6 | * |BG_000
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30 | I_O | D5 | * |DTACK
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31 | I_O | D4 | * |LDS_000
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32 | I_O | D3 | * |UDS_000
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33 | I_O | D2 | * |AS_000
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34 | I_O | D1 | * |AMIGA_BUS_ENABLE
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35 | I_O | D0 | * |VMA
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36 | Inp | | * |VPA
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37 | Vcc | | |
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38 | GND | | |
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39 | GND | | |
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40 | Vcc | | |
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41 | I_O | E0 | * |BERR
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42 | I_O | E1 | |
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43 | I_O | E2 | |
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44 | I_O | E3 | |
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45 | I_O | E4 | |
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46 | I_O | E5 | |
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47 | I_O | E6 | * |CIIN
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48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR
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49 | GND | | |
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50 | GND | | |
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51 | GND | | |
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52 | JTAG | | |
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53 | I_O | F7 | |
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54 | I_O | F6 | |
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55 | I_O | F5 | |
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56 | I_O | F4 | * |IPL_1_
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57 | I_O | F3 | * |FC_0_
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58 | I_O | F2 | * |FC_1_
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59 | I_O | F1 | * |A_17_
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60 | I_O | F0 | |
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61 | CkIn | | * |CLK_OSZI
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62 | Vcc | | |
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63 | GND | | |
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64 | CkIn | | * |CLK_030
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65 | I_O | G0 | * |CLK_DIV_OUT
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66 | I_O | G1 | * |E
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67 | I_O | G2 | * |IPL_0_
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68 | I_O | G3 | * |IPL_2_
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69 | I_O | G4 | * |A0
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70 | I_O | G5 | * |SIZE_0_
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71 | I_O | G6 | * |RW
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72 | I_O | G7 | |
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73 | JTAG | | |
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74 | JTAG | | |
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75 | GND | | |
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76 | GND | | |
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77 | GND | | |
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78 | I_O | H7 | * |FPU_CS
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79 | I_O | H6 | * |SIZE_1_
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80 | I_O | H5 | * |RW_000
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81 | I_O | H4 | * |DSACK1
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82 | I_O | H3 | * |AS_030
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83 | I_O | H2 | * |BGACK_030
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84 | I_O | H1 | * |A_23_
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85 | I_O | H0 | * |A_22_
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86 | Inp | | * |RST
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87 | Vcc | | |
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88 | GND | | |
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89 | GND | | |
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90 | Vcc | | |
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91 | I_O | A0 | |
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92 | I_O | A1 | * |AVEC
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93 | I_O | A2 | * |A_20_
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94 | I_O | A3 | * |A_21_
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95 | I_O | A4 | * |A_18_
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96 | I_O | A5 | * |A_16_
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97 | I_O | A6 | * |A_19_
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98 | I_O | A7 | * |DS_030
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99 | GND | | |
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100 | GND | | |
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---------------------------------------------------------------------------
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<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
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<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
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<Note> Pin Type :
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CkIn : Dedicated input or clock pin
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CLK : Dedicated clock pin
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INP : Dedicated input pin
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JTAG : JTAG Control and test pin
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NC : No connected
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Input_Signal_List
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~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Input
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Pin Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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96 A . I/O ----E--H Hi Slow A_16_
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59 F . I/O ----E--H Hi Slow A_17_
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95 A . I/O ----E--H Hi Slow A_18_
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97 A . I/O ----E--H Hi Slow A_19_
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93 A . I/O ----E--- Hi Slow A_20_
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94 A . I/O ----E--- Hi Slow A_21_
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85 H . I/O ----E--- Hi Slow A_22_
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84 H . I/O ----E--- Hi Slow A_23_
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19 C . I/O ----E--- Hi Slow A_24_
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18 C . I/O ----E--- Hi Slow A_25_
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17 C . I/O ----E--- Hi Slow A_26_
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16 C . I/O ----E--- Hi Slow A_27_
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15 C . I/O ----E--- Hi Slow A_28_
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6 B . I/O ----E--- Hi Slow A_29_
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5 B . I/O ----E--- Hi Slow A_30_
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4 B . I/O ----E--- Hi Slow A_31_
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41 E . I/O AB-D-F-H Hi Slow BERR
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28 D . I/O -------H Hi Slow BGACK_000
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21 C . I/O ---D---- Hi Slow BG_030
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57 F . I/O -------H Hi Slow FC_0_
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58 F . I/O -------H Hi Slow FC_1_
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67 G . I/O -B------ Hi Slow IPL_0_
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56 F . I/O -B------ Hi Slow IPL_1_
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68 G . I/O -B------ Hi Slow IPL_2_
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11 . . Ck/I -B-D---- - Slow CLK_000
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14 . . Ck/I A--DEFGH - Slow nEXP_SPACE
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36 . . Ded -----FG- - Slow VPA
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61 . . Ck/I ABCDEFGH - Slow CLK_OSZI
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64 . . Ck/I A-----GH - Slow CLK_030
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86 . . Ded ABCDEFGH - Slow RST
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----------------------------------------------------------------------
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<Note> Power : Hi = High
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MH = Medium High
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ML = Medium Low
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Lo = Low
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Output_Signal_List
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~~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Output
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Pin Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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48 E 2 COM -------- Hi Slow AMIGA_BUS_DATA_DIR
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34 D 6 DFF * -------- Hi Slow AMIGA_BUS_ENABLE
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20 C 1 DFF * -------- Hi Slow AMIGA_BUS_ENABLE_LOW
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92 A 1 COM -------- Hi Slow AVEC
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22 C 1 DFF * -------- Hi Slow AVEC_EXP
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83 H 2 DFF * -------- Hi Slow BGACK_030
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29 D 2 DFF * -------- Hi Slow BG_000
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47 E 4 COM -------- Hi Slow CIIN
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65 G 1 DFF * -------- Hi Slow CLK_DIV_OUT
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10 B 1 DFF * -------- Hi Slow CLK_EXP
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66 G 4 DFF * -------- Hi Slow E
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78 H 1 COM -------- Hi Slow FPU_CS
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8 B 2 DFF * -------- Hi Slow IPL_030_0_
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7 B 2 DFF * -------- Hi Slow IPL_030_1_
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9 B 2 DFF * -------- Hi Slow IPL_030_2_
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3 B 1 DFF * -------- Hi Slow RESET
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35 D 2 DFF * -------- Hi Slow VMA
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----------------------------------------------------------------------
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<Note> Power : Hi = High
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MH = Medium High
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ML = Medium Low
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Lo = Low
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Bidir_Signal_List
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~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Bidir
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Pin Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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69 G 1 DFF * --C----- Hi Slow A0
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33 D 2 DFF * A---E-GH Hi Slow AS_000
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82 H 4 DFF * -B-D---H Hi Slow AS_030
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81 H 2 DFF * ---D---- Hi Slow DSACK1
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98 A 7 DFF * --C----- Hi Slow DS_030
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30 D 1 COM -----F-- Hi Slow DTACK
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31 D 1 COM A-----GH Hi Slow LDS_000
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71 G 4 DFF * -B--E--H Hi Slow RW
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80 H 3 DFF * A-----G- Hi Slow RW_000
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70 G 1 DFF * --C----- Hi Slow SIZE_0_
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79 H 2 DFF * --C----- Hi Slow SIZE_1_
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32 D 1 COM A-----GH Hi Slow UDS_000
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----------------------------------------------------------------------
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<Note> Power : Hi = High
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MH = Medium High
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ML = Medium Low
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Lo = Low
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Buried_Signal_List
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~~~~~~~~~~~~~~~~~~
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P R
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Pin r e O Node
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#Mc Blk PTs Type e s E Fanout Pwr Slew Signal
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----------------------------------------------------------------------
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A5 A 1 DFF * -----F-- Hi Slow CLK_000_N_SYNC_0_
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C5 C 1 DFF * A------- Hi Slow CLK_000_N_SYNC_10_
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A6 A 1 DFF * A------- Hi Slow CLK_000_N_SYNC_11_
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F2 F 1 DFF * ------G- Hi Slow CLK_000_N_SYNC_1_
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G9 G 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_2_
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C2 C 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_3_
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C13 C 1 DFF * -B------ Hi Slow CLK_000_N_SYNC_4_
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B2 B 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_5_
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C10 C 1 DFF * -------H Hi Slow CLK_000_N_SYNC_6_
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H6 H 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_7_
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C9 C 1 DFF * -B------ Hi Slow CLK_000_N_SYNC_8_
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B13 B 1 DFF * --C----- Hi Slow CLK_000_N_SYNC_9_
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A2 A 1 DFF * ------G- Hi Slow CLK_000_P_SYNC_0_
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G2 G 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_1_
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C6 C 1 DFF * ------G- Hi Slow CLK_000_P_SYNC_2_
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G13 G 1 DFF * A------- Hi Slow CLK_000_P_SYNC_3_
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A13 A 1 DFF * -B------ Hi Slow CLK_000_P_SYNC_4_
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B10 B 1 DFF * ----E--- Hi Slow CLK_000_P_SYNC_5_
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E5 E 1 DFF * A------- Hi Slow CLK_000_P_SYNC_6_
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A9 A 1 DFF * -B------ Hi Slow CLK_000_P_SYNC_7_
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B6 B 1 DFF * ------G- Hi Slow CLK_000_P_SYNC_8_
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G6 G 1 DFF * --C----- Hi Slow CLK_000_P_SYNC_9_
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E1 E 2 DFF * ----E--- Hi Slow CLK_CNT_N_0_
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E9 E 1 DFF * ----E--- Hi Slow CLK_CNT_N_1_
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E12 E 2 DFF * ----E--- Hi Slow CLK_CNT_P_0_
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E13 E 1 DFF * ----E--- Hi Slow CLK_CNT_P_1_
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E8 E 2 COM --C----- Hi Slow CLK_PRE_66_0
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D5 D 6 DFF * ---D---- Hi - RN_AMIGA_BUS_ENABLE --> AMIGA_BUS_ENABLE
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C12 C 1 DFF * --C----- Hi - RN_AMIGA_BUS_ENABLE_LOW --> AMIGA_BUS_ENABLE_LOW
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D4 D 2 DFF * ---D---- Hi - RN_AS_000 --> AS_000
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H8 H 4 DFF * A--D--GH Hi - RN_AS_030 --> AS_030
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C0 C 1 DFF * AB-D-FGH Hi - RN_AVEC_EXP --> AVEC_EXP
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H4 H 2 DFF * A--DE-GH Hi - RN_BGACK_030 --> BGACK_030
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D13 D 2 DFF * ---D---- Hi - RN_BG_000 --> BG_000
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H12 H 2 DFF * -------H Hi - RN_DSACK1 --> DSACK1
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A0 A 7 DFF * A------- Hi - RN_DS_030 --> DS_030
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G4 G 4 DFF * ---D-FG- Hi - RN_E --> E
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B8 B 2 DFF * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_
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B12 B 2 DFF * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_
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B4 B 2 DFF * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_
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G0 G 4 DFF * ------G- Hi - RN_RW --> RW
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H0 H 3 DFF * -------H Hi - RN_RW_000 --> RW_000
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D1 D 2 DFF * ---D-F-- Hi - RN_VMA --> VMA
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F12 F 2 DFF * ---D-F-- Hi Slow SM_AMIGA_0_
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F4 F 2 DFF * ---D-F-H Hi Slow SM_AMIGA_1_
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F9 F 3 DFF * -----F-- Hi Slow SM_AMIGA_2_
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F5 F 6 DFF * -----F-- Hi Slow SM_AMIGA_3_
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F8 F 2 DFF * -B---F-- Hi Slow SM_AMIGA_4_
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F13 F 2 DFF * -----F-- Hi Slow SM_AMIGA_5_
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A8 A 2 DFF * AB-D-F-H Hi Slow SM_AMIGA_6_
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F0 F 13 DFF * A--D---H Hi Slow SM_AMIGA_7_
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F1 F 4 COM -----F-- Hi Slow SM_AMIGA_7__0
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D6 D 2 DFF * ---D--G- Hi Slow cpu_est_0_
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G5 G 5 DFF * ---D-FG- Hi Slow cpu_est_1_
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D2 D 4 DFF * ---D--G- Hi Slow cpu_est_2_
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H9 H 6 DFF * A--D-F-H Hi Slow inst_AS_030_000_SYNC
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D10 D 1 DFF * ---D---- Hi Slow inst_BGACK_030_INT_D
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B5 B 1 DFF * A--D-F-- Hi Slow inst_CLK_000_D0
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||
D9 D 1 DFF * A--D-F-- Hi Slow inst_CLK_000_D1
|
||
F6 F 1 DFF * A------- Hi Slow inst_CLK_000_D2
|
||
A10 A 1 DFF * A------- Hi Slow inst_CLK_000_D3
|
||
A12 A 1 DFF * ---D-F-- Hi Slow inst_CLK_000_NE
|
||
A1 A 5 DFF A------- Hi Slow inst_CLK_030_H
|
||
E2 E 1 DFF * -------H Hi Slow inst_CLK_OUT_PRE
|
||
C4 C 3 DFF * --C-E--- Hi Slow inst_CLK_OUT_PRE_25
|
||
H2 H 1 DFF * --C----H Hi Slow inst_CLK_OUT_PRE_50
|
||
H10 H 1 DFF * --C----- Hi Slow inst_CLK_OUT_PRE_50_D
|
||
H13 H 1 DFF * -B----G- Hi Slow inst_CLK_OUT_PRE_D
|
||
B9 B 3 DFF * -B-D---- Hi Slow inst_DS_000_ENABLE
|
||
C1 C 2 DFF * --CD---- Hi Slow inst_LDS_000_INT
|
||
C8 C 2 DFF * --CD---- Hi Slow inst_UDS_000_INT
|
||
G10 G 1 DFF * ---D---- Hi Slow inst_VPA_D
|
||
----------------------------------------------------------------------
|
||
|
||
<Note> Power : Hi = High
|
||
MH = Medium High
|
||
ML = Medium Low
|
||
Lo = Low
|
||
|
||
|
||
|
||
|
||
Signals_Fanout_List
|
||
~~~~~~~~~~~~~~~~~~~
|
||
Signal Source : Fanout List
|
||
-----------------------------------------------------------------------------
|
||
A_31_{ C}: CIIN{ E}
|
||
IPL_2_{ H}: IPL_030_2_{ B}
|
||
FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
|
||
UDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A}
|
||
: SIZE_0_{ G} A0{ G} RW{ G}
|
||
: inst_CLK_030_H{ A}
|
||
LDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A}
|
||
: SIZE_0_{ G} A0{ G} RW{ G}
|
||
: inst_CLK_030_H{ A}
|
||
A_30_{ C}: CIIN{ E}
|
||
nEXP_SPACE{. }: DTACK{ D}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H}
|
||
: AS_030{ H} DS_030{ A} SIZE_0_{ G}
|
||
: A0{ G} BG_000{ D} DSACK1{ H}
|
||
:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_7_{ F}
|
||
: SM_AMIGA_6_{ A}
|
||
A_29_{ C}: CIIN{ E}
|
||
BERR{ F}: AS_000{ D} DSACK1{ H}inst_AS_030_000_SYNC{ H}
|
||
: SM_AMIGA_7_{ F} SM_AMIGA_1_{ F} SM_AMIGA_0_{ F}
|
||
: SM_AMIGA_6_{ A} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ B}
|
||
: SM_AMIGA_5_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
||
A_28_{ D}: CIIN{ E}
|
||
BG_030{ D}: BG_000{ D}
|
||
A_27_{ D}: CIIN{ E}
|
||
A_26_{ D}: CIIN{ E}
|
||
A_25_{ D}: CIIN{ E}
|
||
BGACK_000{ E}: FPU_CS{ H} BGACK_030{ H}inst_AS_030_000_SYNC{ H}
|
||
A_24_{ D}: CIIN{ E}
|
||
CLK_030{. }: AS_030{ H} DS_030{ A} RW{ G}
|
||
: inst_CLK_030_H{ A}
|
||
A_23_{ I}: CIIN{ E}
|
||
CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ B}
|
||
A_22_{ I}: CIIN{ E}
|
||
A_21_{ B}: CIIN{ E}
|
||
A_20_{ B}: CIIN{ E}
|
||
A_19_{ B}: FPU_CS{ H} CIIN{ E}inst_AS_030_000_SYNC{ H}
|
||
A_18_{ B}: FPU_CS{ H} CIIN{ E}inst_AS_030_000_SYNC{ H}
|
||
A_17_{ G}: FPU_CS{ H} CIIN{ E}inst_AS_030_000_SYNC{ H}
|
||
DTACK{ E}: SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
||
A_16_{ B}: FPU_CS{ H} CIIN{ E}inst_AS_030_000_SYNC{ H}
|
||
IPL_1_{ G}: IPL_030_1_{ B}
|
||
VPA{. }: inst_VPA_D{ G} SM_AMIGA_7_{ F} SM_AMIGA_3_{ F}
|
||
: SM_AMIGA_2_{ F}
|
||
IPL_0_{ H}: IPL_030_0_{ B}
|
||
FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
|
||
RST{. }: CLK_DIV_OUT{ G} SIZE_1_{ H} IPL_030_2_{ B}
|
||
: AS_030{ H} AS_000{ D} RW_000{ H}
|
||
: DS_030{ A} SIZE_0_{ G} A0{ G}
|
||
: BG_000{ D} BGACK_030{ H} CLK_EXP{ B}
|
||
: DSACK1{ H} IPL_030_1_{ B} AVEC_EXP{ C}
|
||
: IPL_030_0_{ B} E{ G} VMA{ D}
|
||
: RESET{ B} RW{ G}AMIGA_BUS_ENABLE{ D}
|
||
:AMIGA_BUS_ENABLE_LOW{ C}inst_AS_030_000_SYNC{ H}inst_BGACK_030_INT_D{ D}
|
||
: inst_VPA_D{ G}inst_CLK_OUT_PRE_50_D{ H}inst_CLK_000_D0{ B}
|
||
: CLK_CNT_N_0_{ E}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ C}
|
||
:inst_CLK_000_D1{ D}inst_CLK_000_D2{ F}inst_CLK_000_D3{ A}
|
||
:inst_CLK_000_NE{ A}inst_CLK_OUT_PRE_D{ H}inst_CLK_OUT_PRE{ E}
|
||
:CLK_000_P_SYNC_9_{ G}CLK_000_N_SYNC_11_{ A} SM_AMIGA_7_{ F}
|
||
: SM_AMIGA_1_{ F} SM_AMIGA_0_{ F} SM_AMIGA_6_{ A}
|
||
: SM_AMIGA_4_{ F}CLK_000_N_SYNC_6_{ C} CLK_CNT_P_1_{ E}
|
||
: CLK_CNT_N_1_{ E} inst_CLK_030_H{ A} CLK_CNT_P_0_{ E}
|
||
:inst_LDS_000_INT{ C}inst_DS_000_ENABLE{ B}inst_UDS_000_INT{ C}
|
||
:CLK_000_P_SYNC_0_{ A}CLK_000_P_SYNC_1_{ G}CLK_000_P_SYNC_2_{ C}
|
||
:CLK_000_P_SYNC_3_{ G}CLK_000_P_SYNC_4_{ A}CLK_000_P_SYNC_5_{ B}
|
||
:CLK_000_P_SYNC_6_{ E}CLK_000_P_SYNC_7_{ A}CLK_000_P_SYNC_8_{ B}
|
||
:CLK_000_N_SYNC_0_{ A}CLK_000_N_SYNC_1_{ F}CLK_000_N_SYNC_2_{ G}
|
||
:CLK_000_N_SYNC_3_{ C}CLK_000_N_SYNC_4_{ C}CLK_000_N_SYNC_5_{ B}
|
||
:CLK_000_N_SYNC_7_{ H}CLK_000_N_SYNC_8_{ C}CLK_000_N_SYNC_9_{ B}
|
||
:CLK_000_N_SYNC_10_{ C} SM_AMIGA_5_{ F} SM_AMIGA_3_{ F}
|
||
: SM_AMIGA_2_{ F} cpu_est_0_{ D} cpu_est_1_{ G}
|
||
: cpu_est_2_{ D}
|
||
SIZE_1_{ I}:inst_LDS_000_INT{ C}
|
||
RN_IPL_030_2_{ C}: IPL_030_2_{ B}
|
||
AS_030{ I}: FPU_CS{ H} AS_000{ D} BG_000{ D}
|
||
: DSACK1{ H}AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}
|
||
:inst_DS_000_ENABLE{ B}
|
||
RN_AS_030{ I}: DTACK{ D} SIZE_1_{ H} AS_030{ H}
|
||
: DS_030{ A} SIZE_0_{ G} A0{ G}
|
||
: inst_CLK_030_H{ A}
|
||
AS_000{ E}:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H}
|
||
: DS_030{ A} SIZE_0_{ G} A0{ G}
|
||
: RW{ G} inst_CLK_030_H{ A}
|
||
RN_AS_000{ E}: AS_000{ D} VMA{ D}
|
||
RW_000{ I}: DS_030{ A} RW{ G}
|
||
RN_RW_000{ I}: RW_000{ H}
|
||
DS_030{ B}:inst_LDS_000_INT{ C}inst_UDS_000_INT{ C}
|
||
RN_DS_030{ B}: DS_030{ A}
|
||
SIZE_0_{ H}:inst_LDS_000_INT{ C}
|
||
A0{ H}:inst_LDS_000_INT{ C}inst_UDS_000_INT{ C}
|
||
RN_BG_000{ E}: BG_000{ D}
|
||
RN_BGACK_030{ I}: UDS_000{ D} LDS_000{ D} DTACK{ D}
|
||
:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H}
|
||
: AS_000{ D} RW_000{ H} DS_030{ A}
|
||
: SIZE_0_{ G} A0{ G} BGACK_030{ H}
|
||
: RW{ G}AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}
|
||
:inst_BGACK_030_INT_D{ D} inst_CLK_030_H{ A}
|
||
DSACK1{ I}: DTACK{ D}
|
||
RN_DSACK1{ I}: DSACK1{ H}
|
||
RN_IPL_030_1_{ C}: IPL_030_1_{ B}
|
||
RN_AVEC_EXP{ D}: IPL_030_2_{ B} AS_000{ D} RW_000{ H}
|
||
: BGACK_030{ H} IPL_030_1_{ B} IPL_030_0_{ B}
|
||
: E{ G} SM_AMIGA_7_{ F} SM_AMIGA_1_{ F}
|
||
: SM_AMIGA_0_{ F} SM_AMIGA_6_{ A} SM_AMIGA_4_{ F}
|
||
:inst_DS_000_ENABLE{ B} SM_AMIGA_5_{ F} SM_AMIGA_3_{ F}
|
||
: SM_AMIGA_2_{ F} cpu_est_0_{ D} cpu_est_1_{ G}
|
||
: cpu_est_2_{ D} SM_AMIGA_7__0{ F}
|
||
RN_IPL_030_0_{ C}: IPL_030_0_{ B}
|
||
RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_7_{ F}
|
||
: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} cpu_est_1_{ G}
|
||
: cpu_est_2_{ D}
|
||
RN_VMA{ E}: VMA{ D} SM_AMIGA_7_{ F} SM_AMIGA_3_{ F}
|
||
: SM_AMIGA_2_{ F}
|
||
RW{ H}:AMIGA_BUS_DATA_DIR{ E} RW_000{ H}inst_DS_000_ENABLE{ B}
|
||
RN_RW{ H}: RW{ G}
|
||
RN_AMIGA_BUS_ENABLE{ E}:AMIGA_BUS_ENABLE{ D}
|
||
RN_AMIGA_BUS_ENABLE_LOW{ D}:AMIGA_BUS_ENABLE_LOW{ C}
|
||
inst_AS_030_000_SYNC{ I}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ A}
|
||
: SM_AMIGA_7__0{ F}
|
||
inst_BGACK_030_INT_D{ E}:AMIGA_BUS_ENABLE{ D}
|
||
inst_VPA_D{ H}: VMA{ D}
|
||
inst_CLK_OUT_PRE_50_D{ I}:inst_CLK_OUT_PRE_25{ C}
|
||
inst_CLK_000_D0{ C}: VMA{ D}AMIGA_BUS_ENABLE{ D}inst_CLK_000_D1{ D}
|
||
: SM_AMIGA_6_{ A}CLK_000_P_SYNC_0_{ A}CLK_000_N_SYNC_0_{ A}
|
||
: SM_AMIGA_7__0{ F}
|
||
CLK_CNT_N_0_{ F}: CLK_CNT_N_0_{ E} CLK_CNT_N_1_{ E} CLK_PRE_66_0{ E}
|
||
inst_CLK_OUT_PRE_50{ I}:inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ C}
|
||
inst_CLK_OUT_PRE_25{ D}:inst_CLK_OUT_PRE_25{ C}inst_CLK_OUT_PRE{ E}
|
||
inst_CLK_000_D1{ E}:AMIGA_BUS_ENABLE{ D}inst_CLK_000_D2{ F} SM_AMIGA_6_{ A}
|
||
:CLK_000_P_SYNC_0_{ A}CLK_000_N_SYNC_0_{ A} SM_AMIGA_7__0{ F}
|
||
inst_CLK_000_D2{ G}:inst_CLK_000_D3{ A}CLK_000_P_SYNC_0_{ A}CLK_000_N_SYNC_0_{ A}
|
||
inst_CLK_000_D3{ B}:CLK_000_P_SYNC_0_{ A}CLK_000_N_SYNC_0_{ A}
|
||
inst_CLK_000_NE{ B}:AMIGA_BUS_ENABLE{ D} SM_AMIGA_7_{ F} SM_AMIGA_1_{ F}
|
||
: SM_AMIGA_0_{ F} SM_AMIGA_4_{ F} SM_AMIGA_5_{ F}
|
||
: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
||
inst_CLK_OUT_PRE_D{ I}: CLK_DIV_OUT{ G} CLK_EXP{ B}
|
||
inst_CLK_OUT_PRE{ F}:inst_CLK_OUT_PRE_D{ H}
|
||
CLK_000_P_SYNC_9_{ H}: AVEC_EXP{ C}
|
||
CLK_000_N_SYNC_11_{ B}:inst_CLK_000_NE{ A}
|
||
SM_AMIGA_7_{ G}: RW_000{ H} BG_000{ D}AMIGA_BUS_ENABLE{ D}
|
||
:inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ A}
|
||
SM_AMIGA_1_{ G}: DSACK1{ H}AMIGA_BUS_ENABLE{ D} SM_AMIGA_7_{ F}
|
||
: SM_AMIGA_1_{ F} SM_AMIGA_0_{ F} SM_AMIGA_7__0{ F}
|
||
SM_AMIGA_0_{ G}:AMIGA_BUS_ENABLE{ D} SM_AMIGA_7_{ F} SM_AMIGA_0_{ F}
|
||
: SM_AMIGA_7__0{ F}
|
||
SM_AMIGA_6_{ B}: AS_000{ D} RW_000{ H} SM_AMIGA_7_{ F}
|
||
: SM_AMIGA_6_{ A}inst_DS_000_ENABLE{ B} SM_AMIGA_5_{ F}
|
||
: SM_AMIGA_7__0{ F}
|
||
SM_AMIGA_4_{ G}: SM_AMIGA_7_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ B}
|
||
: SM_AMIGA_3_{ F} SM_AMIGA_7__0{ F}
|
||
CLK_000_N_SYNC_6_{ D}: DSACK1{ H}CLK_000_N_SYNC_7_{ H}
|
||
CLK_CNT_P_1_{ F}: CLK_CNT_P_0_{ E} CLK_PRE_66_0{ E}
|
||
CLK_CNT_N_1_{ F}: CLK_CNT_N_0_{ E} CLK_PRE_66_0{ E}
|
||
inst_CLK_030_H{ B}: DS_030{ A} inst_CLK_030_H{ A}
|
||
CLK_CNT_P_0_{ F}: CLK_CNT_P_1_{ E} CLK_CNT_P_0_{ E} CLK_PRE_66_0{ E}
|
||
inst_LDS_000_INT{ D}: LDS_000{ D}inst_LDS_000_INT{ C}
|
||
inst_DS_000_ENABLE{ C}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ B}
|
||
inst_UDS_000_INT{ D}: UDS_000{ D}inst_UDS_000_INT{ C}
|
||
CLK_000_P_SYNC_0_{ B}:CLK_000_P_SYNC_1_{ G}
|
||
CLK_000_P_SYNC_1_{ H}:CLK_000_P_SYNC_2_{ C}
|
||
CLK_000_P_SYNC_2_{ D}:CLK_000_P_SYNC_3_{ G}
|
||
CLK_000_P_SYNC_3_{ H}:CLK_000_P_SYNC_4_{ A}
|
||
CLK_000_P_SYNC_4_{ B}:CLK_000_P_SYNC_5_{ B}
|
||
CLK_000_P_SYNC_5_{ C}:CLK_000_P_SYNC_6_{ E}
|
||
CLK_000_P_SYNC_6_{ F}:CLK_000_P_SYNC_7_{ A}
|
||
CLK_000_P_SYNC_7_{ B}:CLK_000_P_SYNC_8_{ B}
|
||
CLK_000_P_SYNC_8_{ C}:CLK_000_P_SYNC_9_{ G}
|
||
CLK_000_N_SYNC_0_{ B}:CLK_000_N_SYNC_1_{ F}
|
||
CLK_000_N_SYNC_1_{ G}:CLK_000_N_SYNC_2_{ G}
|
||
CLK_000_N_SYNC_2_{ H}:CLK_000_N_SYNC_3_{ C}
|
||
CLK_000_N_SYNC_3_{ D}:CLK_000_N_SYNC_4_{ C}
|
||
CLK_000_N_SYNC_4_{ D}:CLK_000_N_SYNC_5_{ B}
|
||
CLK_000_N_SYNC_5_{ C}:CLK_000_N_SYNC_6_{ C}
|
||
CLK_000_N_SYNC_7_{ I}:CLK_000_N_SYNC_8_{ C}
|
||
CLK_000_N_SYNC_8_{ D}:CLK_000_N_SYNC_9_{ B}
|
||
CLK_000_N_SYNC_9_{ C}:CLK_000_N_SYNC_10_{ C}
|
||
CLK_000_N_SYNC_10_{ D}:CLK_000_N_SYNC_11_{ A}
|
||
SM_AMIGA_5_{ G}: SM_AMIGA_7_{ F} SM_AMIGA_4_{ F} SM_AMIGA_5_{ F}
|
||
: SM_AMIGA_7__0{ F}
|
||
SM_AMIGA_3_{ G}: SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
|
||
: SM_AMIGA_7__0{ F}
|
||
SM_AMIGA_2_{ G}: SM_AMIGA_7_{ F} SM_AMIGA_1_{ F} SM_AMIGA_2_{ F}
|
||
: SM_AMIGA_7__0{ F}
|
||
cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D}
|
||
: cpu_est_1_{ G} cpu_est_2_{ D}
|
||
cpu_est_1_{ H}: E{ G} VMA{ D} SM_AMIGA_7_{ F}
|
||
: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} cpu_est_1_{ G}
|
||
: cpu_est_2_{ D}
|
||
cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ G}
|
||
: cpu_est_2_{ D}
|
||
CLK_PRE_66_0{ F}:AMIGA_BUS_ENABLE_LOW{ C}
|
||
SM_AMIGA_7__0{ G}: SM_AMIGA_7_{ F}
|
||
-----------------------------------------------------------------------------
|
||
|
||
<Note> {.} : Indicates block location of signal
|
||
|
||
|
||
Set_Reset_Summary
|
||
~~~~~~~~~~~~~~~~~
|
||
|
||
Block A
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | DS_030
|
||
| | | | | AVEC
|
||
| * | S | BR | BS | SM_AMIGA_6_
|
||
| * | S | BR | BS | inst_CLK_000_NE
|
||
| * | S | BS | BR | RN_DS_030
|
||
| * | S | BR | BR | inst_CLK_030_H
|
||
| * | S | BR | BS | CLK_000_N_SYNC_0_
|
||
| * | S | BR | BS | CLK_000_P_SYNC_7_
|
||
| * | S | BR | BS | CLK_000_P_SYNC_4_
|
||
| * | S | BR | BS | CLK_000_P_SYNC_0_
|
||
| * | S | BR | BS | CLK_000_N_SYNC_11_
|
||
| * | S | BS | BR | inst_CLK_000_D3
|
||
| | | | | A_19_
|
||
| | | | | A_16_
|
||
| | | | | A_18_
|
||
| | | | | A_21_
|
||
| | | | | A_20_
|
||
|
||
|
||
Block B
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | IPL_030_2_
|
||
| * | S | BS | BR | IPL_030_0_
|
||
| * | S | BS | BR | IPL_030_1_
|
||
| * | S | BR | BS | CLK_EXP
|
||
| * | S | BR | BS | RESET
|
||
| * | S | BS | BR | inst_CLK_000_D0
|
||
| * | S | BR | BS | inst_DS_000_ENABLE
|
||
| * | S | BS | BR | RN_IPL_030_0_
|
||
| * | S | BS | BR | RN_IPL_030_1_
|
||
| * | S | BS | BR | RN_IPL_030_2_
|
||
| * | S | BR | BS | CLK_000_N_SYNC_9_
|
||
| * | S | BR | BS | CLK_000_N_SYNC_5_
|
||
| * | S | BR | BS | CLK_000_P_SYNC_8_
|
||
| * | S | BR | BS | CLK_000_P_SYNC_5_
|
||
| | | | | A_29_
|
||
| | | | | A_30_
|
||
| | | | | A_31_
|
||
|
||
|
||
Block C
|
||
block level set pt :
|
||
block level reset pt : !RST
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | AVEC_EXP
|
||
| * | A | | | AMIGA_BUS_ENABLE_LOW
|
||
| * | S | BS | BR | RN_AVEC_EXP
|
||
| * | S | BS | BR | inst_CLK_OUT_PRE_25
|
||
| * | S | BR | BS | inst_UDS_000_INT
|
||
| * | S | BR | BS | inst_LDS_000_INT
|
||
| * | A | | | RN_AMIGA_BUS_ENABLE_LOW
|
||
| * | S | BS | BR | CLK_000_N_SYNC_10_
|
||
| * | S | BS | BR | CLK_000_N_SYNC_8_
|
||
| * | S | BS | BR | CLK_000_N_SYNC_4_
|
||
| * | S | BS | BR | CLK_000_N_SYNC_3_
|
||
| * | S | BS | BR | CLK_000_P_SYNC_2_
|
||
| * | S | BS | BR | CLK_000_N_SYNC_6_
|
||
| | | | | BG_030
|
||
| | | | | A_24_
|
||
| | | | | A_25_
|
||
| | | | | A_26_
|
||
| | | | | A_27_
|
||
| | | | | A_28_
|
||
|
||
|
||
Block D
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | AS_000
|
||
| | | | | UDS_000
|
||
| | | | | LDS_000
|
||
| | | | | DTACK
|
||
| * | S | BS | BR | AMIGA_BUS_ENABLE
|
||
| * | S | BS | BR | VMA
|
||
| * | S | BS | BR | BG_000
|
||
| * | S | BS | BR | inst_CLK_000_D1
|
||
| * | S | BR | BS | cpu_est_2_
|
||
| * | S | BS | BR | RN_VMA
|
||
| * | S | BR | BS | cpu_est_0_
|
||
| * | S | BS | BR | RN_AMIGA_BUS_ENABLE
|
||
| * | S | BS | BR | RN_BG_000
|
||
| * | S | BS | BR | RN_AS_000
|
||
| * | S | BS | BR | inst_BGACK_030_INT_D
|
||
| | | | | BGACK_000
|
||
|
||
|
||
Block E
|
||
block level set pt :
|
||
block level reset pt : !RST
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| | | | | CIIN
|
||
| | | | | AMIGA_BUS_DATA_DIR
|
||
| | | | | CLK_PRE_66_0
|
||
| * | S | BS | BR | CLK_CNT_P_0_
|
||
| * | S | BS | BR | CLK_CNT_N_0_
|
||
| * | S | BS | BR | CLK_000_P_SYNC_6_
|
||
| * | S | BR | BS | CLK_CNT_N_1_
|
||
| * | S | BS | BR | CLK_CNT_P_1_
|
||
| * | S | BS | BR | inst_CLK_OUT_PRE
|
||
| | | | | BERR
|
||
|
||
|
||
Block F
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | SM_AMIGA_7_
|
||
| * | S | BR | BS | SM_AMIGA_1_
|
||
| * | S | BR | BS | SM_AMIGA_4_
|
||
| * | S | BR | BS | SM_AMIGA_0_
|
||
| * | S | BR | BS | SM_AMIGA_3_
|
||
| | | | | SM_AMIGA_7__0
|
||
| * | S | BR | BS | SM_AMIGA_2_
|
||
| * | S | BR | BS | SM_AMIGA_5_
|
||
| * | S | BR | BS | CLK_000_N_SYNC_1_
|
||
| * | S | BS | BR | inst_CLK_000_D2
|
||
| | | | | A_17_
|
||
| | | | | FC_1_
|
||
| | | | | FC_0_
|
||
| | | | | IPL_1_
|
||
|
||
|
||
Block G
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | RW
|
||
| * | S | BS | BR | SIZE_0_
|
||
| * | S | BS | BR | A0
|
||
| * | S | BR | BS | E
|
||
| * | S | BR | BS | CLK_DIV_OUT
|
||
| * | S | BR | BS | cpu_est_1_
|
||
| * | S | BR | BS | RN_E
|
||
| * | S | BS | BR | RN_RW
|
||
| * | S | BR | BS | CLK_000_N_SYNC_2_
|
||
| * | S | BR | BS | CLK_000_P_SYNC_3_
|
||
| * | S | BR | BS | CLK_000_P_SYNC_1_
|
||
| * | S | BR | BS | CLK_000_P_SYNC_9_
|
||
| * | S | BS | BR | inst_VPA_D
|
||
| | | | | IPL_2_
|
||
| | | | | IPL_0_
|
||
|
||
|
||
Block H
|
||
block level set pt : !RST
|
||
block level reset pt :
|
||
Equations :
|
||
| | |Block|Block| Signal
|
||
| Reg |Mode |Set |Reset| Name
|
||
+-----+-----+-----+-----+------------------------
|
||
| * | S | BS | BR | AS_030
|
||
| * | S | BS | BR | RW_000
|
||
| * | S | BS | BR | DSACK1
|
||
| * | S | BS | BR | SIZE_1_
|
||
| * | S | BS | BR | BGACK_030
|
||
| | | | | FPU_CS
|
||
| * | S | BS | BR | RN_BGACK_030
|
||
| * | S | BS | BR | inst_AS_030_000_SYNC
|
||
| * | S | BS | BR | RN_AS_030
|
||
| * | S | BR | BS | inst_CLK_OUT_PRE_D
|
||
| * | S | BR | BS | inst_CLK_OUT_PRE_50
|
||
| * | S | BS | BR | RN_RW_000
|
||
| * | S | BS | BR | RN_DSACK1
|
||
| * | S | BR | BS | CLK_000_N_SYNC_7_
|
||
| * | S | BR | BS | inst_CLK_OUT_PRE_50_D
|
||
| | | | | A_22_
|
||
| | | | | A_23_
|
||
|
||
|
||
<Note> (S) means the macrocell is configured in synchronous mode
|
||
i.e. it uses the block-level set and reset pt.
|
||
(A) means the macrocell is configured in asynchronous mode
|
||
i.e. it can have its independant set or reset pt.
|
||
(BS) means the block-level set pt is selected.
|
||
(BR) means the block-level reset pt is selected.
|
||
|
||
|
||
|
||
|
||
BLOCK_A_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx A0 RST pin 86 mx A17 ... ...
|
||
mx A1 BERR pin 41 mx A18 SM_AMIGA_6_ mcell A8
|
||
mx A2 ... ... mx A19 ... ...
|
||
mx A3CLK_000_P_SYNC_6_ mcell E5 mx A20 RN_BGACK_030 mcell H4
|
||
mx A4 CLK_030 pin 64 mx A21 ... ...
|
||
mx A5 nEXP_SPACE pin 14 mx A22 ... ...
|
||
mx A6 RW_000 pin 80 mx A23 AS_000 pin 33
|
||
mx A7CLK_000_N_SYNC_10_ mcell C5 mx A24 LDS_000 pin 31
|
||
mx A8 UDS_000 pin 32 mx A25 inst_CLK_000_D1 mcell D9
|
||
mx A9CLK_000_P_SYNC_3_ mcell G13 mx A26 ... ...
|
||
mx A10CLK_000_N_SYNC_11_ mcell A6 mx A27inst_AS_030_000_SYNC mcell H9
|
||
mx A11 inst_CLK_000_D2 mcell F6 mx A28 inst_CLK_000_D0 mcell B5
|
||
mx A12 inst_CLK_030_H mcell A1 mx A29 ... ...
|
||
mx A13 RN_AS_030 mcell H8 mx A30 ... ...
|
||
mx A14 inst_CLK_000_D3 mcell A10 mx A31 SM_AMIGA_7_ mcell F0
|
||
mx A15 RN_DS_030 mcell A0 mx A32 ... ...
|
||
mx A16 RN_AVEC_EXP mcell C0
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_B_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx B0 IPL_0_ pin 67 mx B17 RN_IPL_030_0_ mcell B8
|
||
mx B1 BERR pin 41 mx B18 SM_AMIGA_6_ mcell A8
|
||
mx B2CLK_000_P_SYNC_7_ mcell A9 mx B19 AS_030 pin 82
|
||
mx B3 IPL_1_ pin 56 mx B20 SM_AMIGA_4_ mcell F8
|
||
mx B4 IPL_2_ pin 68 mx B21 RST pin 86
|
||
mx B5 ... ... mx B22 ... ...
|
||
mx B6inst_DS_000_ENABLE mcell B9 mx B23 ... ...
|
||
mx B7inst_CLK_OUT_PRE_D mcell H13 mx B24 ... ...
|
||
mx B8 RW pin 71 mx B25CLK_000_P_SYNC_4_ mcell A13
|
||
mx B9 RN_AVEC_EXP mcell C0 mx B26 ... ...
|
||
mx B10 ... ... mx B27 RN_IPL_030_2_ mcell B4
|
||
mx B11CLK_000_N_SYNC_4_ mcell C13 mx B28 ... ...
|
||
mx B12 RN_IPL_030_1_ mcell B12 mx B29 ... ...
|
||
mx B13CLK_000_N_SYNC_8_ mcell C9 mx B30 ... ...
|
||
mx B14 CLK_000 pin 11 mx B31 ... ...
|
||
mx B15 ... ... mx B32 ... ...
|
||
mx B16 ... ...
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_C_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx C0 A0 pin 69 mx C17 SIZE_0_ pin 70
|
||
mx C1inst_LDS_000_INT mcell C1 mx C18inst_CLK_OUT_PRE_50_D mcell H10
|
||
mx C2CLK_000_N_SYNC_3_ mcell C2 mx C19 ... ...
|
||
mx C3 ... ... mx C20 SIZE_1_ pin 79
|
||
mx C4CLK_000_P_SYNC_1_ mcell G2 mx C21 RST pin 86
|
||
mx C5 DS_030 pin 98 mx C22 ... ...
|
||
mx C6inst_CLK_OUT_PRE_25 mcell C4 mx C23CLK_000_P_SYNC_9_ mcell G6
|
||
mx C7CLK_000_N_SYNC_7_ mcell H6 mx C24 ... ...
|
||
mx C8 CLK_PRE_66_0 mcell E8 mx C25CLK_000_N_SYNC_5_ mcell B2
|
||
mx C9 ... ... mx C26 ... ...
|
||
mx C10CLK_000_N_SYNC_9_ mcell B13 mx C27 ... ...
|
||
mx C11 ... ... mx C28 ... ...
|
||
mx C12CLK_000_N_SYNC_2_ mcell G9 mx C29 ... ...
|
||
mx C13 ... ... mx C30 ... ...
|
||
mx C14inst_CLK_OUT_PRE_50 mcell H2 mx C31 ... ...
|
||
mx C15RN_AMIGA_BUS_ENABLE_LOW mcell C12 mx C32 ... ...
|
||
mx C16inst_UDS_000_INT mcell C8
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_D_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx D0 RST pin 86 mx D17 BERR pin 41
|
||
mx D1 SM_AMIGA_0_ mcell F12 mx D18 SM_AMIGA_6_ mcell A8
|
||
mx D2 RN_E mcell G4 mx D19 AS_030 pin 82
|
||
mx D3 CLK_000 pin 11 mx D20inst_BGACK_030_INT_D mcell D10
|
||
mx D4 cpu_est_0_ mcell D6 mx D21 RN_BG_000 mcell D13
|
||
mx D5 inst_VPA_D mcell G10 mx D22 BG_030 pin 21
|
||
mx D6inst_DS_000_ENABLE mcell B9 mx D23 RN_BGACK_030 mcell H4
|
||
mx D7inst_UDS_000_INT mcell C8 mx D24RN_AMIGA_BUS_ENABLE mcell D5
|
||
mx D8 ... ... mx D25 RN_AVEC_EXP mcell C0
|
||
mx D9 inst_CLK_000_NE mcell A12 mx D26 ... ...
|
||
mx D10 DSACK1 pin 81 mx D27 RN_VMA mcell D1
|
||
mx D11inst_AS_030_000_SYNC mcell H9 mx D28 inst_CLK_000_D0 mcell B5
|
||
mx D12 inst_CLK_000_D1 mcell D9 mx D29 SM_AMIGA_1_ mcell F4
|
||
mx D13 RN_AS_030 mcell H8 mx D30inst_LDS_000_INT mcell C1
|
||
mx D14 RN_AS_000 mcell D4 mx D31 SM_AMIGA_7_ mcell F0
|
||
mx D15 nEXP_SPACE pin 14 mx D32 cpu_est_1_ mcell G5
|
||
mx D16 cpu_est_2_ mcell D2
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_E_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx E0 RST pin 86 mx E17 A_26_ pin 17
|
||
mx E1 A_31_ pin 4 mx E18 A_22_ pin 85
|
||
mx E2 CLK_CNT_N_1_ mcell E9 mx E19 A_30_ pin 5
|
||
mx E3 A_27_ pin 16 mx E20 RN_BGACK_030 mcell H4
|
||
mx E4 A_29_ pin 6 mx E21 nEXP_SPACE pin 14
|
||
mx E5 CLK_CNT_N_0_ mcell E1 mx E22 ... ...
|
||
mx E6inst_CLK_OUT_PRE_25 mcell C4 mx E23 AS_000 pin 33
|
||
mx E7 A_28_ pin 15 mx E24CLK_000_P_SYNC_5_ mcell B10
|
||
mx E8 A_17_ pin 59 mx E25 RW pin 71
|
||
mx E9 A_23_ pin 84 mx E26 ... ...
|
||
mx E10 CLK_CNT_P_0_ mcell E12 mx E27 A_19_ pin 97
|
||
mx E11 A_16_ pin 96 mx E28 ... ...
|
||
mx E12 A_25_ pin 18 mx E29 A_20_ pin 93
|
||
mx E13 CLK_CNT_P_1_ mcell E13 mx E30 ... ...
|
||
mx E14 A_24_ pin 19 mx E31 A_18_ pin 95
|
||
mx E15 A_21_ pin 94 mx E32 ... ...
|
||
mx E16 ... ...
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_F_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx F0 RST pin 86 mx F17 SM_AMIGA_0_ mcell F12
|
||
mx F1 BERR pin 41 mx F18 SM_AMIGA_2_ mcell F9
|
||
mx F2CLK_000_N_SYNC_0_ mcell A5 mx F19 ... ...
|
||
mx F3 cpu_est_1_ mcell G5 mx F20 SM_AMIGA_4_ mcell F8
|
||
mx F4 ... ... mx F21 ... ...
|
||
mx F5inst_AS_030_000_SYNC mcell H9 mx F22 ... ...
|
||
mx F6 SM_AMIGA_5_ mcell F13 mx F23 DTACK pin 30
|
||
mx F7 inst_CLK_000_D1 mcell D9 mx F24 inst_CLK_000_NE mcell A12
|
||
mx F8 ... ... mx F25 ... ...
|
||
mx F9 SM_AMIGA_3_ mcell F5 mx F26 ... ...
|
||
mx F10 SM_AMIGA_7__0 mcell F1 mx F27 RN_VMA mcell D1
|
||
mx F11 RN_E mcell G4 mx F28 inst_CLK_000_D0 mcell B5
|
||
mx F12 ... ... mx F29 ... ...
|
||
mx F13 VPA pin 36 mx F30 SM_AMIGA_6_ mcell A8
|
||
mx F14 SM_AMIGA_1_ mcell F4 mx F31 ... ...
|
||
mx F15 nEXP_SPACE pin 14 mx F32 ... ...
|
||
mx F16 RN_AVEC_EXP mcell C0
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_G_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx G0 RST pin 86 mx G17 RN_RW mcell G0
|
||
mx G1 ... ... mx G18 ... ...
|
||
mx G2CLK_000_P_SYNC_8_ mcell B6 mx G19 ... ...
|
||
mx G3 cpu_est_2_ mcell D2 mx G20 RN_BGACK_030 mcell H4
|
||
mx G4 CLK_030 pin 64 mx G21 ... ...
|
||
mx G5 nEXP_SPACE pin 14 mx G22CLK_000_P_SYNC_0_ mcell A2
|
||
mx G6 RW_000 pin 80 mx G23 AS_000 pin 33
|
||
mx G7inst_CLK_OUT_PRE_D mcell H13 mx G24 LDS_000 pin 31
|
||
mx G8 UDS_000 pin 32 mx G25 RN_AVEC_EXP mcell C0
|
||
mx G9CLK_000_P_SYNC_2_ mcell C6 mx G26 ... ...
|
||
mx G10 VPA pin 36 mx G27 ... ...
|
||
mx G11 RN_E mcell G4 mx G28 ... ...
|
||
mx G12 ... ... mx G29 ... ...
|
||
mx G13 RN_AS_030 mcell H8 mx G30 ... ...
|
||
mx G14 ... ... mx G31 ... ...
|
||
mx G15CLK_000_N_SYNC_1_ mcell F2 mx G32 cpu_est_1_ mcell G5
|
||
mx G16 cpu_est_0_ mcell D6
|
||
----------------------------------------------------------------------------
|
||
|
||
|
||
BLOCK_H_LOGIC_ARRAY_FANIN
|
||
~~~~~~~~~~~~~~~~~~~~~~~~~
|
||
CSM Signal Source CSM Signal Source
|
||
------------------------------------ ------------------------------------
|
||
mx H0 AS_000 pin 33 mx H17 FC_0_ pin 57
|
||
mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28
|
||
mx H2 ... ... mx H19 AS_030 pin 82
|
||
mx H3 RN_AS_030 mcell H8 mx H20 RN_BGACK_030 mcell H4
|
||
mx H4 A_18_ pin 95 mx H21 RST pin 86
|
||
mx H5 nEXP_SPACE pin 14 mx H22 ... ...
|
||
mx H6 A_19_ pin 97 mx H23 RN_RW_000 mcell H0
|
||
mx H7 ... ... mx H24 LDS_000 pin 31
|
||
mx H8 RW pin 71 mx H25 BERR pin 41
|
||
mx H9 RN_AVEC_EXP mcell C0 mx H26CLK_000_N_SYNC_6_ mcell C10
|
||
mx H10 SM_AMIGA_1_ mcell F4 mx H27inst_AS_030_000_SYNC mcell H9
|
||
mx H11 A_16_ pin 96 mx H28 CLK_030 pin 64
|
||
mx H12 UDS_000 pin 32 mx H29 RN_DSACK1 mcell H12
|
||
mx H13 A_17_ pin 59 mx H30 SM_AMIGA_6_ mcell A8
|
||
mx H14inst_CLK_OUT_PRE_50 mcell H2 mx H31 SM_AMIGA_7_ mcell F0
|
||
mx H15inst_CLK_OUT_PRE mcell E2 mx H32 ... ...
|
||
mx H16 ... ...
|
||
----------------------------------------------------------------------------
|
||
|
||
<Note> CSM indicates the mux inputs from the Central Switch Matrix.
|
||
<Note> Source indicates where the signal comes from (pin or macrocell).
|
||
|
||
|
||
|
||
|
||
PostFit_Equations
|
||
~~~~~~~~~~~~~~~~~
|
||
|
||
|
||
P-Terms Fan-in Fan-out Type Name (attributes)
|
||
--------- ------ ------- ---- -----------------
|
||
1 2 1 Pin UDS_000-
|
||
1 1 1 Pin UDS_000.OE
|
||
1 2 1 Pin LDS_000-
|
||
1 1 1 Pin LDS_000.OE
|
||
1 1 1 Pin CLK_DIV_OUT.AR
|
||
1 1 1 Pin CLK_DIV_OUT.D
|
||
1 1 1 Pin CLK_DIV_OUT.C
|
||
1 8 1 Pin FPU_CS-
|
||
1 1 1 Pin DTACK
|
||
1 3 1 Pin DTACK.OE
|
||
1 0 1 Pin AVEC
|
||
2 4 1 Pin AMIGA_BUS_DATA_DIR
|
||
4 8 1 Pin CIIN
|
||
1 8 1 Pin CIIN.OE
|
||
1 3 1 Pin SIZE_1_.OE
|
||
2 4 1 Pin SIZE_1_.D-
|
||
1 1 1 Pin SIZE_1_.AP
|
||
1 1 1 Pin SIZE_1_.C
|
||
2 3 1 Pin IPL_030_2_.D
|
||
1 1 1 Pin IPL_030_2_.AP
|
||
1 1 1 Pin IPL_030_2_.C
|
||
1 3 1 Pin AS_030.OE
|
||
4 6 1 Pin AS_030.D
|
||
1 1 1 Pin AS_030.AP
|
||
1 1 1 Pin AS_030.C
|
||
1 1 1 Pin AS_000.OE
|
||
2 5 1 Pin AS_000.D-
|
||
1 1 1 Pin AS_000.AP
|
||
1 1 1 Pin AS_000.C
|
||
1 1 1 Pin RW_000.OE
|
||
3 5 1 Pin RW_000.D-
|
||
1 1 1 Pin RW_000.AP
|
||
1 1 1 Pin RW_000.C
|
||
1 3 1 Pin DS_030.OE
|
||
7 9 1 Pin DS_030.D
|
||
1 1 1 Pin DS_030.AP
|
||
1 1 1 Pin DS_030.C
|
||
1 3 1 Pin SIZE_0_.OE
|
||
1 4 1 Pin SIZE_0_.D-
|
||
1 1 1 Pin SIZE_0_.AP
|
||
1 1 1 Pin SIZE_0_.C
|
||
1 3 1 Pin A0.OE
|
||
1 4 1 Pin A0.D
|
||
1 1 1 Pin A0.AP
|
||
1 1 1 Pin A0.C
|
||
2 6 1 Pin BG_000.D-
|
||
1 1 1 Pin BG_000.AP
|
||
1 1 1 Pin BG_000.C
|
||
2 3 1 Pin BGACK_030.D
|
||
1 1 1 Pin BGACK_030.AP
|
||
1 1 1 Pin BGACK_030.C
|
||
1 1 1 Pin CLK_EXP.AR
|
||
1 1 1 Pin CLK_EXP.D
|
||
1 1 1 Pin CLK_EXP.C
|
||
1 1 1 Pin DSACK1.OE
|
||
2 5 1 Pin DSACK1.D-
|
||
1 1 1 Pin DSACK1.AP
|
||
1 1 1 Pin DSACK1.C
|
||
2 3 1 Pin IPL_030_1_.D
|
||
1 1 1 Pin IPL_030_1_.AP
|
||
1 1 1 Pin IPL_030_1_.C
|
||
1 1 1 Pin AVEC_EXP.AR
|
||
1 1 1 Pin AVEC_EXP.D
|
||
1 1 1 Pin AVEC_EXP.C
|
||
2 3 1 Pin IPL_030_0_.D
|
||
1 1 1 Pin IPL_030_0_.AP
|
||
1 1 1 Pin IPL_030_0_.C
|
||
1 1 1 Pin E.AR
|
||
4 5 1 Pin E.D-
|
||
1 1 1 Pin E.C
|
||
2 7 1 PinX1 VMA.D.X1
|
||
1 5 1 PinX2 VMA.D.X2
|
||
1 1 1 Pin VMA.AP
|
||
1 1 1 Pin VMA.C
|
||
1 1 1 Pin RESET.AR
|
||
1 0 1 Pin RESET.D
|
||
1 1 1 Pin RESET.C
|
||
1 1 1 Pin RW.OE
|
||
4 7 1 Pin RW.D-
|
||
1 1 1 Pin RW.AP
|
||
1 1 1 Pin RW.C
|
||
6 12 1 Pin AMIGA_BUS_ENABLE.D-
|
||
1 1 1 Pin AMIGA_BUS_ENABLE.AP
|
||
1 1 1 Pin AMIGA_BUS_ENABLE.C
|
||
1 1 1 Pin AMIGA_BUS_ENABLE_LOW.AR
|
||
1 1 1 Pin AMIGA_BUS_ENABLE_LOW.D
|
||
1 1 1 Pin AMIGA_BUS_ENABLE_LOW.C
|
||
6 13 1 Node inst_AS_030_000_SYNC.D
|
||
1 1 1 Node inst_AS_030_000_SYNC.AP
|
||
1 1 1 Node inst_AS_030_000_SYNC.C
|
||
1 1 1 Node inst_BGACK_030_INT_D.D
|
||
1 1 1 Node inst_BGACK_030_INT_D.AP
|
||
1 1 1 Node inst_BGACK_030_INT_D.C
|
||
1 1 1 Node inst_VPA_D.D
|
||
1 1 1 Node inst_VPA_D.AP
|
||
1 1 1 Node inst_VPA_D.C
|
||
1 1 1 Node inst_CLK_OUT_PRE_50_D.AR
|
||
1 1 1 Node inst_CLK_OUT_PRE_50_D.D
|
||
1 1 1 Node inst_CLK_OUT_PRE_50_D.C
|
||
1 1 1 Node inst_CLK_000_D0.D
|
||
1 1 1 Node inst_CLK_000_D0.AP
|
||
1 1 1 Node inst_CLK_000_D0.C
|
||
1 1 1 Node CLK_CNT_N_0_.AR
|
||
2 2 1 Node CLK_CNT_N_0_.D
|
||
1 1 1 Node CLK_CNT_N_0_.C
|
||
1 1 1 Node inst_CLK_OUT_PRE_50.AR
|
||
1 1 1 Node inst_CLK_OUT_PRE_50.D
|
||
1 1 1 Node inst_CLK_OUT_PRE_50.C
|
||
1 1 1 Node inst_CLK_OUT_PRE_25.AR
|
||
3 3 1 Node inst_CLK_OUT_PRE_25.D
|
||
1 1 1 Node inst_CLK_OUT_PRE_25.C
|
||
1 1 1 Node inst_CLK_000_D1.D
|
||
1 1 1 Node inst_CLK_000_D1.AP
|
||
1 1 1 Node inst_CLK_000_D1.C
|
||
1 1 1 Node inst_CLK_000_D2.D
|
||
1 1 1 Node inst_CLK_000_D2.AP
|
||
1 1 1 Node inst_CLK_000_D2.C
|
||
1 1 1 Node inst_CLK_000_D3.D
|
||
1 1 1 Node inst_CLK_000_D3.AP
|
||
1 1 1 Node inst_CLK_000_D3.C
|
||
1 1 1 Node inst_CLK_000_NE.AR
|
||
1 1 1 Node inst_CLK_000_NE.D
|
||
1 1 1 Node inst_CLK_000_NE.C
|
||
1 1 1 Node inst_CLK_OUT_PRE_D.AR
|
||
1 1 1 Node inst_CLK_OUT_PRE_D.D
|
||
1 1 1 Node inst_CLK_OUT_PRE_D.C
|
||
1 1 1 Node inst_CLK_OUT_PRE.AR
|
||
1 1 1 Node inst_CLK_OUT_PRE.D
|
||
1 1 1 Node inst_CLK_OUT_PRE.C
|
||
1 1 1 Node CLK_000_P_SYNC_9_.AR
|
||
1 1 1 Node CLK_000_P_SYNC_9_.D
|
||
1 1 1 Node CLK_000_P_SYNC_9_.C
|
||
1 1 1 Node CLK_000_N_SYNC_11_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_11_.D
|
||
1 1 1 Node CLK_000_N_SYNC_11_.C
|
||
13 17 1 Node SM_AMIGA_7_.D
|
||
1 1 1 Node SM_AMIGA_7_.AP
|
||
1 1 1 Node SM_AMIGA_7_.C
|
||
1 1 1 Node SM_AMIGA_1_.AR
|
||
2 5 1 Node SM_AMIGA_1_.D
|
||
1 1 1 Node SM_AMIGA_1_.C
|
||
1 1 1 Node SM_AMIGA_0_.AR
|
||
2 5 1 Node SM_AMIGA_0_.D
|
||
1 1 1 Node SM_AMIGA_0_.C
|
||
1 1 1 Node SM_AMIGA_6_.AR
|
||
2 8 1 Node SM_AMIGA_6_.D
|
||
1 1 1 Node SM_AMIGA_6_.C
|
||
1 1 1 Node SM_AMIGA_4_.AR
|
||
2 5 1 Node SM_AMIGA_4_.D
|
||
1 1 1 Node SM_AMIGA_4_.C
|
||
1 1 1 Node CLK_000_N_SYNC_6_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_6_.D
|
||
1 1 1 Node CLK_000_N_SYNC_6_.C
|
||
1 1 1 Node CLK_CNT_P_1_.AR
|
||
1 1 1 Node CLK_CNT_P_1_.D
|
||
1 1 1 Node CLK_CNT_P_1_.C
|
||
1 1 1 Node CLK_CNT_N_1_.D
|
||
1 1 1 Node CLK_CNT_N_1_.AP
|
||
1 1 1 Node CLK_CNT_N_1_.C
|
||
5 8 1 Node inst_CLK_030_H.D
|
||
1 1 1 Node inst_CLK_030_H.C
|
||
1 1 1 Node CLK_CNT_P_0_.AR
|
||
2 2 1 Node CLK_CNT_P_0_.D
|
||
1 1 1 Node CLK_CNT_P_0_.C
|
||
2 5 1 Node inst_LDS_000_INT.D
|
||
1 1 1 Node inst_LDS_000_INT.AP
|
||
1 1 1 Node inst_LDS_000_INT.C
|
||
1 1 1 Node inst_DS_000_ENABLE.AR
|
||
3 7 1 Node inst_DS_000_ENABLE.D
|
||
1 1 1 Node inst_DS_000_ENABLE.C
|
||
2 3 1 Node inst_UDS_000_INT.D
|
||
1 1 1 Node inst_UDS_000_INT.AP
|
||
1 1 1 Node inst_UDS_000_INT.C
|
||
1 1 1 Node CLK_000_P_SYNC_0_.AR
|
||
1 4 1 Node CLK_000_P_SYNC_0_.D
|
||
1 1 1 Node CLK_000_P_SYNC_0_.C
|
||
1 1 1 Node CLK_000_P_SYNC_1_.AR
|
||
1 1 1 Node CLK_000_P_SYNC_1_.D
|
||
1 1 1 Node CLK_000_P_SYNC_1_.C
|
||
1 1 1 Node CLK_000_P_SYNC_2_.AR
|
||
1 1 1 Node CLK_000_P_SYNC_2_.D
|
||
1 1 1 Node CLK_000_P_SYNC_2_.C
|
||
1 1 1 Node CLK_000_P_SYNC_3_.AR
|
||
1 1 1 Node CLK_000_P_SYNC_3_.D
|
||
1 1 1 Node CLK_000_P_SYNC_3_.C
|
||
1 1 1 Node CLK_000_P_SYNC_4_.AR
|
||
1 1 1 Node CLK_000_P_SYNC_4_.D
|
||
1 1 1 Node CLK_000_P_SYNC_4_.C
|
||
1 1 1 Node CLK_000_P_SYNC_5_.AR
|
||
1 1 1 Node CLK_000_P_SYNC_5_.D
|
||
1 1 1 Node CLK_000_P_SYNC_5_.C
|
||
1 1 1 Node CLK_000_P_SYNC_6_.AR
|
||
1 1 1 Node CLK_000_P_SYNC_6_.D
|
||
1 1 1 Node CLK_000_P_SYNC_6_.C
|
||
1 1 1 Node CLK_000_P_SYNC_7_.AR
|
||
1 1 1 Node CLK_000_P_SYNC_7_.D
|
||
1 1 1 Node CLK_000_P_SYNC_7_.C
|
||
1 1 1 Node CLK_000_P_SYNC_8_.AR
|
||
1 1 1 Node CLK_000_P_SYNC_8_.D
|
||
1 1 1 Node CLK_000_P_SYNC_8_.C
|
||
1 1 1 Node CLK_000_N_SYNC_0_.AR
|
||
1 4 1 Node CLK_000_N_SYNC_0_.D
|
||
1 1 1 Node CLK_000_N_SYNC_0_.C
|
||
1 1 1 Node CLK_000_N_SYNC_1_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_1_.D
|
||
1 1 1 Node CLK_000_N_SYNC_1_.C
|
||
1 1 1 Node CLK_000_N_SYNC_2_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_2_.D
|
||
1 1 1 Node CLK_000_N_SYNC_2_.C
|
||
1 1 1 Node CLK_000_N_SYNC_3_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_3_.D
|
||
1 1 1 Node CLK_000_N_SYNC_3_.C
|
||
1 1 1 Node CLK_000_N_SYNC_4_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_4_.D
|
||
1 1 1 Node CLK_000_N_SYNC_4_.C
|
||
1 1 1 Node CLK_000_N_SYNC_5_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_5_.D
|
||
1 1 1 Node CLK_000_N_SYNC_5_.C
|
||
1 1 1 Node CLK_000_N_SYNC_7_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_7_.D
|
||
1 1 1 Node CLK_000_N_SYNC_7_.C
|
||
1 1 1 Node CLK_000_N_SYNC_8_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_8_.D
|
||
1 1 1 Node CLK_000_N_SYNC_8_.C
|
||
1 1 1 Node CLK_000_N_SYNC_9_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_9_.D
|
||
1 1 1 Node CLK_000_N_SYNC_9_.C
|
||
1 1 1 Node CLK_000_N_SYNC_10_.AR
|
||
1 1 1 Node CLK_000_N_SYNC_10_.D
|
||
1 1 1 Node CLK_000_N_SYNC_10_.C
|
||
1 1 1 Node SM_AMIGA_5_.AR
|
||
2 5 1 Node SM_AMIGA_5_.D
|
||
1 1 1 Node SM_AMIGA_5_.C
|
||
1 1 1 Node SM_AMIGA_3_.AR
|
||
6 10 1 Node SM_AMIGA_3_.D
|
||
1 1 1 Node SM_AMIGA_3_.C
|
||
1 1 1 Node SM_AMIGA_2_.AR
|
||
3 10 1 Node SM_AMIGA_2_.D
|
||
1 1 1 Node SM_AMIGA_2_.C
|
||
1 1 1 Node cpu_est_0_.AR
|
||
2 2 1 Node cpu_est_0_.D
|
||
1 1 1 Node cpu_est_0_.C
|
||
1 1 1 Node cpu_est_1_.AR
|
||
5 5 1 Node cpu_est_1_.D
|
||
1 1 1 Node cpu_est_1_.C
|
||
1 1 1 Node cpu_est_2_.AR
|
||
4 5 1 Node cpu_est_2_.D
|
||
1 1 1 Node cpu_est_2_.C
|
||
2 4 1 Node CLK_PRE_66_0-
|
||
4 11 1 Node SM_AMIGA_7__0
|
||
=========
|
||
338 P-Term Total: 338
|
||
Total Pins: 59
|
||
Total Nodes: 56
|
||
Average P-Term/Output: 2
|
||
|
||
|
||
Equations:
|
||
|
||
!UDS_000 = (inst_DS_000_ENABLE.Q & !inst_UDS_000_INT.Q);
|
||
|
||
UDS_000.OE = (BGACK_030.Q);
|
||
|
||
!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
|
||
|
||
LDS_000.OE = (BGACK_030.Q);
|
||
|
||
CLK_DIV_OUT.AR = (!RST);
|
||
|
||
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
|
||
|
||
CLK_DIV_OUT.C = (CLK_OSZI);
|
||
|
||
!FPU_CS = (FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
|
||
|
||
DTACK = (DSACK1.PIN);
|
||
|
||
DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
AVEC = (1);
|
||
|
||
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN
|
||
# !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN);
|
||
|
||
CIIN = (A_23_ & A_22_ & A_21_ & A_20_
|
||
# !A_23_ & !A_22_ & A_21_ & !A_20_
|
||
# !A_23_ & A_22_ & !A_21_ & !A_20_
|
||
# A_23_ & A_22_ & A_21_ & !A_19_ & !A_18_ & !A_17_ & !A_16_);
|
||
|
||
CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_);
|
||
|
||
SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
!SIZE_1_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN
|
||
# !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);
|
||
|
||
SIZE_1_.AP = (!RST);
|
||
|
||
SIZE_1_.C = (CLK_OSZI);
|
||
|
||
IPL_030_2_.D = (IPL_2_ & AVEC_EXP.Q
|
||
# !AVEC_EXP.Q & IPL_030_2_.Q);
|
||
|
||
IPL_030_2_.AP = (!RST);
|
||
|
||
IPL_030_2_.C = (CLK_OSZI);
|
||
|
||
AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
AS_030.D = (BGACK_030.Q
|
||
# AS_000.PIN
|
||
# CLK_030 & AS_030.Q
|
||
# UDS_000.PIN & LDS_000.PIN);
|
||
|
||
AS_030.AP = (!RST);
|
||
|
||
AS_030.C = (CLK_OSZI);
|
||
|
||
AS_000.OE = (BGACK_030.Q);
|
||
|
||
!AS_000.D = (AVEC_EXP.Q & SM_AMIGA_6_.Q
|
||
# BERR & !AS_000.Q & !AS_030.PIN);
|
||
|
||
AS_000.AP = (!RST);
|
||
|
||
AS_000.C = (CLK_OSZI);
|
||
|
||
RW_000.OE = (BGACK_030.Q);
|
||
|
||
!RW_000.D = (!AVEC_EXP.Q & !SM_AMIGA_7_.Q & !RW_000.Q
|
||
# !SM_AMIGA_7_.Q & !SM_AMIGA_6_.Q & !RW_000.Q
|
||
# AVEC_EXP.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q & !RW.PIN);
|
||
|
||
RW_000.AP = (!RST);
|
||
|
||
RW_000.C = (CLK_OSZI);
|
||
|
||
DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
DS_030.D = (BGACK_030.Q
|
||
# AS_000.PIN
|
||
# AS_030.Q & RW_000.PIN
|
||
# UDS_000.PIN & LDS_000.PIN
|
||
# !CLK_030 & AS_030.Q & inst_CLK_030_H.Q
|
||
# CLK_030 & DS_030.Q & !RW_000.PIN
|
||
# !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN);
|
||
|
||
DS_030.AP = (!RST);
|
||
|
||
DS_030.C = (CLK_OSZI);
|
||
|
||
SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
!SIZE_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN);
|
||
|
||
SIZE_0_.AP = (!RST);
|
||
|
||
SIZE_0_.C = (CLK_OSZI);
|
||
|
||
A0.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q);
|
||
|
||
A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);
|
||
|
||
A0.AP = (!RST);
|
||
|
||
A0.C = (CLK_OSZI);
|
||
|
||
!BG_000.D = (!BG_030 & !BG_000.Q
|
||
# nEXP_SPACE & !BG_030 & CLK_000 & SM_AMIGA_7_.Q & AS_030.PIN);
|
||
|
||
BG_000.AP = (!RST);
|
||
|
||
BG_000.C = (CLK_OSZI);
|
||
|
||
BGACK_030.D = (BGACK_000 & BGACK_030.Q
|
||
# BGACK_000 & AVEC_EXP.Q);
|
||
|
||
BGACK_030.AP = (!RST);
|
||
|
||
BGACK_030.C = (CLK_OSZI);
|
||
|
||
CLK_EXP.AR = (!RST);
|
||
|
||
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
|
||
|
||
CLK_EXP.C = (CLK_OSZI);
|
||
|
||
DSACK1.OE = (nEXP_SPACE);
|
||
|
||
!DSACK1.D = (SM_AMIGA_1_.Q & CLK_000_N_SYNC_6_.Q
|
||
# BERR & !DSACK1.Q & !AS_030.PIN);
|
||
|
||
DSACK1.AP = (!RST);
|
||
|
||
DSACK1.C = (CLK_OSZI);
|
||
|
||
IPL_030_1_.D = (IPL_1_ & AVEC_EXP.Q
|
||
# !AVEC_EXP.Q & IPL_030_1_.Q);
|
||
|
||
IPL_030_1_.AP = (!RST);
|
||
|
||
IPL_030_1_.C = (CLK_OSZI);
|
||
|
||
AVEC_EXP.AR = (!RST);
|
||
|
||
AVEC_EXP.D = (CLK_000_P_SYNC_9_.Q);
|
||
|
||
AVEC_EXP.C = (CLK_OSZI);
|
||
|
||
IPL_030_0_.D = (IPL_0_ & AVEC_EXP.Q
|
||
# !AVEC_EXP.Q & IPL_030_0_.Q);
|
||
|
||
IPL_030_0_.AP = (!RST);
|
||
|
||
IPL_030_0_.C = (CLK_OSZI);
|
||
|
||
E.AR = (!RST);
|
||
|
||
!E.D = (!AVEC_EXP.Q & !E.Q
|
||
# cpu_est_2_.Q & !E.Q
|
||
# AVEC_EXP.Q & cpu_est_1_.Q & cpu_est_2_.Q
|
||
# !cpu_est_0_.Q & cpu_est_1_.Q & !E.Q);
|
||
|
||
E.C = (CLK_OSZI);
|
||
|
||
VMA.D.X1 = (VMA.Q
|
||
# !VMA.Q & inst_CLK_000_D0.Q & AS_000.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q);
|
||
|
||
VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q);
|
||
|
||
VMA.AP = (!RST);
|
||
|
||
VMA.C = (CLK_OSZI);
|
||
|
||
RESET.AR = (!RST);
|
||
|
||
RESET.D = (1);
|
||
|
||
RESET.C = (CLK_OSZI);
|
||
|
||
RW.OE = (!BGACK_030.Q);
|
||
|
||
!RW.D = (CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !UDS_000.PIN
|
||
# !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN
|
||
# CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !LDS_000.PIN
|
||
# !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN);
|
||
|
||
RW.AP = (!RST);
|
||
|
||
RW.C = (CLK_OSZI);
|
||
|
||
!AMIGA_BUS_ENABLE.D = (!BGACK_030.Q
|
||
# !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN
|
||
# !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN
|
||
# !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_NE.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q
|
||
# !AMIGA_BUS_ENABLE.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q
|
||
# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q);
|
||
|
||
AMIGA_BUS_ENABLE.AP = (!RST);
|
||
|
||
AMIGA_BUS_ENABLE.C = (CLK_OSZI);
|
||
|
||
AMIGA_BUS_ENABLE_LOW.AR = (!RST);
|
||
|
||
AMIGA_BUS_ENABLE_LOW.D = (!AMIGA_BUS_ENABLE_LOW.Q);
|
||
|
||
AMIGA_BUS_ENABLE_LOW.C = (!CLK_PRE_66_0);
|
||
|
||
inst_AS_030_000_SYNC.D = (!BERR
|
||
# AS_030.PIN
|
||
# !nEXP_SPACE & inst_AS_030_000_SYNC.Q
|
||
# !BGACK_030.Q & inst_AS_030_000_SYNC.Q
|
||
# inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q
|
||
# FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q);
|
||
|
||
inst_AS_030_000_SYNC.AP = (!RST);
|
||
|
||
inst_AS_030_000_SYNC.C = (CLK_OSZI);
|
||
|
||
inst_BGACK_030_INT_D.D = (BGACK_030.Q);
|
||
|
||
inst_BGACK_030_INT_D.AP = (!RST);
|
||
|
||
inst_BGACK_030_INT_D.C = (CLK_OSZI);
|
||
|
||
inst_VPA_D.D = (VPA);
|
||
|
||
inst_VPA_D.AP = (!RST);
|
||
|
||
inst_VPA_D.C = (CLK_OSZI);
|
||
|
||
inst_CLK_OUT_PRE_50_D.AR = (!RST);
|
||
|
||
inst_CLK_OUT_PRE_50_D.D = (inst_CLK_OUT_PRE_50.Q);
|
||
|
||
inst_CLK_OUT_PRE_50_D.C = (CLK_OSZI);
|
||
|
||
inst_CLK_000_D0.D = (CLK_000);
|
||
|
||
inst_CLK_000_D0.AP = (!RST);
|
||
|
||
inst_CLK_000_D0.C = (CLK_OSZI);
|
||
|
||
CLK_CNT_N_0_.AR = (!RST);
|
||
|
||
CLK_CNT_N_0_.D = (CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q
|
||
# !CLK_CNT_N_0_.Q & !CLK_CNT_N_1_.Q);
|
||
|
||
CLK_CNT_N_0_.C = (!CLK_OSZI);
|
||
|
||
inst_CLK_OUT_PRE_50.AR = (!RST);
|
||
|
||
inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
|
||
|
||
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
|
||
|
||
inst_CLK_OUT_PRE_25.AR = (!RST);
|
||
|
||
inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q
|
||
# !inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
|
||
# !inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q);
|
||
|
||
inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
|
||
|
||
inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
|
||
|
||
inst_CLK_000_D1.AP = (!RST);
|
||
|
||
inst_CLK_000_D1.C = (CLK_OSZI);
|
||
|
||
inst_CLK_000_D2.D = (inst_CLK_000_D1.Q);
|
||
|
||
inst_CLK_000_D2.AP = (!RST);
|
||
|
||
inst_CLK_000_D2.C = (CLK_OSZI);
|
||
|
||
inst_CLK_000_D3.D = (inst_CLK_000_D2.Q);
|
||
|
||
inst_CLK_000_D3.AP = (!RST);
|
||
|
||
inst_CLK_000_D3.C = (CLK_OSZI);
|
||
|
||
inst_CLK_000_NE.AR = (!RST);
|
||
|
||
inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);
|
||
|
||
inst_CLK_000_NE.C = (CLK_OSZI);
|
||
|
||
inst_CLK_OUT_PRE_D.AR = (!RST);
|
||
|
||
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE.Q);
|
||
|
||
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
|
||
|
||
inst_CLK_OUT_PRE.AR = (!RST);
|
||
|
||
inst_CLK_OUT_PRE.D = (inst_CLK_OUT_PRE_25.Q);
|
||
|
||
inst_CLK_OUT_PRE.C = (CLK_OSZI);
|
||
|
||
CLK_000_P_SYNC_9_.AR = (!RST);
|
||
|
||
CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
|
||
|
||
CLK_000_P_SYNC_9_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_11_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);
|
||
|
||
CLK_000_N_SYNC_11_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_7_.D = (SM_AMIGA_7__0
|
||
# !BERR & SM_AMIGA_0_.Q
|
||
# !BERR & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q
|
||
# !BERR & !AVEC_EXP.Q & SM_AMIGA_6_.Q
|
||
# !BERR & !AVEC_EXP.Q & SM_AMIGA_4_.Q
|
||
# !BERR & !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q
|
||
# !BERR & !inst_CLK_000_NE.Q & SM_AMIGA_3_.Q
|
||
# !BERR & !AVEC_EXP.Q & SM_AMIGA_2_.Q
|
||
# !BERR & !VPA & VMA.Q & SM_AMIGA_3_.Q
|
||
# !BERR & !VPA & SM_AMIGA_3_.Q & cpu_est_1_.Q
|
||
# !BERR & !VPA & SM_AMIGA_3_.Q & !E.Q
|
||
# !BERR & VPA & SM_AMIGA_3_.Q & DTACK.PIN
|
||
# !nEXP_SPACE & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
|
||
|
||
SM_AMIGA_7_.AP = (!RST);
|
||
|
||
SM_AMIGA_7_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_1_.AR = (!RST);
|
||
|
||
SM_AMIGA_1_.D = (AVEC_EXP.Q & SM_AMIGA_2_.Q
|
||
# BERR & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q);
|
||
|
||
SM_AMIGA_1_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_0_.AR = (!RST);
|
||
|
||
SM_AMIGA_0_.D = (BERR & !AVEC_EXP.Q & SM_AMIGA_0_.Q
|
||
# inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q);
|
||
|
||
SM_AMIGA_0_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_6_.AR = (!RST);
|
||
|
||
SM_AMIGA_6_.D = (BERR & !AVEC_EXP.Q & SM_AMIGA_6_.Q
|
||
# nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_7_.Q);
|
||
|
||
SM_AMIGA_6_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_4_.AR = (!RST);
|
||
|
||
SM_AMIGA_4_.D = (inst_CLK_000_NE.Q & SM_AMIGA_5_.Q
|
||
# BERR & !AVEC_EXP.Q & SM_AMIGA_4_.Q);
|
||
|
||
SM_AMIGA_4_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_6_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q);
|
||
|
||
CLK_000_N_SYNC_6_.C = (CLK_OSZI);
|
||
|
||
CLK_CNT_P_1_.AR = (!RST);
|
||
|
||
CLK_CNT_P_1_.D = (CLK_CNT_P_0_.Q);
|
||
|
||
CLK_CNT_P_1_.C = (CLK_OSZI);
|
||
|
||
CLK_CNT_N_1_.D = (CLK_CNT_N_0_.Q);
|
||
|
||
CLK_CNT_N_1_.AP = (!RST);
|
||
|
||
CLK_CNT_N_1_.C = (!CLK_OSZI);
|
||
|
||
inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q
|
||
# !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
|
||
# !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
|
||
# CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !UDS_000.PIN
|
||
# CLK_030 & RST & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !LDS_000.PIN);
|
||
|
||
inst_CLK_030_H.C = (CLK_OSZI);
|
||
|
||
CLK_CNT_P_0_.AR = (!RST);
|
||
|
||
CLK_CNT_P_0_.D = (CLK_CNT_P_1_.Q & CLK_CNT_P_0_.Q
|
||
# !CLK_CNT_P_1_.Q & !CLK_CNT_P_0_.Q);
|
||
|
||
CLK_CNT_P_0_.C = (CLK_OSZI);
|
||
|
||
inst_LDS_000_INT.D = (inst_LDS_000_INT.Q & DS_030.PIN
|
||
# !DS_030.PIN & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);
|
||
|
||
inst_LDS_000_INT.AP = (!RST);
|
||
|
||
inst_LDS_000_INT.C = (CLK_OSZI);
|
||
|
||
inst_DS_000_ENABLE.AR = (!RST);
|
||
|
||
inst_DS_000_ENABLE.D = (AVEC_EXP.Q & SM_AMIGA_4_.Q
|
||
# BERR & inst_DS_000_ENABLE.Q & !AS_030.PIN
|
||
# AVEC_EXP.Q & SM_AMIGA_6_.Q & RW.PIN);
|
||
|
||
inst_DS_000_ENABLE.C = (CLK_OSZI);
|
||
|
||
inst_UDS_000_INT.D = (inst_UDS_000_INT.Q & DS_030.PIN
|
||
# !DS_030.PIN & A0.PIN);
|
||
|
||
inst_UDS_000_INT.AP = (!RST);
|
||
|
||
inst_UDS_000_INT.C = (CLK_OSZI);
|
||
|
||
CLK_000_P_SYNC_0_.AR = (!RST);
|
||
|
||
CLK_000_P_SYNC_0_.D = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !inst_CLK_000_D2.Q & !inst_CLK_000_D3.Q);
|
||
|
||
CLK_000_P_SYNC_0_.C = (CLK_OSZI);
|
||
|
||
CLK_000_P_SYNC_1_.AR = (!RST);
|
||
|
||
CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);
|
||
|
||
CLK_000_P_SYNC_1_.C = (CLK_OSZI);
|
||
|
||
CLK_000_P_SYNC_2_.AR = (!RST);
|
||
|
||
CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);
|
||
|
||
CLK_000_P_SYNC_2_.C = (CLK_OSZI);
|
||
|
||
CLK_000_P_SYNC_3_.AR = (!RST);
|
||
|
||
CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);
|
||
|
||
CLK_000_P_SYNC_3_.C = (CLK_OSZI);
|
||
|
||
CLK_000_P_SYNC_4_.AR = (!RST);
|
||
|
||
CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);
|
||
|
||
CLK_000_P_SYNC_4_.C = (CLK_OSZI);
|
||
|
||
CLK_000_P_SYNC_5_.AR = (!RST);
|
||
|
||
CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);
|
||
|
||
CLK_000_P_SYNC_5_.C = (CLK_OSZI);
|
||
|
||
CLK_000_P_SYNC_6_.AR = (!RST);
|
||
|
||
CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);
|
||
|
||
CLK_000_P_SYNC_6_.C = (CLK_OSZI);
|
||
|
||
CLK_000_P_SYNC_7_.AR = (!RST);
|
||
|
||
CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);
|
||
|
||
CLK_000_P_SYNC_7_.C = (CLK_OSZI);
|
||
|
||
CLK_000_P_SYNC_8_.AR = (!RST);
|
||
|
||
CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
|
||
|
||
CLK_000_P_SYNC_8_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_0_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_0_.D = (!inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & inst_CLK_000_D2.Q & inst_CLK_000_D3.Q);
|
||
|
||
CLK_000_N_SYNC_0_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_1_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);
|
||
|
||
CLK_000_N_SYNC_1_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_2_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q);
|
||
|
||
CLK_000_N_SYNC_2_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_3_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q);
|
||
|
||
CLK_000_N_SYNC_3_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_4_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);
|
||
|
||
CLK_000_N_SYNC_4_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_5_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);
|
||
|
||
CLK_000_N_SYNC_5_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_7_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q);
|
||
|
||
CLK_000_N_SYNC_7_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_8_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q);
|
||
|
||
CLK_000_N_SYNC_8_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_9_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q);
|
||
|
||
CLK_000_N_SYNC_9_.C = (CLK_OSZI);
|
||
|
||
CLK_000_N_SYNC_10_.AR = (!RST);
|
||
|
||
CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);
|
||
|
||
CLK_000_N_SYNC_10_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_5_.AR = (!RST);
|
||
|
||
SM_AMIGA_5_.D = (AVEC_EXP.Q & SM_AMIGA_6_.Q
|
||
# BERR & !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q);
|
||
|
||
SM_AMIGA_5_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_3_.AR = (!RST);
|
||
|
||
SM_AMIGA_3_.D = (AVEC_EXP.Q & SM_AMIGA_4_.Q
|
||
# BERR & !inst_CLK_000_NE.Q & SM_AMIGA_3_.Q
|
||
# BERR & !VPA & VMA.Q & SM_AMIGA_3_.Q
|
||
# BERR & !VPA & SM_AMIGA_3_.Q & cpu_est_1_.Q
|
||
# BERR & !VPA & SM_AMIGA_3_.Q & !E.Q
|
||
# BERR & VPA & SM_AMIGA_3_.Q & DTACK.PIN);
|
||
|
||
SM_AMIGA_3_.C = (CLK_OSZI);
|
||
|
||
SM_AMIGA_2_.AR = (!RST);
|
||
|
||
SM_AMIGA_2_.D = (BERR & !AVEC_EXP.Q & SM_AMIGA_2_.Q
|
||
# VPA & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !DTACK.PIN
|
||
# !VPA & !VMA.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q);
|
||
|
||
SM_AMIGA_2_.C = (CLK_OSZI);
|
||
|
||
cpu_est_0_.AR = (!RST);
|
||
|
||
cpu_est_0_.D = (!AVEC_EXP.Q & cpu_est_0_.Q
|
||
# AVEC_EXP.Q & !cpu_est_0_.Q);
|
||
|
||
cpu_est_0_.C = (CLK_OSZI);
|
||
|
||
cpu_est_1_.AR = (!RST);
|
||
|
||
cpu_est_1_.D = (!AVEC_EXP.Q & cpu_est_1_.Q
|
||
# !cpu_est_0_.Q & cpu_est_1_.Q
|
||
# AVEC_EXP.Q & cpu_est_0_.Q & !cpu_est_1_.Q
|
||
# AVEC_EXP.Q & cpu_est_2_.Q & E.Q
|
||
# AVEC_EXP.Q & !cpu_est_2_.Q & !E.Q);
|
||
|
||
cpu_est_1_.C = (CLK_OSZI);
|
||
|
||
cpu_est_2_.AR = (!RST);
|
||
|
||
cpu_est_2_.D = (!AVEC_EXP.Q & cpu_est_2_.Q
|
||
# cpu_est_1_.Q & cpu_est_2_.Q
|
||
# AVEC_EXP.Q & !cpu_est_0_.Q & !cpu_est_1_.Q
|
||
# AVEC_EXP.Q & cpu_est_0_.Q & E.Q);
|
||
|
||
cpu_est_2_.C = (CLK_OSZI);
|
||
|
||
!CLK_PRE_66_0 = (CLK_CNT_P_1_.Q & CLK_CNT_N_1_.Q
|
||
# !CLK_CNT_N_0_.Q & CLK_CNT_P_0_.Q);
|
||
|
||
SM_AMIGA_7__0 = (AVEC_EXP.Q & SM_AMIGA_0_.Q
|
||
# inst_AS_030_000_SYNC.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||
# inst_CLK_000_D0.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||
# !inst_CLK_000_D1.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
|
||
|
||
|
||
Reverse-Polarity Equations:
|
||
|