68030tk/Logic/BUS68030.bl1

#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Mon Jun 09 20:20:30 2014
#$ MODULE bus68030
#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 \
#  LDS_000 SIZE_0_ A0 A_30_ nEXP_SPACE A_29_ BERR A_28_ BG_030 A_27_ BG_000 A_26_ BGACK_030 \
#  A_25_ BGACK_000 A_24_ CLK_030 A_23_ CLK_000 A_22_ CLK_OSZI A_21_ CLK_DIV_OUT A_20_ \
#  CLK_EXP A_19_ FPU_CS A_18_ DSACK1 A_17_ DTACK A_16_ AVEC IPL_030_1_ AVEC_EXP IPL_030_0_ E \
#  IPL_1_ VPA IPL_0_ VMA FC_0_ RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
#  AMIGA_BUS_ENABLE_LOW CIIN
#$ NODES 491 a_i_20__n un19_fpu_cs_1 a_i_23__n un19_fpu_cs_2 cpu_est_i_2__n \
#  un19_fpu_cs_3 VPA_D_i SM_AMIGA_0_sqmuxa_1_1 clk_cnt_n_i_0__n \
#  DS_000_ENABLE_0_sqmuxa_1 a_i_30__n AS_030_000_SYNC_0_sqmuxa_1 \
#  inst_BGACK_030_INTreg a_i_31__n AS_030_000_SYNC_0_sqmuxa_2 vcc_n_n a_i_28__n \
#  N_102_1 inst_avec_expreg a_i_29__n N_101_1 inst_VMA_INTreg a_i_26__n N_100_1 \
#  inst_AMIGA_BUS_ENABLE_INTreg a_i_27__n N_110_1 inst_CLK_OUT_PRE_33reg a_i_24__n \
#  N_104_1 inst_AS_030_000_SYNC a_i_25__n N_104_2 inst_BGACK_030_INT_D N_104_3 \
#  inst_AS_000_DMA RST_i state_machine_un10_clk_000_ne_1_n inst_VPA_D \
#  sm_amiga_ns_0_1_0__n inst_CLK_OUT_PRE_50_D sm_amiga_ns_0_2_0__n inst_CLK_000_D0 \
#  CLK_OSZI_i sm_amiga_ns_0_3_0__n CLK_CNT_N_0_ cpu_est_ns_0_1_2__n \
#  inst_CLK_OUT_PRE_50 CLK_OUT_PRE_50_D_i N_30_1 inst_CLK_OUT_PRE_25 AS_030_c N_222_1 \
#  inst_CLK_000_D1 cpu_estse_1_un3_n inst_CLK_000_D2 AS_000_c cpu_estse_1_un1_n \
#  inst_CLK_000_D3 cpu_estse_1_un0_n inst_CLK_000_NE RW_000_c ipl_030_0_2__un3_n \
#  inst_CLK_OUT_PRE_D ipl_030_0_2__un1_n inst_CLK_OUT_PRE DS_030_c ipl_030_0_2__un0_n \
#  CLK_000_P_SYNC_9_ ipl_030_0_1__un3_n CLK_000_N_SYNC_11_ UDS_000_c \
#  ipl_030_0_1__un1_n state_machine_un10_clk_000_d0_n ipl_030_0_1__un0_n \
#  inst_AS_000_INT LDS_000_c ipl_030_0_0__un3_n SM_AMIGA_7_ ipl_030_0_0__un1_n \
#  SM_AMIGA_1_ size_c_0__n ipl_030_0_0__un0_n SM_AMIGA_0_ rw_000_int_0_un3_n \
#  SM_AMIGA_6_ size_c_1__n rw_000_int_0_un1_n SM_AMIGA_4_ rw_000_int_0_un0_n \
#  CLK_000_N_SYNC_6_ a_c_16__n dsack1_int_0_un3_n CLK_CNT_P_1_ dsack1_int_0_un1_n \
#  CLK_CNT_N_1_ a_c_17__n dsack1_int_0_un0_n inst_RW_000_INT ds_000_enable_0_un3_n \
#  inst_DSACK1_INT a_c_18__n ds_000_enable_0_un1_n \
#  state_machine_un3_clk_out_pre_50_n ds_000_enable_0_un0_n inst_CLK_030_H a_c_19__n \
#  as_000_int_0_un3_n CLK_CNT_P_0_ as_000_int_0_un1_n inst_RW_000_DMA a_c_20__n \
#  as_000_int_0_un0_n un1_LDS_000_INT as_030_000_sync_0_un3_n inst_LDS_000_INT \
#  a_c_21__n as_030_000_sync_0_un1_n inst_DS_000_ENABLE as_030_000_sync_0_un0_n \
#  un1_UDS_000_INT a_c_22__n bgack_030_int_0_un3_n inst_UDS_000_INT \
#  bgack_030_int_0_un1_n a_c_23__n bgack_030_int_0_un0_n as_000_dma_0_un3_n \
#  state_machine_un12_clk_000_d0_n a_c_24__n as_000_dma_0_un1_n as_000_dma_0_un0_n \
#  inst_DS_000_DMA a_c_25__n ds_000_dma_0_un3_n SIZE_DMA_0_ ds_000_dma_0_un1_n \
#  SIZE_DMA_1_ a_c_26__n ds_000_dma_0_un0_n inst_A0_DMA rw_000_dma_0_un3_n G_109 \
#  a_c_27__n rw_000_dma_0_un1_n G_115 rw_000_dma_0_un0_n CLK_000_P_SYNC_0_ a_c_28__n \
#  clk_030_h_0_un3_n CLK_000_P_SYNC_1_ clk_030_h_0_un1_n CLK_000_P_SYNC_2_ a_c_29__n \
#  clk_030_h_0_un0_n CLK_000_P_SYNC_3_ amiga_bus_enable_int_0_un3_n \
#  CLK_000_P_SYNC_4_ a_c_30__n amiga_bus_enable_int_0_un1_n CLK_000_P_SYNC_5_ \
#  amiga_bus_enable_int_0_un0_n CLK_000_P_SYNC_6_ a_c_31__n bg_000_0_un3_n \
#  CLK_000_P_SYNC_7_ bg_000_0_un1_n CLK_000_P_SYNC_8_ A0_c bg_000_0_un0_n \
#  CLK_000_N_SYNC_0_ lds_000_int_0_un3_n CLK_000_N_SYNC_1_ nEXP_SPACE_c \
#  lds_000_int_0_un1_n CLK_000_N_SYNC_2_ lds_000_int_0_un0_n CLK_000_N_SYNC_3_ BERR_c \
#  uds_000_int_0_un3_n CLK_000_N_SYNC_4_ uds_000_int_0_un1_n CLK_000_N_SYNC_5_ \
#  BG_030_c uds_000_int_0_un0_n CLK_000_N_SYNC_7_ vma_int_0_un3_n CLK_000_N_SYNC_8_ \
#  BG_000DFFSHreg vma_int_0_un1_n CLK_000_N_SYNC_9_ vma_int_0_un0_n \
#  CLK_000_N_SYNC_10_ cpu_estse_0_un3_n un28_ciin BGACK_000_c cpu_estse_0_un1_n \
#  un19_fpu_cs cpu_estse_0_un0_n SM_AMIGA_5_ CLK_030_c cpu_estse_2_un3_n SM_AMIGA_3_ \
#  cpu_estse_2_un1_n SM_AMIGA_2_ CLK_000_c cpu_estse_2_un0_n CLK_OSZI_c CLK_OUT_INTreg \
#  IPL_030DFFSH_0_reg IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg ipl_c_0__n ipl_c_1__n \
#  CLK_OUT_PRE_25_0 ipl_c_2__n DSACK1_c DTACK_c VPA_c cpu_est_0_ RST_c cpu_est_1_ \
#  cpu_est_2_ RESETDFFRHreg cpu_est_3_reg RW_c fc_c_0__n cpu_est_ns_1__n fc_c_1__n \
#  cpu_est_ns_2__n un6_clk_pre_66 un2_clk_pre_66 AMIGA_BUS_DATA_DIR_c N_222 N_37 N_223 \
#  N_224 SM_AMIGA_0_sqmuxa_i N_227 DS_000_ENABLE_0_sqmuxa_i N_219 \
#  un1_SM_AMIGA_0_sqmuxa_2_i N_228 state_machine_un10_clk_000_ne_i_n N_229 \
#  state_machine_un4_clk_000_ne_i_n N_230 state_machine_un6_clk_000_ne_i_n N_28 \
#  state_machine_rw_000_int_3_0_n N_29 N_75_0 N_30 sm_amiga_ns_0_0__n un28_ciin_0_x2 \
#  N_105_i N_31 N_106_i N_220 sm_amiga_ns_0_1__n N_32 N_107_i N_35 sm_amiga_ns_0_2__n \
#  state_machine_un5_clk_000_n_sync_n N_110_i N_178 sm_amiga_ns_0_4__n N_179 N_114_i \
#  N_179_1 N_113_i un19_fpu_cs_5 sm_amiga_ns_0_6__n state_machine_un28_as_030_n N_91_i \
#  N_247 N_92_i state_machine_un8_bgack_030_int_n sm_amiga_i_5__n \
#  state_machine_un10_bgack_030_int_n N_93_i CLK_030_H_1_sqmuxa N_95_0 \
#  AS_000_DMA_1_sqmuxa N_103_i DS_000_DMA_1_sqmuxa N_100_i DS_000_DMA_1_sqmuxa_1 \
#  N_102_i state_machine_un24_bgack_030_int_n N_101_i state_machine_clk_030_h_2_n \
#  N_104_i state_machine_clk_030_h_2_f1_n state_machine_un4_bgack_000_0_n \
#  state_machine_un31_bgack_030_int_n N_33_i state_machine_ds_000_dma_3_n N_220_0 \
#  un1_bgack_030_int_d state_machine_un3_bgack_030_int_d_i_n \
#  un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa un1_bgack_030_int_d_0 \
#  state_machine_un10_bg_030_n AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \
#  state_machine_un3_bgack_030_int_d_n AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i \
#  AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 sm_amiga_i_6__n SM_AMIGA_0_sqmuxa_1 N_96_i \
#  AMIGA_BUS_ENABLE_INT_3_sqmuxa sm_amiga_i_2__n N_98 sm_amiga_i_4__n \
#  AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 N_115_i state_machine_un8_bg_030_n \
#  AMIGA_BUS_ENABLE_INT_2_sqmuxa N_111_i N_103 N_112_i N_91 sm_amiga_ns_0_5__n N_109 \
#  N_109_i N_112 N_108_i N_115 sm_amiga_ns_0_3__n N_95 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \
#  N_108 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_111 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 \
#  N_96 BG_030_c_i state_machine_un4_bgack_000_n state_machine_un8_bg_030_i_n N_33 \
#  state_machine_un10_bg_030_0_n DS_000_ENABLE_0_sqmuxa \
#  state_machine_un5_bgack_030_int_d_i_n AS_030_000_SYNC_0_sqmuxa \
#  state_machine_un10_bgack_030_int_0_n un2_as_030 state_machine_ds_000_dma_3_0_n \
#  un1_AS_030_000_SYNC_0_sqmuxa_1_1 state_machine_size_dma_4_0_0__n \
#  un1_SM_AMIGA_0_sqmuxa_2 state_machine_size_dma_4_0_1__n \
#  un1_AS_030_000_SYNC_0_sqmuxa_1 CLK_030_H_i N_102 CLK_030_H_1_sqmuxa_i N_92 \
#  state_machine_clk_030_h_2_f1_0_n N_101 un3_dtack_i N_93 cpu_est_ns_0_1__n N_100 \
#  N_37_i N_110 N_224_i N_107 N_32_i N_114_1 N_223_i N_104 N_178_i N_114 N_179_i \
#  state_machine_un10_clk_000_ne_n AMIGA_BUS_DATA_DIR_c_0 \
#  state_machine_un6_clk_000_ne_n N_219_i N_113 N_30_i SM_AMIGA_0_sqmuxa N_31_i N_99 \
#  un28_ciin_0 N_105 N_28_i N_106 N_29_i N_75 cpu_est_ns_e_0_0__n \
#  state_machine_rw_000_int_3_n N_228_i state_machine_un4_clk_000_ne_n N_229_i \
#  DSACK1_INT_1_sqmuxa N_230_i DSACK1_INT_0_sqmuxa cpu_est_ns_0_2__n \
#  AS_000_INT_1_sqmuxa N_35_i un19_fpu_cs_i N_227_i \
#  un1_AS_030_000_SYNC_0_sqmuxa_1_1_i N_164_i N_99_i N_222_i DSACK1_INT_0_sqmuxa_i \
#  state_machine_un10_clk_000_d0_i_n DTACK_i state_machine_un12_clk_000_d0_0_n \
#  BERR_i un2_clk_pre_66_i CLK_000_NE_i un6_clk_pre_66_i sm_amiga_i_1__n CLK_PRE_66_0 \
#  VPA_i LDS_000_INT_i VMA_INT_i un1_LDS_000_INT_0 sm_amiga_i_0__n UDS_000_INT_i \
#  SM_AMIGA_0_sqmuxa_1_i un1_UDS_000_INT_0 sm_amiga_i_3__n \
#  state_machine_un7_ds_030_i_n avec_exp_i A0_c_i AS_030_i size_c_i_1__n \
#  AS_030_000_SYNC_0_sqmuxa_i un3_dtack_i_1 AS_030_000_SYNC_i N_247_1 a_i_16__n \
#  N_247_2 a_i_19__n N_247_3 a_i_17__n N_247_4 a_i_18__n N_247_5 sm_amiga_i_7__n N_247_6 \
#  N_98_i state_machine_un7_ds_030_i_1_n BGACK_030_INT_i N_31_1 BGACK_030_INT_D_i \
#  N_31_2 DS_000_DMA_1_sqmuxa_1_i N_179_1_0 state_machine_un8_bgack_030_int_i_n \
#  state_machine_clk_000_p_sync_3_1_0__n CLK_030_i \
#  state_machine_clk_000_p_sync_3_2_0__n UDS_000_i state_machine_un28_as_030_1_n \
#  LDS_000_i state_machine_un28_as_030_2_n state_machine_un31_bgack_030_int_i_n \
#  state_machine_clk_000_n_sync_2_1_0__n RW_000_i cpu_est_ns_0_1_1__n \
#  state_machine_un24_bgack_030_int_i_n cpu_est_ns_0_2_1__n AS_000_DMA_i \
#  state_machine_un10_clk_000_d0_1_n CLK_000_D2_i state_machine_un10_clk_000_d0_2_n \
#  CLK_000_D3_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_000_D1_i \
#  AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_as_030_i_n N_96_i_1 \
#  nEXP_SPACE_i state_machine_un8_bg_030_1_n AS_000_i state_machine_un8_bg_030_2_n \
#  RW_i un1_bgack_030_int_d_0_1 CLK_000_D0_i N_33_1 cpu_est_i_3__n N_33_2 \
#  cpu_est_i_1__n un19_fpu_cs_5_1 cpu_est_i_0__n un19_fpu_cs_5_2
.model bus68030
.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BERR.BLIF \
BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF \
RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \
A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \
A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF \
AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF \
A0.BLIF DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF a_i_20__n.BLIF \
un19_fpu_cs_1.BLIF a_i_23__n.BLIF un19_fpu_cs_2.BLIF cpu_est_i_2__n.BLIF \
un19_fpu_cs_3.BLIF VPA_D_i.BLIF SM_AMIGA_0_sqmuxa_1_1.BLIF \
clk_cnt_n_i_0__n.BLIF DS_000_ENABLE_0_sqmuxa_1.BLIF a_i_30__n.BLIF \
AS_030_000_SYNC_0_sqmuxa_1.BLIF inst_BGACK_030_INTreg.BLIF a_i_31__n.BLIF \
AS_030_000_SYNC_0_sqmuxa_2.BLIF vcc_n_n.BLIF a_i_28__n.BLIF N_102_1.BLIF \
inst_avec_expreg.BLIF a_i_29__n.BLIF N_101_1.BLIF inst_VMA_INTreg.BLIF \
a_i_26__n.BLIF N_100_1.BLIF inst_AMIGA_BUS_ENABLE_INTreg.BLIF a_i_27__n.BLIF \
N_110_1.BLIF inst_CLK_OUT_PRE_33reg.BLIF a_i_24__n.BLIF N_104_1.BLIF \
inst_AS_030_000_SYNC.BLIF a_i_25__n.BLIF N_104_2.BLIF \
inst_BGACK_030_INT_D.BLIF N_104_3.BLIF inst_AS_000_DMA.BLIF RST_i.BLIF \
state_machine_un10_clk_000_ne_1_n.BLIF inst_VPA_D.BLIF \
sm_amiga_ns_0_1_0__n.BLIF inst_CLK_OUT_PRE_50_D.BLIF sm_amiga_ns_0_2_0__n.BLIF \
inst_CLK_000_D0.BLIF CLK_OSZI_i.BLIF sm_amiga_ns_0_3_0__n.BLIF \
CLK_CNT_N_0_.BLIF cpu_est_ns_0_1_2__n.BLIF inst_CLK_OUT_PRE_50.BLIF \
CLK_OUT_PRE_50_D_i.BLIF N_30_1.BLIF inst_CLK_OUT_PRE_25.BLIF AS_030_c.BLIF \
N_222_1.BLIF inst_CLK_000_D1.BLIF cpu_estse_1_un3_n.BLIF inst_CLK_000_D2.BLIF \
AS_000_c.BLIF cpu_estse_1_un1_n.BLIF inst_CLK_000_D3.BLIF \
cpu_estse_1_un0_n.BLIF inst_CLK_000_NE.BLIF RW_000_c.BLIF \
ipl_030_0_2__un3_n.BLIF inst_CLK_OUT_PRE_D.BLIF ipl_030_0_2__un1_n.BLIF \
inst_CLK_OUT_PRE.BLIF DS_030_c.BLIF ipl_030_0_2__un0_n.BLIF \
CLK_000_P_SYNC_9_.BLIF ipl_030_0_1__un3_n.BLIF CLK_000_N_SYNC_11_.BLIF \
UDS_000_c.BLIF ipl_030_0_1__un1_n.BLIF state_machine_un10_clk_000_d0_n.BLIF \
ipl_030_0_1__un0_n.BLIF inst_AS_000_INT.BLIF LDS_000_c.BLIF \
ipl_030_0_0__un3_n.BLIF SM_AMIGA_7_.BLIF ipl_030_0_0__un1_n.BLIF \
SM_AMIGA_1_.BLIF size_c_0__n.BLIF ipl_030_0_0__un0_n.BLIF SM_AMIGA_0_.BLIF \
rw_000_int_0_un3_n.BLIF SM_AMIGA_6_.BLIF size_c_1__n.BLIF \
rw_000_int_0_un1_n.BLIF SM_AMIGA_4_.BLIF rw_000_int_0_un0_n.BLIF \
CLK_000_N_SYNC_6_.BLIF a_c_16__n.BLIF dsack1_int_0_un3_n.BLIF \
CLK_CNT_P_1_.BLIF dsack1_int_0_un1_n.BLIF CLK_CNT_N_1_.BLIF a_c_17__n.BLIF \
dsack1_int_0_un0_n.BLIF inst_RW_000_INT.BLIF ds_000_enable_0_un3_n.BLIF \
inst_DSACK1_INT.BLIF a_c_18__n.BLIF ds_000_enable_0_un1_n.BLIF \
state_machine_un3_clk_out_pre_50_n.BLIF ds_000_enable_0_un0_n.BLIF \
inst_CLK_030_H.BLIF a_c_19__n.BLIF as_000_int_0_un3_n.BLIF CLK_CNT_P_0_.BLIF \
as_000_int_0_un1_n.BLIF inst_RW_000_DMA.BLIF a_c_20__n.BLIF \
as_000_int_0_un0_n.BLIF un1_LDS_000_INT.BLIF as_030_000_sync_0_un3_n.BLIF \
inst_LDS_000_INT.BLIF a_c_21__n.BLIF as_030_000_sync_0_un1_n.BLIF \
inst_DS_000_ENABLE.BLIF as_030_000_sync_0_un0_n.BLIF un1_UDS_000_INT.BLIF \
a_c_22__n.BLIF bgack_030_int_0_un3_n.BLIF inst_UDS_000_INT.BLIF \
bgack_030_int_0_un1_n.BLIF a_c_23__n.BLIF bgack_030_int_0_un0_n.BLIF \
as_000_dma_0_un3_n.BLIF state_machine_un12_clk_000_d0_n.BLIF a_c_24__n.BLIF \
as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_DS_000_DMA.BLIF \
a_c_25__n.BLIF ds_000_dma_0_un3_n.BLIF SIZE_DMA_0_.BLIF \
ds_000_dma_0_un1_n.BLIF SIZE_DMA_1_.BLIF a_c_26__n.BLIF \
ds_000_dma_0_un0_n.BLIF inst_A0_DMA.BLIF rw_000_dma_0_un3_n.BLIF G_109.BLIF \
a_c_27__n.BLIF rw_000_dma_0_un1_n.BLIF G_115.BLIF rw_000_dma_0_un0_n.BLIF \
CLK_000_P_SYNC_0_.BLIF a_c_28__n.BLIF clk_030_h_0_un3_n.BLIF \
CLK_000_P_SYNC_1_.BLIF clk_030_h_0_un1_n.BLIF CLK_000_P_SYNC_2_.BLIF \
a_c_29__n.BLIF clk_030_h_0_un0_n.BLIF CLK_000_P_SYNC_3_.BLIF \
amiga_bus_enable_int_0_un3_n.BLIF CLK_000_P_SYNC_4_.BLIF a_c_30__n.BLIF \
amiga_bus_enable_int_0_un1_n.BLIF CLK_000_P_SYNC_5_.BLIF \
amiga_bus_enable_int_0_un0_n.BLIF CLK_000_P_SYNC_6_.BLIF a_c_31__n.BLIF \
bg_000_0_un3_n.BLIF CLK_000_P_SYNC_7_.BLIF bg_000_0_un1_n.BLIF \
CLK_000_P_SYNC_8_.BLIF A0_c.BLIF bg_000_0_un0_n.BLIF CLK_000_N_SYNC_0_.BLIF \
lds_000_int_0_un3_n.BLIF CLK_000_N_SYNC_1_.BLIF nEXP_SPACE_c.BLIF \
lds_000_int_0_un1_n.BLIF CLK_000_N_SYNC_2_.BLIF lds_000_int_0_un0_n.BLIF \
CLK_000_N_SYNC_3_.BLIF BERR_c.BLIF uds_000_int_0_un3_n.BLIF \
CLK_000_N_SYNC_4_.BLIF uds_000_int_0_un1_n.BLIF CLK_000_N_SYNC_5_.BLIF \
BG_030_c.BLIF uds_000_int_0_un0_n.BLIF CLK_000_N_SYNC_7_.BLIF \
vma_int_0_un3_n.BLIF CLK_000_N_SYNC_8_.BLIF BG_000DFFSHreg.BLIF \
vma_int_0_un1_n.BLIF CLK_000_N_SYNC_9_.BLIF vma_int_0_un0_n.BLIF \
CLK_000_N_SYNC_10_.BLIF cpu_estse_0_un3_n.BLIF un28_ciin.BLIF BGACK_000_c.BLIF \
cpu_estse_0_un1_n.BLIF un19_fpu_cs.BLIF cpu_estse_0_un0_n.BLIF \
SM_AMIGA_5_.BLIF CLK_030_c.BLIF cpu_estse_2_un3_n.BLIF SM_AMIGA_3_.BLIF \
cpu_estse_2_un1_n.BLIF SM_AMIGA_2_.BLIF CLK_000_c.BLIF cpu_estse_2_un0_n.BLIF \
CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \
IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_2_reg.BLIF ipl_c_0__n.BLIF \
ipl_c_1__n.BLIF CLK_OUT_PRE_25_0.BLIF ipl_c_2__n.BLIF DSACK1_c.BLIF \
DTACK_c.BLIF VPA_c.BLIF cpu_est_0_.BLIF RST_c.BLIF cpu_est_1_.BLIF \
cpu_est_2_.BLIF RESETDFFRHreg.BLIF cpu_est_3_reg.BLIF RW_c.BLIF fc_c_0__n.BLIF \
cpu_est_ns_1__n.BLIF fc_c_1__n.BLIF cpu_est_ns_2__n.BLIF un6_clk_pre_66.BLIF \
un2_clk_pre_66.BLIF AMIGA_BUS_DATA_DIR_c.BLIF N_222.BLIF N_37.BLIF N_223.BLIF \
N_224.BLIF SM_AMIGA_0_sqmuxa_i.BLIF N_227.BLIF DS_000_ENABLE_0_sqmuxa_i.BLIF \
N_219.BLIF un1_SM_AMIGA_0_sqmuxa_2_i.BLIF N_228.BLIF \
state_machine_un10_clk_000_ne_i_n.BLIF N_229.BLIF \
state_machine_un4_clk_000_ne_i_n.BLIF N_230.BLIF \
state_machine_un6_clk_000_ne_i_n.BLIF N_28.BLIF \
state_machine_rw_000_int_3_0_n.BLIF N_29.BLIF N_75_0.BLIF N_30.BLIF \
sm_amiga_ns_0_0__n.BLIF un28_ciin_0_x2.BLIF N_105_i.BLIF N_31.BLIF \
N_106_i.BLIF N_220.BLIF sm_amiga_ns_0_1__n.BLIF N_32.BLIF N_107_i.BLIF \
N_35.BLIF sm_amiga_ns_0_2__n.BLIF state_machine_un5_clk_000_n_sync_n.BLIF \
N_110_i.BLIF N_178.BLIF sm_amiga_ns_0_4__n.BLIF N_179.BLIF N_114_i.BLIF \
N_179_1.BLIF N_113_i.BLIF un19_fpu_cs_5.BLIF sm_amiga_ns_0_6__n.BLIF \
state_machine_un28_as_030_n.BLIF N_91_i.BLIF N_247.BLIF N_92_i.BLIF \
state_machine_un8_bgack_030_int_n.BLIF sm_amiga_i_5__n.BLIF \
state_machine_un10_bgack_030_int_n.BLIF N_93_i.BLIF CLK_030_H_1_sqmuxa.BLIF \
N_95_0.BLIF AS_000_DMA_1_sqmuxa.BLIF N_103_i.BLIF DS_000_DMA_1_sqmuxa.BLIF \
N_100_i.BLIF DS_000_DMA_1_sqmuxa_1.BLIF N_102_i.BLIF \
state_machine_un24_bgack_030_int_n.BLIF N_101_i.BLIF \
state_machine_clk_030_h_2_n.BLIF N_104_i.BLIF \
state_machine_clk_030_h_2_f1_n.BLIF state_machine_un4_bgack_000_0_n.BLIF \
state_machine_un31_bgack_030_int_n.BLIF N_33_i.BLIF \
state_machine_ds_000_dma_3_n.BLIF N_220_0.BLIF un1_bgack_030_int_d.BLIF \
state_machine_un3_bgack_030_int_d_i_n.BLIF \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF un1_bgack_030_int_d_0.BLIF \
state_machine_un10_bg_030_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \
state_machine_un3_bgack_030_int_d_n.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF \
sm_amiga_i_6__n.BLIF SM_AMIGA_0_sqmuxa_1.BLIF N_96_i.BLIF \
AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF sm_amiga_i_2__n.BLIF N_98.BLIF \
sm_amiga_i_4__n.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF N_115_i.BLIF \
state_machine_un8_bg_030_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \
N_111_i.BLIF N_103.BLIF N_112_i.BLIF N_91.BLIF sm_amiga_ns_0_5__n.BLIF \
N_109.BLIF N_109_i.BLIF N_112.BLIF N_108_i.BLIF N_115.BLIF \
sm_amiga_ns_0_3__n.BLIF N_95.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF \
N_108.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF N_111.BLIF \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF N_96.BLIF BG_030_c_i.BLIF \
state_machine_un4_bgack_000_n.BLIF state_machine_un8_bg_030_i_n.BLIF N_33.BLIF \
state_machine_un10_bg_030_0_n.BLIF DS_000_ENABLE_0_sqmuxa.BLIF \
state_machine_un5_bgack_030_int_d_i_n.BLIF AS_030_000_SYNC_0_sqmuxa.BLIF \
state_machine_un10_bgack_030_int_0_n.BLIF un2_as_030.BLIF \
state_machine_ds_000_dma_3_0_n.BLIF un1_AS_030_000_SYNC_0_sqmuxa_1_1.BLIF \
state_machine_size_dma_4_0_0__n.BLIF un1_SM_AMIGA_0_sqmuxa_2.BLIF \
state_machine_size_dma_4_0_1__n.BLIF un1_AS_030_000_SYNC_0_sqmuxa_1.BLIF \
CLK_030_H_i.BLIF N_102.BLIF CLK_030_H_1_sqmuxa_i.BLIF N_92.BLIF \
state_machine_clk_030_h_2_f1_0_n.BLIF N_101.BLIF un3_dtack_i.BLIF N_93.BLIF \
cpu_est_ns_0_1__n.BLIF N_100.BLIF N_37_i.BLIF N_110.BLIF N_224_i.BLIF \
N_107.BLIF N_32_i.BLIF N_114_1.BLIF N_223_i.BLIF N_104.BLIF N_178_i.BLIF \
N_114.BLIF N_179_i.BLIF state_machine_un10_clk_000_ne_n.BLIF \
AMIGA_BUS_DATA_DIR_c_0.BLIF state_machine_un6_clk_000_ne_n.BLIF N_219_i.BLIF \
N_113.BLIF N_30_i.BLIF SM_AMIGA_0_sqmuxa.BLIF N_31_i.BLIF N_99.BLIF \
un28_ciin_0.BLIF N_105.BLIF N_28_i.BLIF N_106.BLIF N_29_i.BLIF N_75.BLIF \
cpu_est_ns_e_0_0__n.BLIF state_machine_rw_000_int_3_n.BLIF N_228_i.BLIF \
state_machine_un4_clk_000_ne_n.BLIF N_229_i.BLIF DSACK1_INT_1_sqmuxa.BLIF \
N_230_i.BLIF DSACK1_INT_0_sqmuxa.BLIF cpu_est_ns_0_2__n.BLIF \
AS_000_INT_1_sqmuxa.BLIF N_35_i.BLIF un19_fpu_cs_i.BLIF N_227_i.BLIF \
un1_AS_030_000_SYNC_0_sqmuxa_1_1_i.BLIF N_164_i.BLIF N_99_i.BLIF N_222_i.BLIF \
DSACK1_INT_0_sqmuxa_i.BLIF state_machine_un10_clk_000_d0_i_n.BLIF DTACK_i.BLIF \
state_machine_un12_clk_000_d0_0_n.BLIF BERR_i.BLIF un2_clk_pre_66_i.BLIF \
CLK_000_NE_i.BLIF un6_clk_pre_66_i.BLIF sm_amiga_i_1__n.BLIF CLK_PRE_66_0.BLIF \
VPA_i.BLIF LDS_000_INT_i.BLIF VMA_INT_i.BLIF un1_LDS_000_INT_0.BLIF \
sm_amiga_i_0__n.BLIF UDS_000_INT_i.BLIF SM_AMIGA_0_sqmuxa_1_i.BLIF \
un1_UDS_000_INT_0.BLIF sm_amiga_i_3__n.BLIF state_machine_un7_ds_030_i_n.BLIF \
avec_exp_i.BLIF A0_c_i.BLIF AS_030_i.BLIF size_c_i_1__n.BLIF \
AS_030_000_SYNC_0_sqmuxa_i.BLIF un3_dtack_i_1.BLIF AS_030_000_SYNC_i.BLIF \
N_247_1.BLIF a_i_16__n.BLIF N_247_2.BLIF a_i_19__n.BLIF N_247_3.BLIF \
a_i_17__n.BLIF N_247_4.BLIF a_i_18__n.BLIF N_247_5.BLIF sm_amiga_i_7__n.BLIF \
N_247_6.BLIF N_98_i.BLIF state_machine_un7_ds_030_i_1_n.BLIF \
BGACK_030_INT_i.BLIF N_31_1.BLIF BGACK_030_INT_D_i.BLIF N_31_2.BLIF \
DS_000_DMA_1_sqmuxa_1_i.BLIF N_179_1_0.BLIF \
state_machine_un8_bgack_030_int_i_n.BLIF \
state_machine_clk_000_p_sync_3_1_0__n.BLIF CLK_030_i.BLIF \
state_machine_clk_000_p_sync_3_2_0__n.BLIF UDS_000_i.BLIF \
state_machine_un28_as_030_1_n.BLIF LDS_000_i.BLIF \
state_machine_un28_as_030_2_n.BLIF state_machine_un31_bgack_030_int_i_n.BLIF \
state_machine_clk_000_n_sync_2_1_0__n.BLIF RW_000_i.BLIF \
cpu_est_ns_0_1_1__n.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \
cpu_est_ns_0_2_1__n.BLIF AS_000_DMA_i.BLIF \
state_machine_un10_clk_000_d0_1_n.BLIF CLK_000_D2_i.BLIF \
state_machine_un10_clk_000_d0_2_n.BLIF CLK_000_D3_i.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_000_D1_i.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF state_machine_un28_as_030_i_n.BLIF \
N_96_i_1.BLIF nEXP_SPACE_i.BLIF state_machine_un8_bg_030_1_n.BLIF \
AS_000_i.BLIF state_machine_un8_bg_030_2_n.BLIF RW_i.BLIF \
un1_bgack_030_int_d_0_1.BLIF CLK_000_D0_i.BLIF N_33_1.BLIF cpu_est_i_3__n.BLIF \
N_33_2.BLIF cpu_est_i_1__n.BLIF un19_fpu_cs_5_1.BLIF cpu_est_i_0__n.BLIF \
un19_fpu_cs_5_2.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \
DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF
.outputs IPL_030_2_ BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC AVEC_EXP \
E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN \
IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.D \
cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR \
cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_7_.D SM_AMIGA_7_.C \
SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \
SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \
SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \
SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \
SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \
CLK_000_N_SYNC_6_.AR CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \
CLK_000_N_SYNC_7_.AR CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C \
CLK_000_N_SYNC_8_.AR CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C \
CLK_000_N_SYNC_9_.AR CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \
CLK_000_N_SYNC_10_.AR CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C \
CLK_000_N_SYNC_11_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR \
CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AP CLK_CNT_P_0_.D CLK_CNT_P_0_.C \
CLK_CNT_P_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR SIZE_DMA_0_.D \
SIZE_DMA_0_.C SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP \
IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \
IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \
IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP \
CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_1_.AR \
CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_2_.AR \
CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_3_.AR \
CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_4_.AR \
CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_5_.AR \
CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_6_.AR \
CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_7_.AR \
CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_8_.AR \
CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_9_.AR \
CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_0_.AR \
CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_1_.AR \
CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_2_.AR \
CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_3_.AR \
CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_4_.AR \
CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_5_.AR \
inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR \
inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \
CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_0_.AR inst_AS_000_INT.D \
inst_AS_000_INT.C inst_AS_000_INT.AP inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \
inst_DS_000_ENABLE.AR BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \
inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_LDS_000_INT.D \
inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_UDS_000_INT.D inst_UDS_000_INT.C \
inst_UDS_000_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP \
inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_A0_DMA.D \
inst_A0_DMA.C inst_A0_DMA.AP inst_CLK_030_H.D inst_CLK_030_H.C \
inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_DMA.AP inst_DS_000_DMA.D \
inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C \
inst_AS_000_DMA.AP inst_AMIGA_BUS_ENABLE_INTreg.D \
inst_AMIGA_BUS_ENABLE_INTreg.C inst_AMIGA_BUS_ENABLE_INTreg.AP \
inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \
inst_CLK_OUT_PRE_33reg.D inst_CLK_OUT_PRE_33reg.C inst_CLK_OUT_PRE_33reg.AR \
inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D3.D \
inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \
inst_CLK_000_D2.AP RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR \
CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D1.D \
inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D \
inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D \
inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_OUT_PRE_D.D \
inst_CLK_OUT_PRE_D.C inst_CLK_OUT_PRE_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C \
inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP inst_avec_expreg.D \
inst_avec_expreg.C inst_avec_expreg.AR inst_CLK_000_NE.D inst_CLK_000_NE.C \
inst_CLK_000_NE.AR inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
inst_CLK_OUT_PRE_50.AR SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 \
DSACK1 DTACK RW SIZE_0_ a_i_20__n un19_fpu_cs_1 a_i_23__n un19_fpu_cs_2 \
cpu_est_i_2__n un19_fpu_cs_3 VPA_D_i SM_AMIGA_0_sqmuxa_1_1 clk_cnt_n_i_0__n \
DS_000_ENABLE_0_sqmuxa_1 a_i_30__n AS_030_000_SYNC_0_sqmuxa_1 a_i_31__n \
AS_030_000_SYNC_0_sqmuxa_2 vcc_n_n a_i_28__n N_102_1 a_i_29__n N_101_1 \
a_i_26__n N_100_1 a_i_27__n N_110_1 a_i_24__n N_104_1 a_i_25__n N_104_2 \
N_104_3 RST_i state_machine_un10_clk_000_ne_1_n sm_amiga_ns_0_1_0__n \
sm_amiga_ns_0_2_0__n CLK_OSZI_i sm_amiga_ns_0_3_0__n cpu_est_ns_0_1_2__n \
CLK_OUT_PRE_50_D_i N_30_1 AS_030_c N_222_1 cpu_estse_1_un3_n AS_000_c \
cpu_estse_1_un1_n cpu_estse_1_un0_n RW_000_c ipl_030_0_2__un3_n \
ipl_030_0_2__un1_n DS_030_c ipl_030_0_2__un0_n ipl_030_0_1__un3_n UDS_000_c \
ipl_030_0_1__un1_n state_machine_un10_clk_000_d0_n ipl_030_0_1__un0_n \
LDS_000_c ipl_030_0_0__un3_n ipl_030_0_0__un1_n size_c_0__n ipl_030_0_0__un0_n \
rw_000_int_0_un3_n size_c_1__n rw_000_int_0_un1_n rw_000_int_0_un0_n a_c_16__n \
dsack1_int_0_un3_n dsack1_int_0_un1_n a_c_17__n dsack1_int_0_un0_n \
ds_000_enable_0_un3_n a_c_18__n ds_000_enable_0_un1_n \
state_machine_un3_clk_out_pre_50_n ds_000_enable_0_un0_n a_c_19__n \
as_000_int_0_un3_n as_000_int_0_un1_n a_c_20__n as_000_int_0_un0_n \
un1_LDS_000_INT as_030_000_sync_0_un3_n a_c_21__n as_030_000_sync_0_un1_n \
as_030_000_sync_0_un0_n un1_UDS_000_INT a_c_22__n bgack_030_int_0_un3_n \
bgack_030_int_0_un1_n a_c_23__n bgack_030_int_0_un0_n as_000_dma_0_un3_n \
state_machine_un12_clk_000_d0_n a_c_24__n as_000_dma_0_un1_n \
as_000_dma_0_un0_n a_c_25__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_26__n \
ds_000_dma_0_un0_n rw_000_dma_0_un3_n a_c_27__n rw_000_dma_0_un1_n \
rw_000_dma_0_un0_n a_c_28__n clk_030_h_0_un3_n clk_030_h_0_un1_n a_c_29__n \
clk_030_h_0_un0_n amiga_bus_enable_int_0_un3_n a_c_30__n \
amiga_bus_enable_int_0_un1_n amiga_bus_enable_int_0_un0_n a_c_31__n \
bg_000_0_un3_n bg_000_0_un1_n A0_c bg_000_0_un0_n lds_000_int_0_un3_n \
nEXP_SPACE_c lds_000_int_0_un1_n lds_000_int_0_un0_n BERR_c \
uds_000_int_0_un3_n uds_000_int_0_un1_n BG_030_c uds_000_int_0_un0_n \
vma_int_0_un3_n vma_int_0_un1_n vma_int_0_un0_n cpu_estse_0_un3_n un28_ciin \
BGACK_000_c cpu_estse_0_un1_n un19_fpu_cs cpu_estse_0_un0_n CLK_030_c \
cpu_estse_2_un3_n cpu_estse_2_un1_n CLK_000_c cpu_estse_2_un0_n CLK_OSZI_c \
ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c DTACK_c VPA_c RST_c RW_c fc_c_0__n \
cpu_est_ns_1__n fc_c_1__n cpu_est_ns_2__n un6_clk_pre_66 un2_clk_pre_66 \
AMIGA_BUS_DATA_DIR_c N_222 N_37 N_223 N_224 SM_AMIGA_0_sqmuxa_i N_227 \
DS_000_ENABLE_0_sqmuxa_i N_219 un1_SM_AMIGA_0_sqmuxa_2_i N_228 \
state_machine_un10_clk_000_ne_i_n N_229 state_machine_un4_clk_000_ne_i_n N_230 \
state_machine_un6_clk_000_ne_i_n N_28 state_machine_rw_000_int_3_0_n N_29 \
N_75_0 N_30 sm_amiga_ns_0_0__n N_105_i N_31 N_106_i N_220 sm_amiga_ns_0_1__n \
N_32 N_107_i N_35 sm_amiga_ns_0_2__n state_machine_un5_clk_000_n_sync_n \
N_110_i N_178 sm_amiga_ns_0_4__n N_179 N_114_i N_179_1 N_113_i un19_fpu_cs_5 \
sm_amiga_ns_0_6__n state_machine_un28_as_030_n N_91_i N_247 N_92_i \
state_machine_un8_bgack_030_int_n sm_amiga_i_5__n \
state_machine_un10_bgack_030_int_n N_93_i CLK_030_H_1_sqmuxa N_95_0 \
AS_000_DMA_1_sqmuxa N_103_i DS_000_DMA_1_sqmuxa N_100_i DS_000_DMA_1_sqmuxa_1 \
N_102_i state_machine_un24_bgack_030_int_n N_101_i state_machine_clk_030_h_2_n \
N_104_i state_machine_clk_030_h_2_f1_n state_machine_un4_bgack_000_0_n \
state_machine_un31_bgack_030_int_n N_33_i state_machine_ds_000_dma_3_n N_220_0 \
un1_bgack_030_int_d state_machine_un3_bgack_030_int_d_i_n \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa un1_bgack_030_int_d_0 \
state_machine_un10_bg_030_n AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \
state_machine_un3_bgack_030_int_d_n AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 sm_amiga_i_6__n SM_AMIGA_0_sqmuxa_1 N_96_i \
AMIGA_BUS_ENABLE_INT_3_sqmuxa sm_amiga_i_2__n N_98 sm_amiga_i_4__n \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 N_115_i state_machine_un8_bg_030_n \
AMIGA_BUS_ENABLE_INT_2_sqmuxa N_111_i N_103 N_112_i N_91 sm_amiga_ns_0_5__n \
N_109 N_109_i N_112 N_108_i N_115 sm_amiga_ns_0_3__n N_95 \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_i N_108 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_111 \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 N_96 BG_030_c_i \
state_machine_un4_bgack_000_n state_machine_un8_bg_030_i_n N_33 \
state_machine_un10_bg_030_0_n DS_000_ENABLE_0_sqmuxa \
state_machine_un5_bgack_030_int_d_i_n AS_030_000_SYNC_0_sqmuxa \
state_machine_un10_bgack_030_int_0_n un2_as_030 state_machine_ds_000_dma_3_0_n \
un1_AS_030_000_SYNC_0_sqmuxa_1_1 state_machine_size_dma_4_0_0__n \
un1_SM_AMIGA_0_sqmuxa_2 state_machine_size_dma_4_0_1__n \
un1_AS_030_000_SYNC_0_sqmuxa_1 CLK_030_H_i N_102 CLK_030_H_1_sqmuxa_i N_92 \
state_machine_clk_030_h_2_f1_0_n N_101 un3_dtack_i N_93 cpu_est_ns_0_1__n \
N_100 N_37_i N_110 N_224_i N_107 N_32_i N_114_1 N_223_i N_104 N_178_i N_114 \
N_179_i state_machine_un10_clk_000_ne_n AMIGA_BUS_DATA_DIR_c_0 \
state_machine_un6_clk_000_ne_n N_219_i N_113 N_30_i SM_AMIGA_0_sqmuxa N_31_i \
N_99 un28_ciin_0 N_105 N_28_i N_106 N_29_i N_75 cpu_est_ns_e_0_0__n \
state_machine_rw_000_int_3_n N_228_i state_machine_un4_clk_000_ne_n N_229_i \
DSACK1_INT_1_sqmuxa N_230_i DSACK1_INT_0_sqmuxa cpu_est_ns_0_2__n \
AS_000_INT_1_sqmuxa N_35_i un19_fpu_cs_i N_227_i \
un1_AS_030_000_SYNC_0_sqmuxa_1_1_i N_164_i N_99_i N_222_i \
DSACK1_INT_0_sqmuxa_i state_machine_un10_clk_000_d0_i_n DTACK_i \
state_machine_un12_clk_000_d0_0_n BERR_i un2_clk_pre_66_i CLK_000_NE_i \
un6_clk_pre_66_i sm_amiga_i_1__n CLK_PRE_66_0 VPA_i LDS_000_INT_i VMA_INT_i \
un1_LDS_000_INT_0 sm_amiga_i_0__n UDS_000_INT_i SM_AMIGA_0_sqmuxa_1_i \
un1_UDS_000_INT_0 sm_amiga_i_3__n state_machine_un7_ds_030_i_n avec_exp_i \
A0_c_i AS_030_i size_c_i_1__n AS_030_000_SYNC_0_sqmuxa_i un3_dtack_i_1 \
AS_030_000_SYNC_i N_247_1 a_i_16__n N_247_2 a_i_19__n N_247_3 a_i_17__n \
N_247_4 a_i_18__n N_247_5 sm_amiga_i_7__n N_247_6 N_98_i \
state_machine_un7_ds_030_i_1_n BGACK_030_INT_i N_31_1 BGACK_030_INT_D_i N_31_2 \
DS_000_DMA_1_sqmuxa_1_i N_179_1_0 state_machine_un8_bgack_030_int_i_n \
state_machine_clk_000_p_sync_3_1_0__n CLK_030_i \
state_machine_clk_000_p_sync_3_2_0__n UDS_000_i state_machine_un28_as_030_1_n \
LDS_000_i state_machine_un28_as_030_2_n state_machine_un31_bgack_030_int_i_n \
state_machine_clk_000_n_sync_2_1_0__n RW_000_i cpu_est_ns_0_1_1__n \
state_machine_un24_bgack_030_int_i_n cpu_est_ns_0_2_1__n AS_000_DMA_i \
state_machine_un10_clk_000_d0_1_n CLK_000_D2_i \
state_machine_un10_clk_000_d0_2_n CLK_000_D3_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \
CLK_000_D1_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_as_030_i_n \
N_96_i_1 nEXP_SPACE_i state_machine_un8_bg_030_1_n AS_000_i \
state_machine_un8_bg_030_2_n RW_i un1_bgack_030_int_d_0_1 CLK_000_D0_i N_33_1 \
cpu_est_i_3__n N_33_2 cpu_est_i_1__n un19_fpu_cs_5_1 cpu_est_i_0__n \
un19_fpu_cs_5_2 AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE \
SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE CIIN.OE G_109 G_115 \
CLK_OUT_PRE_25_0 un28_ciin_0_x2
.names cpu_est_ns_e_0_0__n.BLIF cpu_est_0_.D
0 1
.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D
1- 1
-1 1
.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D
1- 1
-1 1
.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D
1- 1
-1 1
.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D
0 1
.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D
0 1
.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D
0 1
.names sm_amiga_ns_0_3__n.BLIF SM_AMIGA_4_.D
0 1
.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D
0 1
.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
0 1
.names sm_amiga_ns_0_6__n.BLIF SM_AMIGA_1_.D
0 1
.names N_103_i.BLIF N_115_i.BLIF SM_AMIGA_0_.D
11 1
.names G_109.BLIF CLK_CNT_N_0_.D
0 1
.names G_115.BLIF CLK_CNT_P_0_.D
0 1
.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D
0 1
.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D
0 1
.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D
1- 1
-1 1
.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D
1- 1
-1 1
.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D
1- 1
-1 1
.names state_machine_clk_000_n_sync_2_1_0__n.BLIF \
state_machine_un5_clk_000_n_sync_n.BLIF CLK_000_N_SYNC_0_.D
11 1
.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \
inst_BGACK_030_INTreg.D
1- 1
-1 1
.names state_machine_clk_000_p_sync_3_1_0__n.BLIF \
state_machine_clk_000_p_sync_3_2_0__n.BLIF CLK_000_P_SYNC_0_.D
11 1
.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D
1- 1
-1 1
.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF \
inst_DS_000_ENABLE.D
1- 1
-1 1
.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D
1- 1
-1 1
.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D
1- 1
-1 1
.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D
1- 1
-1 1
.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D
1- 1
-1 1
.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D
1- 1
-1 1
.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D
1- 1
-1 1
.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D
11 1
.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D
1- 1
-1 1
.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF inst_RW_000_DMA.D
1- 1
-1 1
.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D
1- 1
-1 1
.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D
1- 1
-1 1
.names amiga_bus_enable_int_0_un1_n.BLIF amiga_bus_enable_int_0_un0_n.BLIF \
inst_AMIGA_BUS_ENABLE_INTreg.D
1- 1
-1 1
.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \
inst_AS_030_000_SYNC.D
1- 1
-1 1
.names inst_CLK_OUT_PRE_33reg.BLIF inst_CLK_OUT_PRE_33reg.D
0 1
.names CLK_PRE_66_0.BLIF inst_CLK_OUT_PRE_33reg.C
0 1
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
0 1
.names a_c_20__n.BLIF a_i_20__n
0 1
.names AS_030_i.BLIF a_i_16__n.BLIF un19_fpu_cs_1
11 1
.names a_c_23__n.BLIF a_i_23__n
0 1
.names a_i_18__n.BLIF a_i_19__n.BLIF un19_fpu_cs_2
11 1
.names cpu_est_2_.BLIF cpu_est_i_2__n
0 1
.names un19_fpu_cs_1.BLIF un19_fpu_cs_2.BLIF un19_fpu_cs_3
11 1
.names inst_VPA_D.BLIF VPA_D_i
0 1
.names AS_030_000_SYNC_i.BLIF nEXP_SPACE_c.BLIF SM_AMIGA_0_sqmuxa_1_1
11 1
.names CLK_CNT_N_0_.BLIF clk_cnt_n_i_0__n
0 1
.names RW_c.BLIF SM_AMIGA_6_.BLIF DS_000_ENABLE_0_sqmuxa_1
11 1
.names a_c_30__n.BLIF a_i_30__n
0 1
.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF AS_030_000_SYNC_0_sqmuxa_1
11 1
.names a_c_31__n.BLIF a_i_31__n
0 1
.names nEXP_SPACE_c.BLIF state_machine_un28_as_030_i_n.BLIF \
AS_030_000_SYNC_0_sqmuxa_2
11 1
.names vcc_n_n
 1
.names a_c_28__n.BLIF a_i_28__n
0 1
.names BERR_i.BLIF N_92.BLIF N_102_1
11 1
.names a_c_29__n.BLIF a_i_29__n
0 1
.names N_93.BLIF BERR_i.BLIF N_101_1
11 1
.names a_c_26__n.BLIF a_i_26__n
0 1
.names BERR_i.BLIF N_96.BLIF N_100_1
11 1
.names a_c_27__n.BLIF a_i_27__n
0 1
.names BERR_c.BLIF N_92.BLIF N_110_1
11 1
.names a_c_24__n.BLIF a_i_24__n
0 1
.names N_93_i.BLIF N_96_i.BLIF N_104_1
11 1
.names a_c_25__n.BLIF a_i_25__n
0 1
.names SM_AMIGA_0_sqmuxa_1_i.BLIF sm_amiga_i_0__n.BLIF N_104_2
11 1
.names N_104_1.BLIF N_104_2.BLIF N_104_3
11 1
.names RST_c.BLIF RST_i
0 1
.names VPA_i.BLIF N_219_i.BLIF state_machine_un10_clk_000_ne_1_n
11 1
.names N_101_i.BLIF N_102_i.BLIF sm_amiga_ns_0_1_0__n
11 1
.names N_104_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2_0__n
11 1
.names CLK_OSZI_c.BLIF CLK_OSZI_i
0 1
.names sm_amiga_ns_0_1_0__n.BLIF sm_amiga_ns_0_2_0__n.BLIF \
sm_amiga_ns_0_3_0__n
11 1
.names N_230_i.BLIF N_228_i.BLIF cpu_est_ns_0_1_2__n
11 1
.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i
0 1
.names un28_ciin_0_x2.BLIF a_i_20__n.BLIF N_30_1
11 1
.names CLK_000_D0_i.BLIF N_37.BLIF N_222_1
11 1
.names inst_avec_expreg.BLIF cpu_estse_1_un3_n
0 1
.names cpu_est_ns_2__n.BLIF inst_avec_expreg.BLIF cpu_estse_1_un1_n
11 1
.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n
11 1
.names inst_avec_expreg.BLIF ipl_030_0_2__un3_n
0 1
.names ipl_c_2__n.BLIF inst_avec_expreg.BLIF ipl_030_0_2__un1_n
11 1
.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
11 1
.names inst_avec_expreg.BLIF ipl_030_0_1__un3_n
0 1
.names ipl_c_1__n.BLIF inst_avec_expreg.BLIF ipl_030_0_1__un1_n
11 1
.names state_machine_un10_clk_000_d0_1_n.BLIF \
state_machine_un10_clk_000_d0_2_n.BLIF state_machine_un10_clk_000_d0_n
11 1
.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
11 1
.names inst_avec_expreg.BLIF ipl_030_0_0__un3_n
0 1
.names ipl_c_0__n.BLIF inst_avec_expreg.BLIF ipl_030_0_0__un1_n
11 1
.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
11 1
.names N_75.BLIF rw_000_int_0_un3_n
0 1
.names state_machine_rw_000_int_3_n.BLIF N_75.BLIF rw_000_int_0_un1_n
11 1
.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n
11 1
.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n
0 1
.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n
11 1
.names DSACK1_INT_0_sqmuxa_i.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
11 1
.names un2_as_030.BLIF ds_000_enable_0_un3_n
0 1
.names inst_DS_000_ENABLE.BLIF un2_as_030.BLIF ds_000_enable_0_un1_n
11 1
.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \
state_machine_un3_clk_out_pre_50_n
11 1
.names un1_SM_AMIGA_0_sqmuxa_2.BLIF ds_000_enable_0_un3_n.BLIF \
ds_000_enable_0_un0_n
11 1
.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
0 1
.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n
11 1
.names N_99_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
11 1
.names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT
0 1
.names un1_AS_030_000_SYNC_0_sqmuxa_1.BLIF as_030_000_sync_0_un3_n
0 1
.names inst_AS_030_000_SYNC.BLIF un1_AS_030_000_SYNC_0_sqmuxa_1.BLIF \
as_030_000_sync_0_un1_n
11 1
.names un1_AS_030_000_SYNC_0_sqmuxa_1_1_i.BLIF as_030_000_sync_0_un3_n.BLIF \
as_030_000_sync_0_un0_n
11 1
.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT
0 1
.names state_machine_un4_bgack_000_n.BLIF bgack_030_int_0_un3_n
0 1
.names BGACK_000_c.BLIF state_machine_un4_bgack_000_n.BLIF \
bgack_030_int_0_un1_n
11 1
.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \
bgack_030_int_0_un0_n
11 1
.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n
0 1
.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n
0 1
.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n
11 1
.names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF \
as_000_dma_0_un0_n
11 1
.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n
0 1
.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n
11 1
.names state_machine_ds_000_dma_3_n.BLIF ds_000_dma_0_un3_n.BLIF \
ds_000_dma_0_un0_n
11 1
.names AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un3_n
0 1
.names inst_RW_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF rw_000_dma_0_un1_n
11 1
.names DS_000_DMA_1_sqmuxa_1_i.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n
11 1
.names RST_c.BLIF clk_030_h_0_un3_n
0 1
.names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n
11 1
.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n
11 1
.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un3_n
0 1
.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF amiga_bus_enable_int_0_un1_n
11 1
.names un1_bgack_030_int_d.BLIF amiga_bus_enable_int_0_un3_n.BLIF \
amiga_bus_enable_int_0_un0_n
11 1
.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n
0 1
.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n
11 1
.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
11 1
.names DS_030_c.BLIF lds_000_int_0_un3_n
0 1
.names inst_LDS_000_INT.BLIF DS_030_c.BLIF lds_000_int_0_un1_n
11 1
.names state_machine_un7_ds_030_i_n.BLIF lds_000_int_0_un3_n.BLIF \
lds_000_int_0_un0_n
11 1
.names DS_030_c.BLIF uds_000_int_0_un3_n
0 1
.names inst_UDS_000_INT.BLIF DS_030_c.BLIF uds_000_int_0_un1_n
11 1
.names A0_c.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
11 1
.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n
0 1
.names state_machine_un10_clk_000_d0_n.BLIF \
state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n
11 1
.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
11 1
.names inst_avec_expreg.BLIF cpu_estse_0_un3_n
0 1
.names un28_ciin_0.BLIF un28_ciin
0 1
.names cpu_est_ns_1__n.BLIF inst_avec_expreg.BLIF cpu_estse_0_un1_n
11 1
.names un19_fpu_cs_3.BLIF un19_fpu_cs_5.BLIF un19_fpu_cs
11 1
.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n
11 1
.names inst_avec_expreg.BLIF cpu_estse_2_un3_n
0 1
.names N_164_i.BLIF inst_avec_expreg.BLIF cpu_estse_2_un1_n
11 1
.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n
11 1
.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n
0 1
.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n
0 1
.names CLK_CNT_N_1_.BLIF CLK_CNT_P_1_.BLIF un6_clk_pre_66
11 1
.names clk_cnt_n_i_0__n.BLIF CLK_CNT_P_0_.BLIF un2_clk_pre_66
11 1
.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
0 1
.names N_222_1.BLIF VPA_D_i.BLIF N_222
11 1
.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_37
11 1
.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_223
11 1
.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_224
11 1
.names SM_AMIGA_0_sqmuxa.BLIF SM_AMIGA_0_sqmuxa_i
0 1
.names N_219.BLIF cpu_est_2_.BLIF N_227
11 1
.names DS_000_ENABLE_0_sqmuxa.BLIF DS_000_ENABLE_0_sqmuxa_i
0 1
.names N_219_i.BLIF N_219
0 1
.names DS_000_ENABLE_0_sqmuxa_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF \
un1_SM_AMIGA_0_sqmuxa_2_i
11 1
.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_228
11 1
.names state_machine_un10_clk_000_ne_n.BLIF state_machine_un10_clk_000_ne_i_n
0 1
.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_229
11 1
.names state_machine_un4_clk_000_ne_n.BLIF state_machine_un4_clk_000_ne_i_n
0 1
.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_230
11 1
.names state_machine_un4_clk_000_ne_i_n.BLIF \
state_machine_un10_clk_000_ne_i_n.BLIF state_machine_un6_clk_000_ne_i_n
11 1
.names inst_avec_expreg.BLIF cpu_est_i_0__n.BLIF N_28
11 1
.names RW_i.BLIF sm_amiga_i_7__n.BLIF state_machine_rw_000_int_3_0_n
11 1
.names avec_exp_i.BLIF cpu_est_0_.BLIF N_29
11 1
.names N_99_i.BLIF sm_amiga_i_7__n.BLIF N_75_0
11 1
.names N_30_1.BLIF a_i_23__n.BLIF N_30
11 1
.names sm_amiga_ns_0_3_0__n.BLIF N_103_i.BLIF sm_amiga_ns_0_0__n
11 1
.names N_105.BLIF N_105_i
0 1
.names N_31_1.BLIF N_31_2.BLIF N_31
11 1
.names N_106.BLIF N_106_i
0 1
.names N_220_0.BLIF N_220
0 1
.names N_105_i.BLIF N_106_i.BLIF sm_amiga_ns_0_1__n
11 1
.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_32
11 1
.names N_107.BLIF N_107_i
0 1
.names N_32.BLIF cpu_est_i_3__n.BLIF N_35
11 1
.names N_99_i.BLIF N_107_i.BLIF sm_amiga_ns_0_2__n
11 1
.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF \
state_machine_un5_clk_000_n_sync_n
11 1
.names N_110.BLIF N_110_i
0 1
.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_178
11 1
.names N_110_i.BLIF SM_AMIGA_0_sqmuxa_i.BLIF sm_amiga_ns_0_4__n
11 1
.names N_179_1_0.BLIF nEXP_SPACE_i.BLIF N_179
11 1
.names N_114.BLIF N_114_i
0 1
.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_179_1
11 1
.names N_113.BLIF N_113_i
0 1
.names un19_fpu_cs_5_1.BLIF un19_fpu_cs_5_2.BLIF un19_fpu_cs_5
11 1
.names N_113_i.BLIF N_114_i.BLIF sm_amiga_ns_0_6__n
11 1
.names state_machine_un28_as_030_1_n.BLIF state_machine_un28_as_030_2_n.BLIF \
state_machine_un28_as_030_n
11 1
.names BERR_c.BLIF avec_exp_i.BLIF N_91_i
11 1
.names N_247_5.BLIF N_247_6.BLIF N_247
11 1
.names inst_CLK_000_NE.BLIF state_machine_un6_clk_000_ne_n.BLIF N_92_i
11 1
.names N_179_1.BLIF state_machine_un10_bgack_030_int_n.BLIF \
state_machine_un8_bgack_030_int_n
11 1
.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
0 1
.names state_machine_un10_bgack_030_int_0_n.BLIF \
state_machine_un10_bgack_030_int_n
0 1
.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_93_i
11 1
.names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa
11 1
.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_95_0
11 1
.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF \
AS_000_DMA_1_sqmuxa
11 1
.names N_103.BLIF N_103_i
0 1
.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \
DS_000_DMA_1_sqmuxa
11 1
.names N_100.BLIF N_100_i
0 1
.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \
DS_000_DMA_1_sqmuxa_1
11 1
.names N_102.BLIF N_102_i
0 1
.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n
11 1
.names N_101.BLIF N_101_i
0 1
.names state_machine_clk_030_h_2_f1_n.BLIF \
state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n
11 1
.names N_104.BLIF N_104_i
0 1
.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n
0 1
.names BGACK_000_c.BLIF avec_exp_i.BLIF state_machine_un4_bgack_000_0_n
11 1
.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n
11 1
.names N_33.BLIF N_33_i
0 1
.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n
0 1
.names a_i_20__n.BLIF N_33_i.BLIF N_220_0
11 1
.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d
0 1
.names state_machine_un3_bgack_030_int_d_n.BLIF \
state_machine_un3_bgack_030_int_d_i_n
0 1
.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \
un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa
0 1
.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \
un1_bgack_030_int_d_0
11 1
.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n
0 1
.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i
0 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF \
state_machine_un3_bgack_030_int_d_n
11 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i
0 1
.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_0_sqmuxa_1_i.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1
11 1
.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
0 1
.names SM_AMIGA_0_sqmuxa_1_1.BLIF state_machine_un5_clk_000_n_sync_n.BLIF \
SM_AMIGA_0_sqmuxa_1
11 1
.names N_96_i_1.BLIF sm_amiga_i_6__n.BLIF N_96_i
11 1
.names N_98_i.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \
AMIGA_BUS_ENABLE_INT_3_sqmuxa
11 1
.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
0 1
.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_98
11 1
.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
0 1
.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_2
11 1
.names N_115.BLIF N_115_i
0 1
.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF \
state_machine_un8_bg_030_n
11 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa
11 1
.names N_111.BLIF N_111_i
0 1
.names N_91.BLIF SM_AMIGA_0_.BLIF N_103
11 1
.names N_112.BLIF N_112_i
0 1
.names N_91_i.BLIF N_91
0 1
.names N_111_i.BLIF N_112_i.BLIF sm_amiga_ns_0_5__n
11 1
.names N_91_i.BLIF SM_AMIGA_4_.BLIF N_109
11 1
.names N_109.BLIF N_109_i
0 1
.names N_91_i.BLIF SM_AMIGA_2_.BLIF N_112
11 1
.names N_108.BLIF N_108_i
0 1
.names N_95.BLIF sm_amiga_i_0__n.BLIF N_115
11 1
.names N_108_i.BLIF N_109_i.BLIF sm_amiga_ns_0_3__n
11 1
.names N_95_0.BLIF N_95
0 1
.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i
0 1
.names inst_CLK_000_NE.BLIF SM_AMIGA_5_.BLIF N_108
11 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i
0 1
.names N_92_i.BLIF SM_AMIGA_3_.BLIF N_111
11 1
.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0
11 1
.names N_96_i.BLIF N_96
0 1
.names BG_030_c.BLIF BG_030_c_i
0 1
.names state_machine_un4_bgack_000_0_n.BLIF state_machine_un4_bgack_000_n
0 1
.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n
0 1
.names N_33_1.BLIF N_33_2.BLIF N_33
11 1
.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF \
state_machine_un10_bg_030_0_n
11 1
.names DS_000_ENABLE_0_sqmuxa_1.BLIF inst_avec_expreg.BLIF \
DS_000_ENABLE_0_sqmuxa
11 1
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
state_machine_un5_bgack_030_int_d_i_n
11 1
.names AS_030_000_SYNC_0_sqmuxa_1.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF \
AS_030_000_SYNC_0_sqmuxa
11 1
.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n
11 1
.names un1_AS_030_000_SYNC_0_sqmuxa_1_1.BLIF un1_SM_AMIGA_0_sqmuxa_2_i.BLIF \
un2_as_030
11 1
.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \
state_machine_ds_000_dma_3_0_n
11 1
.names AS_030_i.BLIF BERR_c.BLIF un1_AS_030_000_SYNC_0_sqmuxa_1_1
11 1
.names state_machine_un8_bgack_030_int_n.BLIF \
state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n
11 1
.names un1_SM_AMIGA_0_sqmuxa_2_i.BLIF un1_SM_AMIGA_0_sqmuxa_2
0 1
.names state_machine_un8_bgack_030_int_n.BLIF \
state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n
11 1
.names AS_030_000_SYNC_0_sqmuxa_i.BLIF un1_AS_030_000_SYNC_0_sqmuxa_1_1.BLIF \
un1_AS_030_000_SYNC_0_sqmuxa_1
11 1
.names inst_CLK_030_H.BLIF CLK_030_H_i
0 1
.names N_102_1.BLIF SM_AMIGA_3_.BLIF N_102
11 1
.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i
0 1
.names N_92_i.BLIF N_92
0 1
.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF \
state_machine_clk_030_h_2_f1_0_n
11 1
.names N_101_1.BLIF CLK_000_NE_i.BLIF N_101
11 1
.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i
11 1
.names N_93_i.BLIF N_93
0 1
.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n
11 1
.names N_100_1.BLIF avec_exp_i.BLIF N_100
11 1
.names N_37.BLIF N_37_i
0 1
.names N_110_1.BLIF SM_AMIGA_3_.BLIF N_110
11 1
.names N_224.BLIF N_224_i
0 1
.names N_114_1.BLIF SM_AMIGA_5_.BLIF N_107
11 1
.names N_32.BLIF N_32_i
0 1
.names BERR_c.BLIF CLK_000_NE_i.BLIF N_114_1
11 1
.names N_223.BLIF N_223_i
0 1
.names N_104_3.BLIF sm_amiga_i_3__n.BLIF N_104
11 1
.names N_178.BLIF N_178_i
0 1
.names N_114_1.BLIF SM_AMIGA_1_.BLIF N_114
11 1
.names N_179.BLIF N_179_i
0 1
.names state_machine_un10_clk_000_ne_1_n.BLIF VMA_INT_i.BLIF \
state_machine_un10_clk_000_ne_n
11 1
.names N_178_i.BLIF N_179_i.BLIF AMIGA_BUS_DATA_DIR_c_0
11 1
.names state_machine_un6_clk_000_ne_i_n.BLIF state_machine_un6_clk_000_ne_n
0 1
.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_219_i
11 1
.names SM_AMIGA_2_.BLIF inst_avec_expreg.BLIF N_113
11 1
.names N_30.BLIF N_30_i
0 1
.names SM_AMIGA_4_.BLIF inst_avec_expreg.BLIF SM_AMIGA_0_sqmuxa
11 1
.names N_31.BLIF N_31_i
0 1
.names SM_AMIGA_6_.BLIF inst_avec_expreg.BLIF N_99
11 1
.names N_30_i.BLIF N_31_i.BLIF un28_ciin_0
11 1
.names SM_AMIGA_7_.BLIF SM_AMIGA_0_sqmuxa_1.BLIF N_105
11 1
.names N_28.BLIF N_28_i
0 1
.names N_91_i.BLIF SM_AMIGA_6_.BLIF N_106
11 1
.names N_29.BLIF N_29_i
0 1
.names N_75_0.BLIF N_75
0 1
.names N_28_i.BLIF N_29_i.BLIF cpu_est_ns_e_0_0__n
11 1
.names state_machine_rw_000_int_3_0_n.BLIF state_machine_rw_000_int_3_n
0 1
.names N_228.BLIF N_228_i
0 1
.names DTACK_i.BLIF VPA_c.BLIF state_machine_un4_clk_000_ne_n
11 1
.names N_229.BLIF N_229_i
0 1
.names DSACK1_INT_0_sqmuxa_i.BLIF un1_AS_030_000_SYNC_0_sqmuxa_1_1.BLIF \
DSACK1_INT_1_sqmuxa
11 1
.names N_230.BLIF N_230_i
0 1
.names CLK_000_N_SYNC_6_.BLIF SM_AMIGA_1_.BLIF DSACK1_INT_0_sqmuxa
11 1
.names cpu_est_ns_0_1_2__n.BLIF N_229_i.BLIF cpu_est_ns_0_2__n
11 1
.names N_99_i.BLIF un1_AS_030_000_SYNC_0_sqmuxa_1_1.BLIF AS_000_INT_1_sqmuxa
11 1
.names N_35.BLIF N_35_i
0 1
.names un19_fpu_cs.BLIF un19_fpu_cs_i
0 1
.names N_227.BLIF N_227_i
0 1
.names un1_AS_030_000_SYNC_0_sqmuxa_1_1.BLIF \
un1_AS_030_000_SYNC_0_sqmuxa_1_1_i
0 1
.names N_35_i.BLIF N_227_i.BLIF N_164_i
11 1
.names N_99.BLIF N_99_i
0 1
.names N_222.BLIF N_222_i
0 1
.names DSACK1_INT_0_sqmuxa.BLIF DSACK1_INT_0_sqmuxa_i
0 1
.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n
0 1
.names DTACK_c.BLIF DTACK_i
0 1
.names N_222_i.BLIF state_machine_un10_clk_000_d0_i_n.BLIF \
state_machine_un12_clk_000_d0_0_n
11 1
.names BERR_c.BLIF BERR_i
0 1
.names un2_clk_pre_66.BLIF un2_clk_pre_66_i
0 1
.names inst_CLK_000_NE.BLIF CLK_000_NE_i
0 1
.names un6_clk_pre_66.BLIF un6_clk_pre_66_i
0 1
.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
0 1
.names un2_clk_pre_66_i.BLIF un6_clk_pre_66_i.BLIF CLK_PRE_66_0
11 1
.names VPA_c.BLIF VPA_i
0 1
.names inst_LDS_000_INT.BLIF LDS_000_INT_i
0 1
.names inst_VMA_INTreg.BLIF VMA_INT_i
0 1
.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0
11 1
.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
0 1
.names inst_UDS_000_INT.BLIF UDS_000_INT_i
0 1
.names SM_AMIGA_0_sqmuxa_1.BLIF SM_AMIGA_0_sqmuxa_1_i
0 1
.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0
11 1
.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
0 1
.names state_machine_un7_ds_030_i_1_n.BLIF size_c_0__n.BLIF \
state_machine_un7_ds_030_i_n
11 1
.names inst_avec_expreg.BLIF avec_exp_i
0 1
.names A0_c.BLIF A0_c_i
0 1
.names AS_030_c.BLIF AS_030_i
0 1
.names size_c_1__n.BLIF size_c_i_1__n
0 1
.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i
0 1
.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1
11 1
.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
0 1
.names a_i_24__n.BLIF a_i_25__n.BLIF N_247_1
11 1
.names a_c_16__n.BLIF a_i_16__n
0 1
.names a_i_26__n.BLIF a_i_27__n.BLIF N_247_2
11 1
.names a_c_19__n.BLIF a_i_19__n
0 1
.names a_i_28__n.BLIF a_i_29__n.BLIF N_247_3
11 1
.names a_c_17__n.BLIF a_i_17__n
0 1
.names a_i_30__n.BLIF a_i_31__n.BLIF N_247_4
11 1
.names a_c_18__n.BLIF a_i_18__n
0 1
.names N_247_1.BLIF N_247_2.BLIF N_247_5
11 1
.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
0 1
.names N_247_3.BLIF N_247_4.BLIF N_247_6
11 1
.names N_98.BLIF N_98_i
0 1
.names size_c_i_1__n.BLIF A0_c_i.BLIF state_machine_un7_ds_030_i_1_n
11 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
0 1
.names a_c_21__n.BLIF a_c_22__n.BLIF N_31_1
11 1
.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i
0 1
.names a_c_23__n.BLIF N_220.BLIF N_31_2
11 1
.names DS_000_DMA_1_sqmuxa_1.BLIF DS_000_DMA_1_sqmuxa_1_i
0 1
.names N_179_1.BLIF RW_c.BLIF N_179_1_0
11 1
.names state_machine_un8_bgack_030_int_n.BLIF \
state_machine_un8_bgack_030_int_i_n
0 1
.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF \
state_machine_clk_000_p_sync_3_1_0__n
11 1
.names CLK_030_c.BLIF CLK_030_i
0 1
.names CLK_000_D2_i.BLIF CLK_000_D3_i.BLIF \
state_machine_clk_000_p_sync_3_2_0__n
11 1
.names UDS_000_c.BLIF UDS_000_i
0 1
.names a_i_16__n.BLIF a_i_18__n.BLIF state_machine_un28_as_030_1_n
11 1
.names LDS_000_c.BLIF LDS_000_i
0 1
.names a_i_19__n.BLIF un19_fpu_cs_5.BLIF state_machine_un28_as_030_2_n
11 1
.names state_machine_un31_bgack_030_int_n.BLIF \
state_machine_un31_bgack_030_int_i_n
0 1
.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.BLIF \
state_machine_clk_000_n_sync_2_1_0__n
11 1
.names RW_000_c.BLIF RW_000_i
0 1
.names N_32_i.BLIF N_37_i.BLIF cpu_est_ns_0_1_1__n
11 1
.names state_machine_un24_bgack_030_int_n.BLIF \
state_machine_un24_bgack_030_int_i_n
0 1
.names N_223_i.BLIF N_224_i.BLIF cpu_est_ns_0_2_1__n
11 1
.names inst_AS_000_DMA.BLIF AS_000_DMA_i
0 1
.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF \
state_machine_un10_clk_000_d0_1_n
11 1
.names inst_CLK_000_D2.BLIF CLK_000_D2_i
0 1
.names N_35.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n
11 1
.names inst_CLK_000_D3.BLIF CLK_000_D3_i
0 1
.names N_95.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1
11 1
.names inst_CLK_000_D1.BLIF CLK_000_D1_i
0 1
.names sm_amiga_i_7__n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \
AMIGA_BUS_ENABLE_INT_2_sqmuxa_2
11 1
.names state_machine_un28_as_030_n.BLIF state_machine_un28_as_030_i_n
0 1
.names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_96_i_1
11 1
.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
0 1
.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n
11 1
.names AS_000_c.BLIF AS_000_i
0 1
.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n
11 1
.names RW_c.BLIF RW_i
0 1
.names state_machine_un3_bgack_030_int_d_i_n.BLIF \
AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1
11 1
.names inst_CLK_000_D0.BLIF CLK_000_D0_i
0 1
.names a_i_16__n.BLIF a_i_17__n.BLIF N_33_1
11 1
.names cpu_est_3_reg.BLIF cpu_est_i_3__n
0 1
.names a_i_18__n.BLIF a_i_19__n.BLIF N_33_2
11 1
.names cpu_est_1_.BLIF cpu_est_i_1__n
0 1
.names a_c_17__n.BLIF BGACK_000_c.BLIF un19_fpu_cs_5_1
11 1
.names cpu_est_0_.BLIF cpu_est_i_0__n
0 1
.names fc_c_0__n.BLIF fc_c_1__n.BLIF un19_fpu_cs_5_2
11 1
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
1 1
0 0
.names BG_000DFFSHreg.BLIF BG_000
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF BGACK_030
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
1 1
0 0
.names CLK_OUT_INTreg.BLIF CLK_EXP
1 1
0 0
.names un19_fpu_cs_i.BLIF FPU_CS
1 1
0 0
.names vcc_n_n.BLIF AVEC
1 1
0 0
.names inst_avec_expreg.BLIF AVEC_EXP
1 1
0 0
.names cpu_est_3_reg.BLIF E
1 1
0 0
.names inst_VMA_INTreg.BLIF VMA
1 1
0 0
.names RESETDFFRHreg.BLIF RESET
1 1
0 0
.names inst_AMIGA_BUS_ENABLE_INTreg.BLIF AMIGA_BUS_ENABLE
1 1
0 0
.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
1 1
0 0
.names inst_CLK_OUT_PRE_33reg.BLIF AMIGA_BUS_ENABLE_LOW
1 1
0 0
.names un28_ciin.BLIF CIIN
1 1
0 0
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
1 1
0 0
.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_0_.C
1 1
0 0
.names RST_i.BLIF cpu_est_0_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_1_.C
1 1
0 0
.names RST_i.BLIF cpu_est_1_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_2_.C
1 1
0 0
.names RST_i.BLIF cpu_est_2_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF cpu_est_3_reg.C
1 1
0 0
.names RST_i.BLIF cpu_est_3_reg.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_7_.AP
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_6_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_5_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_4_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_3_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_2_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_1_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
1 1
0 0
.names RST_i.BLIF SM_AMIGA_0_.AR
1 1
0 0
.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_6_.AR
1 1
0 0
.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_7_.AR
1 1
0 0
.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_8_.AR
1 1
0 0
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_9_.AR
1 1
0 0
.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_10_.AR
1 1
0 0
.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_11_.AR
1 1
0 0
.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C
1 1
0 0
.names RST_i.BLIF CLK_CNT_N_0_.AR
1 1
0 0
.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D
1 1
0 0
.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C
1 1
0 0
.names RST_i.BLIF CLK_CNT_N_1_.AP
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C
1 1
0 0
.names RST_i.BLIF CLK_CNT_P_0_.AR
1 1
0 0
.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_CNT_P_1_.C
1 1
0 0
.names RST_i.BLIF CLK_CNT_P_1_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C
1 1
0 0
.names RST_i.BLIF SIZE_DMA_0_.AP
1 1
0 0
.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C
1 1
0 0
.names RST_i.BLIF SIZE_DMA_1_.AP
1 1
0 0
.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C
1 1
0 0
.names RST_i.BLIF IPL_030DFFSH_0_reg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C
1 1
0 0
.names RST_i.BLIF IPL_030DFFSH_1_reg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C
1 1
0 0
.names RST_i.BLIF IPL_030DFFSH_2_reg.AP
1 1
0 0
.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_1_.AR
1 1
0 0
.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_2_.AR
1 1
0 0
.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_3_.AR
1 1
0 0
.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_4_.AR
1 1
0 0
.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_5_.AR
1 1
0 0
.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_6_.AR
1 1
0 0
.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_7_.AR
1 1
0 0
.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_8_.AR
1 1
0 0
.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_9_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_0_.AR
1 1
0 0
.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_1_.AR
1 1
0 0
.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_2_.AR
1 1
0 0
.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_3_.AR
1 1
0 0
.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_4_.AR
1 1
0 0
.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C
1 1
0 0
.names RST_i.BLIF CLK_000_N_SYNC_5_.AR
1 1
0 0
.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_25.AR
1 1
0 0
.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
1 1
0 0
.names RST_i.BLIF inst_BGACK_030_INTreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C
1 1
0 0
.names RST_i.BLIF CLK_000_P_SYNC_0_.AR
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_AS_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C
1 1
0 0
.names RST_i.BLIF inst_DS_000_ENABLE.AR
1 1
0 0
.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C
1 1
0 0
.names RST_i.BLIF BG_000DFFSHreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C
1 1
0 0
.names RST_i.BLIF inst_DSACK1_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_LDS_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_UDS_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_RW_000_INT.C
1 1
0 0
.names RST_i.BLIF inst_RW_000_INT.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
1 1
0 0
.names RST_i.BLIF inst_VMA_INTreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_A0_DMA.C
1 1
0 0
.names RST_i.BLIF inst_A0_DMA.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
1 1
0 0
.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C
1 1
0 0
.names RST_i.BLIF inst_RW_000_DMA.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C
1 1
0 0
.names RST_i.BLIF inst_DS_000_DMA.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
1 1
0 0
.names RST_i.BLIF inst_AS_000_DMA.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_INTreg.C
1 1
0 0
.names RST_i.BLIF inst_AMIGA_BUS_ENABLE_INTreg.AP
1 1
0 0
.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
1 1
0 0
.names RST_i.BLIF inst_AS_030_000_SYNC.AP
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_33reg.AR
1 1
0 0
.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE.AR
1 1
0 0
.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D3.AP
1 1
0 0
.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D2.AP
1 1
0 0
.names vcc_n_n.BLIF RESETDFFRHreg.D
1 1
0 0
.names CLK_OSZI_c.BLIF RESETDFFRHreg.C
1 1
0 0
.names RST_i.BLIF RESETDFFRHreg.AR
1 1
0 0
.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D
1 1
0 0
.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C
1 1
0 0
.names RST_i.BLIF CLK_OUT_INTreg.AR
1 1
0 0
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D1.AP
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
1 1
0 0
.names RST_i.BLIF inst_BGACK_030_INT_D.AP
1 1
0 0
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50_D.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR
1 1
0 0
.names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_D.AR
1 1
0 0
.names CLK_000_c.BLIF inst_CLK_000_D0.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_D0.AP
1 1
0 0
.names VPA_c.BLIF inst_VPA_D.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_VPA_D.C
1 1
0 0
.names RST_i.BLIF inst_VPA_D.AP
1 1
0 0
.names CLK_000_P_SYNC_9_.BLIF inst_avec_expreg.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_avec_expreg.C
1 1
0 0
.names RST_i.BLIF inst_avec_expreg.AR
1 1
0 0
.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C
1 1
0 0
.names RST_i.BLIF inst_CLK_000_NE.AR
1 1
0 0
.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
1 1
0 0
.names RST_i.BLIF inst_CLK_OUT_PRE_50.AR
1 1
0 0
.names SIZE_DMA_1_.BLIF SIZE_1_
1 1
0 0
.names inst_AS_000_DMA.BLIF AS_030
1 1
0 0
.names inst_AS_000_INT.BLIF AS_000
1 1
0 0
.names inst_RW_000_INT.BLIF RW_000
1 1
0 0
.names inst_DS_000_DMA.BLIF DS_030
1 1
0 0
.names un1_UDS_000_INT.BLIF UDS_000
1 1
0 0
.names un1_LDS_000_INT.BLIF LDS_000
1 1
0 0
.names inst_A0_DMA.BLIF A0
1 1
0 0
.names inst_DSACK1_INT.BLIF DSACK1
1 1
0 0
.names DSACK1_c.BLIF DTACK
1 1
0 0
.names inst_RW_000_DMA.BLIF RW
1 1
0 0
.names SIZE_DMA_0_.BLIF SIZE_0_
1 1
0 0
.names AS_030.PIN.BLIF AS_030_c
1 1
0 0
.names AS_000.PIN.BLIF AS_000_c
1 1
0 0
.names RW_000.PIN.BLIF RW_000_c
1 1
0 0
.names DS_030.PIN.BLIF DS_030_c
1 1
0 0
.names UDS_000.PIN.BLIF UDS_000_c
1 1
0 0
.names LDS_000.PIN.BLIF LDS_000_c
1 1
0 0
.names SIZE_0_.PIN.BLIF size_c_0__n
1 1
0 0
.names SIZE_1_.PIN.BLIF size_c_1__n
1 1
0 0
.names A_16_.BLIF a_c_16__n
1 1
0 0
.names A_17_.BLIF a_c_17__n
1 1
0 0
.names A_18_.BLIF a_c_18__n
1 1
0 0
.names A_19_.BLIF a_c_19__n
1 1
0 0
.names A_20_.BLIF a_c_20__n
1 1
0 0
.names A_21_.BLIF a_c_21__n
1 1
0 0
.names A_22_.BLIF a_c_22__n
1 1
0 0
.names A_23_.BLIF a_c_23__n
1 1
0 0
.names A_24_.BLIF a_c_24__n
1 1
0 0
.names A_25_.BLIF a_c_25__n
1 1
0 0
.names A_26_.BLIF a_c_26__n
1 1
0 0
.names A_27_.BLIF a_c_27__n
1 1
0 0
.names A_28_.BLIF a_c_28__n
1 1
0 0
.names A_29_.BLIF a_c_29__n
1 1
0 0
.names A_30_.BLIF a_c_30__n
1 1
0 0
.names A_31_.BLIF a_c_31__n
1 1
0 0
.names A0.PIN.BLIF A0_c
1 1
0 0
.names nEXP_SPACE.BLIF nEXP_SPACE_c
1 1
0 0
.names BERR.BLIF BERR_c
1 1
0 0
.names BG_030.BLIF BG_030_c
1 1
0 0
.names BGACK_000.BLIF BGACK_000_c
1 1
0 0
.names CLK_030.BLIF CLK_030_c
1 1
0 0
.names CLK_000.BLIF CLK_000_c
1 1
0 0
.names CLK_OSZI.BLIF CLK_OSZI_c
1 1
0 0
.names IPL_0_.BLIF ipl_c_0__n
1 1
0 0
.names IPL_1_.BLIF ipl_c_1__n
1 1
0 0
.names IPL_2_.BLIF ipl_c_2__n
1 1
0 0
.names DSACK1.PIN.BLIF DSACK1_c
1 1
0 0
.names DTACK.PIN.BLIF DTACK_c
1 1
0 0
.names VPA.BLIF VPA_c
1 1
0 0
.names RST.BLIF RST_c
1 1
0 0
.names RW.PIN.BLIF RW_c
1 1
0 0
.names FC_0_.BLIF fc_c_0__n
1 1
0 0
.names FC_1_.BLIF fc_c_1__n
1 1
0 0
.names un3_dtack_i.BLIF AS_030.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF AS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF RW_000.OE
1 1
0 0
.names un3_dtack_i.BLIF DS_030.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF UDS_000.OE
1 1
0 0
.names inst_BGACK_030_INTreg.BLIF LDS_000.OE
1 1
0 0
.names un3_dtack_i.BLIF SIZE_0_.OE
1 1
0 0
.names un3_dtack_i.BLIF SIZE_1_.OE
1 1
0 0
.names un3_dtack_i.BLIF A0.OE
1 1
0 0
.names nEXP_SPACE_c.BLIF DSACK1.OE
1 1
0 0
.names un3_dtack_i.BLIF DTACK.OE
1 1
0 0
.names BGACK_030_INT_i.BLIF RW.OE
1 1
0 0
.names N_247.BLIF CIIN.OE
1 1
0 0
.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF G_109
01 1
10 1
11 0
00 0
.names CLK_CNT_P_1_.BLIF CLK_CNT_P_0_.BLIF G_115
01 1
10 1
11 0
00 0
.names inst_CLK_OUT_PRE_25.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \
CLK_OUT_PRE_25_0
01 1
10 1
11 0
00 0
.names a_c_21__n.BLIF a_c_22__n.BLIF un28_ciin_0_x2
01 1
10 1
11 0
00 0
.end