Lay out most of board

This commit is contained in:
garrettfellers 2021-02-09 18:23:48 -05:00
parent 4119d124bf
commit 39335b0637
4 changed files with 4408 additions and 609 deletions

View File

@ -310,26 +310,6 @@ X ~ 5 -300 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GW_Logic_741G74DC
#
DEF GW_Logic_741G74DC U 0 40 Y Y 1 F N
F0 "U" 0 300 50 H V C CNN
F1 "GW_Logic_741G74DC" 0 -300 50 H V C CNN
F2 "stdpads:SOT-353" 0 -350 50 H I C TNN
F3 "" 0 -200 60 H I C CNN
DRAW
S 200 -250 -200 250 0 1 10 f
X CK 1 -400 -150 200 R 50 50 1 1 I
X D 2 -400 150 200 R 50 50 1 1 I
X ~Q~ 3 400 -50 200 L 50 50 1 1 O
X GND 4 400 -150 200 L 50 50 1 1 W
X Q 5 400 50 200 L 50 50 1 1 O
X ~R~ 6 -400 -50 200 R 50 50 1 1 I
X ~S~ 7 -400 50 200 R 50 50 1 1 I
X Vcc 8 400 150 200 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# GW_MCU_ESP-WROOM-32
#
DEF GW_MCU_ESP-WROOM-32 U 0 40 Y Y 1 F N

File diff suppressed because it is too large Load Diff

View File

@ -1,4 +1,4 @@
update=Saturday, February 06, 2021 at 06:09:02 AM
update=Monday, February 08, 2021 at 02:06:36 AM
version=1
last_client=kicad
[general]
@ -12,6 +12,16 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
@ -37,20 +47,15 @@ TrackWidth6=0.4
TrackWidth7=0.45
TrackWidth8=0.5
TrackWidth9=0.6
TrackWidth10=0.8
TrackWidth11=1
TrackWidth12=1.27
TrackWidth13=1.524
TrackWidth10=0.65
TrackWidth11=0.8
TrackWidth12=1
ViaDiameter1=0.5
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
ViaDiameter4=1
ViaDrill4=0.5
ViaDiameter5=1.524
ViaDrill5=0.762
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
@ -77,18 +82,18 @@ OthersTextUpright=1
SolderMaskClearance=0.05
SolderMaskMinWidth=0.09999999999999999
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Type=1
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
@ -256,13 +261,3 @@ uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

624
ADBT.sch
View File

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$EndComp
$Comp
L Device:R_Small R2
U 1 1 6035866C
P 5500 1050
F 0 "R2" H 5559 1096 50 0000 L CNN
F 1 "124k" H 5559 1005 50 0000 L CNN
F 2 "stdpads:R_0603" H 5500 1050 50 0001 C CNN
F 3 "~" H 5500 1050 50 0001 C CNN
1 5500 1050
-1 0 0 -1
$EndComp
$Comp
L Device:R_Small R18
U 1 1 60358C43
P 5500 1300
F 0 "R18" H 5559 1346 50 0000 L CNN
F 1 "124k" H 5559 1255 50 0000 L CNN
F 2 "stdpads:R_0603" H 5500 1300 50 0001 C CNN
F 3 "~" H 5500 1300 50 0001 C CNN
1 5500 1300
-1 0 0 -1
$EndComp
Wire Wire Line
5500 1200 5500 1150
Connection ~ 5500 1150
Wire Wire Line
5500 1400 5500 1450
Wire Wire Line
5500 1450 5900 1450
Wire Wire Line
6900 950 6600 950
Connection ~ 6600 950
Wire Wire Line
6600 1150 6600 1450
Wire Wire Line
6600 1450 7150 1450
Connection ~ 6600 1450
Wire Wire Line
6300 1150 6350 1150
Wire Wire Line
7100 1150 7150 1150
Wire Wire Line
6350 1200 7100 1200
Wire Wire Line
6350 1150 6350 1200
Wire Wire Line
7100 1200 7100 1150
Wire Wire Line
5900 1450 6600 1450
Connection ~ 5900 1450
$Comp
L Device:D_Schottky_Small_ALT D7
U 1 1 603DA193
P 6600 1050
F 0 "D7" V 6554 1118 50 0000 L CNN
F 1 "1N5819" V 6645 1118 50 0000 L CNN
F 2 "stdpads:D_SOD-123" V 6600 1050 50 0001 C CNN
F 3 "~" V 6600 1050 50 0001 C CNN
1 6600 1050
0 1 1 0
$EndComp
Wire Wire Line
4900 1450 5500 1450
Connection ~ 4900 1450
Connection ~ 5500 1450
Wire Wire Line
5500 950 4900 950
Connection ~ 5500 950
Connection ~ 4900 950
$Comp
L power:GND #PWR0105
U 1 1 601CD7C0
P 3250 4550
F 0 "#PWR0105" H 3250 4300 50 0001 C CNN
F 1 "GND" H 3250 4400 50 0000 C CNN
F 2 "" H 3250 4550 50 0001 C CNN
F 3 "" H 3250 4550 50 0001 C CNN
1 3250 4550
1 0 0 -1
$EndComp
$Comp
L power:+3V3 #PWR0106
U 1 1 601D380C
P 3250 4350
F 0 "#PWR0106" H 3250 4200 50 0001 C CNN
F 1 "+3V3" H 3250 4500 50 0000 C CNN
F 2 "" H 3250 4350 50 0001 C CNN
F 3 "" H 3250 4350 50 0001 C CNN
1 3250 4350
-1 0 0 -1
$EndComp
$Comp
L 74xGxx:74LVC1G14 U4
U 1 1 607ABB09
P 3250 4450
F 0 "U4" H 3350 4500 50 0000 C BNN
F 1 "74LVC1G14GW" H 3250 4350 50 0000 L CNN
F 2 "stdpads:SOT-353" H 3250 4450 50 0001 C CNN
F 3 "http://www.ti.com/lit/sg/scyt129e/scyt129e.pdf" H 3250 4450 50 0001 C CNN
F 4 "C265125" H 3250 4450 50 0001 C CNN "LCSC Part"
1 3250 4450
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R16
U 1 1 60ECB303
P 3600 4450
F 0 "R16" V 3450 4450 50 0000 C CNN
F 1 "27" V 3550 4450 50 0000 C BNN
F 2 "stdpads:R_0603" H 3600 4450 50 0001 C CNN
F 3 "~" H 3600 4450 50 0001 C CNN
1 3600 4450
0 -1 1 0
$EndComp
Text Label 3900 4450 2 50 ~ 0
ADBin
Wire Wire Line
3900 4450 3700 4450
Text Notes 2800 4050 0 50 ~ 0
ADB input receiver & synchronizer
Wire Notes Line
2700 4800 2700 4100
Wire Notes Line
4250 4100 4250 4800
Wire Notes Line
2700 4100 4250 4100
Wire Notes Line
4250 4800 2700 4800
$EndSCHEMATC