Macintosh-HW
/
MacClassicRAMCard
mirror of https://github.com/garrettsworkshop/MacClassicRAMCard.git
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Migrate to KiCAD 6

This commit is contained in:
Zane Kaminski 2022-02-05 19:31:38 -05:00
parent 68f0acbebf
commit c1a979994e
8 changed files with 20807 additions and 5485 deletions
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1
.gitignore vendored
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@ -14,6 +14,7 @@ _autosave-*
*-save.pro
*-save.kicad_pcb
fp-info-cache
MacClassicRAMCard-backups/*
# Netlist files (exported from Eeschema)
*.net

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Documentation/Assembly.html Normal file
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17505
MacClassicRAMCard.kicad_pcb
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75
MacClassicRAMCard.kicad_prl Normal file
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@ -0,0 +1,75 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
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"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "MacClassicRAMCard.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

450
MacClassicRAMCard.kicad_pro Normal file
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@ -0,0 +1,450 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.15,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 0.45,
"width": 1.15
},
"silk_line_width": 0.15,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15,
"silk_text_upright": false,
"zones": {
"45_degree_only": false,
"min_clearance": 0.154
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"copper_edge_clearance": "error",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
"rule_severitieslegacy_no_courtyard_defined": false,
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.075,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.15,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.5,
"use_height_for_length_calcs": true
},
"track_widths": [
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0.2,
0.25,
0.3,
0.35,
0.4,
0.45,
0.5,
0.6,
0.8,
1.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.6,
"drill": 0.3
},
{
"diameter": 0.8,
"drill": 0.4
},
{
"diameter": 1.0,
"drill": 0.5
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
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],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "MacClassicRAMCard.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"via_diameter": 0.5,
"via_drill": 0.2,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "MacClassicRAMCard.net",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"pin_symbol_size": 0.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "Pcbnew",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
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]
],
"text_variables": {}
}

2839
MacClassicRAMCard.kicad_sch Normal file
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264
MacClassicRAMCard.pro
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@ -1,264 +0,0 @@
update=Tuesday, November 16, 2021 at 02:17:51 PM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=MacClassicRAMCard.net
CopperLayerCount=2
BoardThickness=1.2
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.15
MinViaDiameter=0.5
MinViaDrill=0.2
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.15
TrackWidth2=0.2
TrackWidth3=0.25
TrackWidth4=0.3
TrackWidth5=0.35
TrackWidth6=0.4
TrackWidth7=0.45
TrackWidth8=0.5
TrackWidth9=0.6
TrackWidth10=0.8
TrackWidth11=1
ViaDiameter1=0.5
ViaDrill1=0.2
ViaDiameter2=0.6
ViaDrill2=0.3
ViaDiameter3=0.8
ViaDrill3=0.4
ViaDiameter4=1
ViaDrill4=0.5
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.075
SolderMaskMinWidth=0.09999999999999999
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=2
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=2
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.15
TrackWidth=0.15
ViaDiameter=0.5
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

813
MacClassicRAMCard.sch
View File

@ -1,813 +0,0 @@
EESchema Schematic File Version 4
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Wire Wire Line
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$Comp
L Device:C_Small C2
U 1 1 60C16BC7
P 1100 4000
F 0 "C2" H 1192 4046 50 0000 L CNN
F 1 "2u2" H 1192 3955 50 0000 L CNN
F 2 "stdpads:C_0805" H 1100 4000 50 0001 C CNN
F 3 "~" H 1100 4000 50 0001 C CNN
1 1100 4000
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C4
U 1 1 60C16BCD
P 1900 4000
F 0 "C4" H 1992 4046 50 0000 L CNN
F 1 "2u2" H 1992 3955 50 0000 L CNN
F 2 "stdpads:C_0805" H 1900 4000 50 0001 C CNN
F 3 "~" H 1900 4000 50 0001 C CNN
1 1900 4000
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C1
U 1 1 60C16BD3
P 700 4000
F 0 "C1" H 792 4046 50 0000 L CNN
F 1 "2u2" H 792 3955 50 0000 L CNN
F 2 "stdpads:C_0805" H 700 4000 50 0001 C CNN
F 3 "~" H 700 4000 50 0001 C CNN
1 700 4000
1 0 0 -1
$EndComp
$Comp
L Device:C_Small C3
U 1 1 60C16BD9
P 1500 4000
F 0 "C3" H 1592 4046 50 0000 L CNN
F 1 "2u2" H 1592 3955 50 0000 L CNN
F 2 "stdpads:C_0805" H 1500 4000 50 0001 C CNN
F 3 "~" H 1500 4000 50 0001 C CNN
1 1500 4000
1 0 0 -1
$EndComp
Connection ~ 1900 3900
Wire Wire Line
1900 3900 2300 3900
Connection ~ 1900 4100
Wire Wire Line
1900 4100 2300 4100
Connection ~ 1500 3900
Wire Wire Line
1500 3900 1900 3900
Connection ~ 1500 4100
Wire Wire Line
1500 4100 1900 4100
Connection ~ 1100 3900
Wire Wire Line
1100 3900 1500 3900
Connection ~ 1100 4100
Wire Wire Line
1100 4100 1500 4100
Connection ~ 700 3900
$Comp
L Mechanical:Fiducial FID4
U 1 1 5EDCCFC0
P 3100 3650
F 0 "FID4" H 3185 3696 50 0000 L CNN
F 1 "Fiducial" H 3185 3605 50 0000 L CNN
F 2 "stdpads:Fiducial" H 3100 3650 50 0001 C CNN
F 3 "~" H 3100 3650 50 0001 C CNN
1 3100 3650
1 0 0 -1
$EndComp
$Comp
L Mechanical:Fiducial FID2
U 1 1 5EDCCA31
P 2100 3650
F 0 "FID2" H 2185 3696 50 0000 L CNN
F 1 "Fiducial" H 2185 3605 50 0000 L CNN
F 2 "stdpads:Fiducial" H 2100 3650 50 0001 C CNN
F 3 "~" H 2100 3650 50 0001 C CNN
1 2100 3650
1 0 0 -1
$EndComp
$Comp
L Mechanical:Fiducial FID1
U 1 1 5EDCC581
P 2100 3400
F 0 "FID1" H 2185 3446 50 0000 L CNN
F 1 "Fiducial" H 2185 3355 50 0000 L CNN
F 2 "stdpads:Fiducial" H 2100 3400 50 0001 C CNN
F 3 "~" H 2100 3400 50 0001 C CNN
1 2100 3400
1 0 0 -1
$EndComp
Text Label 4700 1450 2 50 ~ 0
A0
Text Label 4700 1550 2 50 ~ 0
A1
Text Label 4700 1650 2 50 ~ 0
A2
Text Label 4700 1750 2 50 ~ 0
A3
Text Label 4700 1850 2 50 ~ 0
A4
Text Label 4700 1950 2 50 ~ 0
A5
Text Label 4700 2050 2 50 ~ 0
A6
Text Label 4700 2150 2 50 ~ 0
A7
Text Label 4700 2250 2 50 ~ 0
A8
Text Label 4700 2350 2 50 ~ 0
A9
Connection ~ 3100 4100
$Comp
L GW_RAM:DRAM-1Mx16-SOP-42 U1
U 1 1 60CFBCF9
P 5100 2150
F 0 "U1" H 5100 2950 50 0000 C CNN
F 1 "AS4C1M16F5" V 5100 2150 50 0000 C CNN
F 2 "stdpads:SOJ-42_400mil" H 5100 1200 50 0001 C CNN
F 3 "" H 5100 1800 50 0001 C CNN
1 5100 2150
1 0 0 -1
$EndComp
Text Label 4700 2550 2 50 ~ 0
U~CAS~0
Text Label 4700 2650 2 50 ~ 0
~RAS~
Text Label 4700 2750 2 50 ~ 0
~WE~
Text Label 4700 2850 2 50 ~ 0
~OE~0
Text Label 4700 2450 2 50 ~ 0
L~CAS~0
$Comp
L power:GND #PWR0101
U 1 1 60D0B9EF
P 4700 2950
F 0 "#PWR0101" H 4700 2700 50 0001 C CNN
F 1 "GND" H 4700 2800 50 0000 C CNN
F 2 "" H 4700 2950 50 0001 C CNN
F 3 "" H 4700 2950 50 0001 C CNN
1 4700 2950
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR0102
U 1 1 60D0BE9E
P 4700 1350
F 0 "#PWR0102" H 4700 1200 50 0001 C CNN
F 1 "+5V" H 4700 1500 50 0000 C CNN
F 2 "" H 4700 1350 50 0001 C CNN
F 3 "" H 4700 1350 50 0001 C CNN
1 4700 1350
-1 0 0 -1
$EndComp
Text Label 6300 1450 2 50 ~ 0
A0
Text Label 6300 1550 2 50 ~ 0
A1
Text Label 6300 1650 2 50 ~ 0
A2
Text Label 6300 1750 2 50 ~ 0
A3
Text Label 6300 1850 2 50 ~ 0
A4
Text Label 6300 1950 2 50 ~ 0
A5
Text Label 6300 2050 2 50 ~ 0
A6
Text Label 6300 2150 2 50 ~ 0
A7
Text Label 6300 2250 2 50 ~ 0
A8
Text Label 6300 2350 2 50 ~ 0
A9
$Comp
L GW_RAM:DRAM-1Mx16-SOP-42 U2
U 1 1 60D12031
P 6700 2150
F 0 "U2" H 6700 2950 50 0000 C CNN
F 1 "AS4C1M16F5" V 6700 2150 50 0000 C CNN
F 2 "stdpads:SOJ-42_400mil" H 6700 1200 50 0001 C CNN
F 3 "" H 6700 1800 50 0001 C CNN
1 6700 2150
1 0 0 -1
$EndComp
Text Label 6300 2550 2 50 ~ 0
U~CAS~1
Text Label 6300 2650 2 50 ~ 0
~RAS~
Text Label 6300 2750 2 50 ~ 0
~WE~
Text Label 6300 2850 2 50 ~ 0
~OE~1
Text Label 6300 2450 2 50 ~ 0
L~CAS~1
Text Label 7100 2350 0 50 ~ 0
DQ8
$Comp
L power:GND #PWR0103
U 1 1 60D12044
P 6300 2950
F 0 "#PWR0103" H 6300 2700 50 0001 C CNN
F 1 "GND" H 6300 2800 50 0000 C CNN
F 2 "" H 6300 2950 50 0001 C CNN
F 3 "" H 6300 2950 50 0001 C CNN
1 6300 2950
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR0104
U 1 1 60D1204A
P 6300 1350
F 0 "#PWR0104" H 6300 1200 50 0001 C CNN
F 1 "+5V" H 6300 1500 50 0000 C CNN
F 2 "" H 6300 1350 50 0001 C CNN
F 3 "" H 6300 1350 50 0001 C CNN
1 6300 1350
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0105
U 1 1 60D18BDD
P 850 750
F 0 "#PWR0105" H 850 500 50 0001 C CNN
F 1 "GND" H 850 600 50 0000 C CNN
F 2 "" H 850 750 50 0001 C CNN
F 3 "" H 850 750 50 0001 C CNN
1 850 750
-1 0 0 1
$EndComp
$Comp
L power:GND #PWR0106
U 1 1 60D1928E
P 1350 750
F 0 "#PWR0106" H 1350 500 50 0001 C CNN
F 1 "GND" H 1350 600 50 0000 C CNN
F 2 "" H 1350 750 50 0001 C CNN
F 3 "" H 1350 750 50 0001 C CNN
1 1350 750
-1 0 0 1
$EndComp
$Comp
L power:+5V #PWR0107
U 1 1 60D1968F
P 1550 750
F 0 "#PWR0107" H 1550 600 50 0001 C CNN
F 1 "+5V" H 1550 900 50 0000 C CNN
F 2 "" H 1550 750 50 0001 C CNN
F 3 "" H 1550 750 50 0001 C CNN
1 1550 750
-1 0 0 -1
$EndComp
Wire Wire Line
1550 750 1550 850
Wire Wire Line
1550 850 1350 850
$Comp
L power:+5V #PWR0108
U 1 1 60D1A5D4
P 650 750
F 0 "#PWR0108" H 650 600 50 0001 C CNN
F 1 "+5V" H 650 900 50 0000 C CNN
F 2 "" H 650 750 50 0001 C CNN
F 3 "" H 650 750 50 0001 C CNN
1 650 750
1 0 0 -1
$EndComp
Wire Wire Line
650 750 650 850
Text Label 1350 950 0 50 ~ 0
L~CAS~C
Text Label 850 1050 2 50 ~ 0
L~CAS~E
Text Label 1350 1050 0 50 ~ 0
U~CAS~E
Text Label 850 1150 2 50 ~ 0
U~CAS~D
Text Label 1350 1150 0 50 ~ 0
L~CAS~D
Text Label 850 1250 2 50 ~ 0
~SIMM~
Text Label 1350 1250 0 50 ~ 0
~EXP~
Text Label 1350 1350 0 50 ~ 0
DQ4
Text Label 1350 1450 0 50 ~ 0
DQ5
Text Label 1350 1550 0 50 ~ 0
DQ6
Text Label 1350 1650 0 50 ~ 0
DQ7
Text Label 850 1650 2 50 ~ 0
DQ3
Text Label 850 1450 2 50 ~ 0
DQ1
Text Label 850 1550 2 50 ~ 0
DQ2
Text Label 850 1350 2 50 ~ 0
DQ0
Text Label 850 2550 2 50 ~ 0
DQ12
Text Label 850 2650 2 50 ~ 0
DQ13
Text Label 1350 2550 0 50 ~ 0
DQ14
Text Label 1350 2650 0 50 ~ 0
DQ15
Text Label 1350 1850 0 50 ~ 0
DQ11
Text Label 850 1850 2 50 ~ 0
DQ9
Text Label 1350 1750 0 50 ~ 0
DQ10
Text Label 850 1750 2 50 ~ 0
DQ8
$Comp
L power:GND #PWR0109
U 1 1 60D2005E
P 1350 2850
F 0 "#PWR0109" H 1350 2600 50 0001 C CNN
F 1 "GND" H 1350 2700 50 0000 C CNN
F 2 "" H 1350 2850 50 0001 C CNN
F 3 "" H 1350 2850 50 0001 C CNN
1 1350 2850
-1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR0110
U 1 1 60D20064
P 1550 2850
F 0 "#PWR0110" H 1550 2700 50 0001 C CNN
F 1 "+5V" H 1550 3000 50 0000 C CNN
F 2 "" H 1550 2850 50 0001 C CNN
F 3 "" H 1550 2850 50 0001 C CNN
1 1550 2850
-1 0 0 1
$EndComp
Wire Wire Line
1550 2850 1550 2750
Wire Wire Line
1550 2750 1350 2750
$Comp
L power:GND #PWR0111
U 1 1 60D20E22
P 850 2850
F 0 "#PWR0111" H 850 2600 50 0001 C CNN
F 1 "GND" H 850 2700 50 0000 C CNN
F 2 "" H 850 2850 50 0001 C CNN
F 3 "" H 850 2850 50 0001 C CNN
1 850 2850
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR0114
U 1 1 60D20E28
P 650 2850
F 0 "#PWR0114" H 650 2700 50 0001 C CNN
F 1 "+5V" H 650 3000 50 0000 C CNN
F 2 "" H 650 2850 50 0001 C CNN
F 3 "" H 650 2850 50 0001 C CNN
1 650 2850
1 0 0 1
$EndComp
Wire Wire Line
650 2850 650 2750
Text Label 850 2450 2 50 ~ 0
~RAS~
Text Label 1350 2450 0 50 ~ 0
~WE~
Text Label 850 2250 2 50 ~ 0
A0
Text Label 850 2150 2 50 ~ 0
A1
Text Label 850 2050 2 50 ~ 0
A2
Text Label 850 1950 2 50 ~ 0
A3
Text Label 1350 1950 0 50 ~ 0
A4
Text Label 1350 2050 0 50 ~ 0
A5
Text Label 1350 2150 0 50 ~ 0
A6
Text Label 1350 2250 0 50 ~ 0
A7
Text Label 850 2350 2 50 ~ 0
A8
Text Label 1350 2350 0 50 ~ 0
A9
$Comp
L 74xx:74LS08 U3
U 2 2 60D271A2
P 2450 1650
F 0 "U3" H 2450 1650 50 0000 C CNN
F 1 "74HCT08D" H 2450 1850 50 0000 C CNN
F 2 "stdpads:SOIC-14_3.9mm" H 2450 1650 50 0001 C CNN
F 3 "http://www.ti.com/lit/gpn/sn74LS08" H 2450 1650 50 0001 C CNN
2 2450 1650
1 0 0 -1
$EndComp
Text Label 850 950 2 50 ~ 0
U~CAS~C
Text Label 1850 1550 0 50 ~ 0
U~CAS~C
Text Label 1850 1750 0 50 ~ 0
U~CAS~D
Text Label 1850 1950 0 50 ~ 0
L~CAS~C
Text Label 1850 2150 0 50 ~ 0
L~CAS~D
Text Label 1850 2450 0 50 ~ 0
U~CAS~E
Wire Wire Line
2150 1950 1850 1950
Wire Wire Line
1850 2150 2150 2150
Wire Wire Line
1850 1750 2150 1750
Wire Wire Line
1850 1550 2150 1550
Text Label 2750 1650 0 50 ~ 0
U~CAS~0
Text Label 2750 2050 0 50 ~ 0
L~CAS~0
Wire Wire Line
3150 2050 2750 2050
Wire Wire Line
2750 1650 3150 1650
Text Label 3050 2450 2 50 ~ 0
U~CAS~1
Wire Wire Line
3150 2450 1850 2450
Text Label 1850 2650 0 50 ~ 0
L~CAS~E
Text Label 3050 2650 2 50 ~ 0
L~CAS~1
Wire Wire Line
3150 2650 1850 2650
$Comp
L 74xx:74LS08 U3
U 1 2 60D2CF76
P 2450 2050
F 0 "U3" H 2450 2050 50 0000 C CNN
F 1 "74HCT08D" H 2450 2250 50 0000 C CNN
F 2 "stdpads:SOIC-14_3.9mm" H 2450 2050 50 0001 C CNN
F 3 "http://www.ti.com/lit/gpn/sn74LS08" H 2450 2050 50 0001 C CNN
1 2450 2050
1 0 0 -1
$EndComp
Wire Wire Line
3150 1950 3150 2050
Wire Wire Line
3150 1750 3150 1650
Text Label 3950 1850 2 50 ~ 0
~OE~0
Wire Wire Line
3950 1850 3750 1850
Text Label 3950 2550 2 50 ~ 0
~OE~1
Wire Wire Line
3950 2550 3750 2550
$Comp
L power:+5V #PWR0116
U 1 1 60D54A33
P 4400 3100
F 0 "#PWR0116" H 4400 2950 50 0001 C CNN
F 1 "+5V" H 4400 3250 50 0000 C CNN
F 2 "" H 4400 3100 50 0001 C CNN
F 3 "" H 4400 3100 50 0001 C CNN
1 4400 3100
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0117
U 1 1 60D5518C
P 4400 4100
F 0 "#PWR0117" H 4400 3850 50 0001 C CNN
F 1 "GND" H 4400 3950 50 0000 C CNN
F 2 "" H 4400 4100 50 0001 C CNN
F 3 "" H 4400 4100 50 0001 C CNN
1 4400 4100
-1 0 0 -1
$EndComp
Text Label 3900 3700 0 50 ~ 0
~SIMM~
Text Label 3900 3800 0 50 ~ 0
~EXP~
$Comp
L power:GND #PWR0118
U 1 1 60D5688B
P 4100 4100
F 0 "#PWR0118" H 4100 3850 50 0001 C CNN
F 1 "GND" H 4100 3950 50 0000 C CNN
F 2 "" H 4100 4100 50 0001 C CNN
F 3 "" H 4100 4100 50 0001 C CNN
1 4100 4100
1 0 0 -1
$EndComp
Wire Wire Line
4100 4100 4100 3800
Wire Wire Line
4100 3700 3900 3700
Wire Wire Line
3900 3800 4100 3800
Connection ~ 4100 3800
Wire Wire Line
4100 3800 4100 3700
$Comp
L 74xx:74LS08 U3
U 4 2 60D4623E
P 3450 2550
F 0 "U3" H 3450 2550 50 0000 C CNN
F 1 "74HCT08D" H 3450 2750 50 0000 C CNN
F 2 "stdpads:SOIC-14_3.9mm" H 3450 2550 50 0001 C CNN
F 3 "http://www.ti.com/lit/gpn/sn74LS08" H 3450 2550 50 0001 C CNN
4 3450 2550
1 0 0 -1
$EndComp
$Comp
L 74xx:74LS08 U3
U 5 1 60D535D3
P 4400 3600
F 0 "U3" H 4630 3646 50 0000 L CNN
F 1 "74HCT08D" H 4630 3555 50 0000 L CNN
F 2 "stdpads:SOIC-14_3.9mm" H 4400 3600 50 0001 C CNN
F 3 "http://www.ti.com/lit/gpn/sn74LS08" H 4400 3600 50 0001 C CNN
5 4400 3600
1 0 0 -1
$EndComp
Wire Wire Line
650 2750 850 2750
Wire Wire Line
650 850 850 850
$Comp
L Connector_Generic:Conn_02x22_Odd_Even J1
U 1 1 60D165FF
P 1150 1750
F 0 "J1" H 1200 2850 50 0000 C CNN
F 1 "RAM Exp." H 1200 550 50 0000 C CNN
F 2 "stdpads:PinSocket_2x22_P2.54mm_Horizontal" H 1150 1750 50 0001 C CNN
F 3 "~" H 1150 1750 50 0001 C CNN
1 1150 1750
-1 0 0 -1
$EndComp
$Comp
L 74xx:74LS08 U3
U 3 2 60D3EADF
P 3450 1850
F 0 "U3" H 3450 1850 50 0000 C CNN
F 1 "74HCT08D" H 3450 2050 50 0000 C CNN
F 2 "stdpads:SOIC-14_3.9mm" H 3450 1850 50 0001 C CNN
F 3 "http://www.ti.com/lit/gpn/sn74LS08" H 3450 1850 50 0001 C CNN
3 3450 1850
1 0 0 -1
$EndComp
Text Label 5500 1950 0 50 ~ 0
DQ0
Text Label 5500 1750 0 50 ~ 0
DQ1
Text Label 5500 1850 0 50 ~ 0
DQ5
Text Label 5500 2050 0 50 ~ 0
DQ4
Text Label 5500 1650 0 50 ~ 0
DQ6
Text Label 5500 1450 0 50 ~ 0
DQ7
Text Label 5500 1550 0 50 ~ 0
DQ2
Text Label 5500 1350 0 50 ~ 0
DQ3
Text Label 7100 1950 0 50 ~ 0
DQ0
Text Label 7100 1750 0 50 ~ 0
DQ1
Text Label 7100 1850 0 50 ~ 0
DQ5
Text Label 7100 2050 0 50 ~ 0
DQ4
Text Label 7100 1650 0 50 ~ 0
DQ6
Text Label 7100 1450 0 50 ~ 0
DQ7
Text Label 7100 1550 0 50 ~ 0
DQ2
Text Label 7100 1350 0 50 ~ 0
DQ3
Text Label 7100 2750 0 50 ~ 0
DQ12
Text Label 7100 2950 0 50 ~ 0
DQ13
Text Label 7100 2650 0 50 ~ 0
DQ14
Text Label 7100 2850 0 50 ~ 0
DQ15
Text Label 5500 2750 0 50 ~ 0
DQ12
Text Label 5500 2950 0 50 ~ 0
DQ13
Text Label 5500 2650 0 50 ~ 0
DQ14
Text Label 5500 2850 0 50 ~ 0
DQ15
Text Label 7100 2250 0 50 ~ 0
DQ10
Text Label 7100 2550 0 50 ~ 0
DQ9
Text Label 7100 2450 0 50 ~ 0
DQ11
Text Label 5500 2350 0 50 ~ 0
DQ8
Text Label 5500 2250 0 50 ~ 0
DQ10
Text Label 5500 2550 0 50 ~ 0
DQ9
Text Label 5500 2450 0 50 ~ 0
DQ11
Wire Wire Line
3150 1650 3150 1550
Wire Wire Line
3150 1550 3950 1550
Connection ~ 3150 1650
Wire Wire Line
3150 2050 3950 2050
Connection ~ 3150 2050
Text Label 3950 1550 2 50 ~ 0
U~CAS~0
Text Label 3950 2050 2 50 ~ 0
L~CAS~0
Wire Wire Line
3150 2450 3150 2250
Wire Wire Line
3150 2250 3950 2250
Connection ~ 3150 2450
Wire Wire Line
3150 2650 3150 2750
Wire Wire Line
3150 2750 3950 2750
Connection ~ 3150 2650
Text Label 3950 2750 2 50 ~ 0
L~CAS~1
Text Label 3950 2250 2 50 ~ 0
U~CAS~1
Text Notes 1900 1250 0 50 ~ 0
U3A and U3B combine the /CAS signals for the two 256kx4 banks.\nU3C and U3D generate /OE signals to the DRAMs.\nOn the original Classic RAM card /OE is tied low.\nThis arrangement lets us use EDO DRAM.
Connection ~ 3000 3500
Connection ~ 3300 3500
Wire Wire Line
3000 3500 3300 3500
Wire Wire Line
3300 3500 3600 3500
Wire Wire Line
2700 3500 3000 3500
$Comp
L Mechanical:Fiducial FID3
U 1 1 5EDCCCF0
P 2600 3650
F 0 "FID3" H 2685 3696 50 0000 L CNN
F 1 "Fiducial" H 2685 3605 50 0000 L CNN
F 2 "stdpads:Fiducial" H 2600 3650 50 0001 C CNN
F 3 "~" H 2600 3650 50 0001 C CNN
1 2600 3650
1 0 0 -1
$EndComp
Connection ~ 3600 3500
$EndSCHEMATC