Removed uSD board
This commit is contained in:
Zane Kaminski
parent
2a2383b96b
commit
3ee6816950
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@ -1,483 +0,0 @@
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# Connector_Generic_Conn_02x32_Counter_Clockwise
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#
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DEF Connector_Generic_Conn_02x32_Counter_Clockwise J 0 40 Y N 1 F N
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F0 "J" 50 1600 50 H V C CNN
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F1 "Connector_Generic_Conn_02x32_Counter_Clockwise" 50 -1700 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Connector*:*_2x??_*
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$ENDFPLIST
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DRAW
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S -50 -1595 0 -1605 1 1 6 N
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S -50 -1495 0 -1505 1 1 6 N
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S -50 -1395 0 -1405 1 1 6 N
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S -50 -1295 0 -1305 1 1 6 N
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S -50 -1195 0 -1205 1 1 6 N
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S -50 -1095 0 -1105 1 1 6 N
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S -50 -995 0 -1005 1 1 6 N
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S -50 -895 0 -905 1 1 6 N
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S -50 -795 0 -805 1 1 6 N
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S -50 -695 0 -705 1 1 6 N
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S -50 -595 0 -605 1 1 6 N
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S -50 -495 0 -505 1 1 6 N
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S -50 -395 0 -405 1 1 6 N
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S -50 -295 0 -305 1 1 6 N
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S -50 -195 0 -205 1 1 6 N
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S -50 -95 0 -105 1 1 6 N
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S -50 5 0 -5 1 1 6 N
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S -50 105 0 95 1 1 6 N
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S -50 205 0 195 1 1 6 N
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S -50 305 0 295 1 1 6 N
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S -50 405 0 395 1 1 6 N
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S -50 505 0 495 1 1 6 N
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S -50 605 0 595 1 1 6 N
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S -50 705 0 695 1 1 6 N
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S -50 805 0 795 1 1 6 N
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S -50 905 0 895 1 1 6 N
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S -50 1005 0 995 1 1 6 N
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S -50 1105 0 1095 1 1 6 N
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S -50 1205 0 1195 1 1 6 N
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S -50 1305 0 1295 1 1 6 N
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S -50 1405 0 1395 1 1 6 N
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S -50 1505 0 1495 1 1 6 N
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S -50 1550 150 -1650 1 1 10 f
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S 150 -1595 100 -1605 1 1 6 N
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S 150 -1495 100 -1505 1 1 6 N
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S 150 -1395 100 -1405 1 1 6 N
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S 150 -1295 100 -1305 1 1 6 N
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S 150 -1195 100 -1205 1 1 6 N
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S 150 -1095 100 -1105 1 1 6 N
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S 150 -995 100 -1005 1 1 6 N
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S 150 -895 100 -905 1 1 6 N
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S 150 -795 100 -805 1 1 6 N
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S 150 -695 100 -705 1 1 6 N
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S 150 -595 100 -605 1 1 6 N
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S 150 -495 100 -505 1 1 6 N
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S 150 -395 100 -405 1 1 6 N
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S 150 -295 100 -305 1 1 6 N
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S 150 -195 100 -205 1 1 6 N
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S 150 -95 100 -105 1 1 6 N
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S 150 5 100 -5 1 1 6 N
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S 150 105 100 95 1 1 6 N
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S 150 205 100 195 1 1 6 N
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S 150 305 100 295 1 1 6 N
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S 150 405 100 395 1 1 6 N
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S 150 505 100 495 1 1 6 N
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S 150 605 100 595 1 1 6 N
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S 150 705 100 695 1 1 6 N
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S 150 805 100 795 1 1 6 N
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S 150 905 100 895 1 1 6 N
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S 150 1005 100 995 1 1 6 N
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S 150 1105 100 1095 1 1 6 N
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S 150 1205 100 1195 1 1 6 N
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S 150 1305 100 1295 1 1 6 N
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S 150 1405 100 1395 1 1 6 N
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S 150 1505 100 1495 1 1 6 N
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X Pin_1 1 -200 1500 150 R 50 50 1 1 P
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X Pin_10 10 -200 600 150 R 50 50 1 1 P
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X Pin_11 11 -200 500 150 R 50 50 1 1 P
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X Pin_12 12 -200 400 150 R 50 50 1 1 P
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X Pin_13 13 -200 300 150 R 50 50 1 1 P
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X Pin_14 14 -200 200 150 R 50 50 1 1 P
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X Pin_15 15 -200 100 150 R 50 50 1 1 P
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X Pin_16 16 -200 0 150 R 50 50 1 1 P
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X Pin_17 17 -200 -100 150 R 50 50 1 1 P
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X Pin_18 18 -200 -200 150 R 50 50 1 1 P
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X Pin_19 19 -200 -300 150 R 50 50 1 1 P
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X Pin_2 2 -200 1400 150 R 50 50 1 1 P
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X Pin_20 20 -200 -400 150 R 50 50 1 1 P
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X Pin_21 21 -200 -500 150 R 50 50 1 1 P
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X Pin_22 22 -200 -600 150 R 50 50 1 1 P
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X Pin_23 23 -200 -700 150 R 50 50 1 1 P
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X Pin_24 24 -200 -800 150 R 50 50 1 1 P
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X Pin_25 25 -200 -900 150 R 50 50 1 1 P
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X Pin_26 26 -200 -1000 150 R 50 50 1 1 P
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X Pin_27 27 -200 -1100 150 R 50 50 1 1 P
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X Pin_28 28 -200 -1200 150 R 50 50 1 1 P
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X Pin_29 29 -200 -1300 150 R 50 50 1 1 P
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X Pin_3 3 -200 1300 150 R 50 50 1 1 P
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X Pin_30 30 -200 -1400 150 R 50 50 1 1 P
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X Pin_31 31 -200 -1500 150 R 50 50 1 1 P
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X Pin_32 32 -200 -1600 150 R 50 50 1 1 P
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X Pin_33 33 300 -1600 150 L 50 50 1 1 P
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X Pin_34 34 300 -1500 150 L 50 50 1 1 P
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X Pin_35 35 300 -1400 150 L 50 50 1 1 P
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X Pin_36 36 300 -1300 150 L 50 50 1 1 P
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X Pin_37 37 300 -1200 150 L 50 50 1 1 P
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X Pin_38 38 300 -1100 150 L 50 50 1 1 P
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X Pin_39 39 300 -1000 150 L 50 50 1 1 P
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X Pin_4 4 -200 1200 150 R 50 50 1 1 P
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X Pin_40 40 300 -900 150 L 50 50 1 1 P
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X Pin_41 41 300 -800 150 L 50 50 1 1 P
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X Pin_42 42 300 -700 150 L 50 50 1 1 P
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X Pin_43 43 300 -600 150 L 50 50 1 1 P
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X Pin_44 44 300 -500 150 L 50 50 1 1 P
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X Pin_45 45 300 -400 150 L 50 50 1 1 P
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X Pin_46 46 300 -300 150 L 50 50 1 1 P
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X Pin_47 47 300 -200 150 L 50 50 1 1 P
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X Pin_48 48 300 -100 150 L 50 50 1 1 P
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X Pin_49 49 300 0 150 L 50 50 1 1 P
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X Pin_5 5 -200 1100 150 R 50 50 1 1 P
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X Pin_50 50 300 100 150 L 50 50 1 1 P
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X Pin_51 51 300 200 150 L 50 50 1 1 P
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X Pin_52 52 300 300 150 L 50 50 1 1 P
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X Pin_53 53 300 400 150 L 50 50 1 1 P
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X Pin_54 54 300 500 150 L 50 50 1 1 P
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X Pin_55 55 300 600 150 L 50 50 1 1 P
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X Pin_56 56 300 700 150 L 50 50 1 1 P
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X Pin_57 57 300 800 150 L 50 50 1 1 P
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X Pin_58 58 300 900 150 L 50 50 1 1 P
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X Pin_59 59 300 1000 150 L 50 50 1 1 P
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X Pin_6 6 -200 1000 150 R 50 50 1 1 P
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X Pin_60 60 300 1100 150 L 50 50 1 1 P
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X Pin_61 61 300 1200 150 L 50 50 1 1 P
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X Pin_62 62 300 1300 150 L 50 50 1 1 P
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X Pin_63 63 300 1400 150 L 50 50 1 1 P
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X Pin_64 64 300 1500 150 L 50 50 1 1 P
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X Pin_7 7 -200 900 150 R 50 50 1 1 P
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X Pin_8 8 -200 800 150 R 50 50 1 1 P
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X Pin_9 9 -200 700 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_C_Small
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#
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DEF Device_C_Small C 0 10 N N 1 F N
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F0 "C" 10 70 50 H V L CNN
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F1 "Device_C_Small" 10 -80 50 H V L CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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C_*
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$ENDFPLIST
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DRAW
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P 2 0 1 13 -60 -20 60 -20 N
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P 2 0 1 12 -60 20 60 20 N
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X ~ 1 0 100 80 D 50 50 1 1 P
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X ~ 2 0 -100 80 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# GW_Connector_Micro_SD_SingleDet
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#
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DEF GW_Connector_Micro_SD_SingleDet J 0 40 Y Y 1 F N
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F0 "J" -650 700 50 H V C CNN
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F1 "GW_Connector_Micro_SD_SingleDet" 650 700 50 H V R CNN
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F2 "" 2050 700 50 H I C CNN
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F3 "" 0 100 50 H I C CNN
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ALIAS Micro_SD_Card_Det_Hirose_DM3AT_0
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$FPLIST
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microSD*
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$ENDFPLIST
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DRAW
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S -300 -275 -200 -325 0 1 0 F
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S -300 -175 -200 -225 0 1 0 F
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S -300 -75 -200 -125 0 1 0 F
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S -300 25 -200 -25 0 1 0 F
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S -300 125 -200 75 0 1 0 F
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S -300 225 -200 175 0 1 0 F
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S -300 325 -200 275 0 1 0 F
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S -300 425 -200 375 0 1 0 F
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P 6 0 1 10 650 600 650 650 -750 650 -750 -650 650 -650 650 -350 N
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P 11 0 1 10 -350 -350 -350 450 -50 450 100 600 150 600 150 550 250 550 300 600 800 600 800 -350 -350 -350 f
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X DAT2 1 -900 400 150 R 50 50 1 1 B
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X SHIELD 10 800 -500 150 L 50 50 1 1 P
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X DAT3/CD 2 -900 300 150 R 50 50 1 1 B
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X CMD 3 -900 200 150 R 50 50 1 1 I
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X VDD 4 -900 100 150 R 50 50 1 1 W
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X CLK 5 -900 0 150 R 50 50 1 1 I
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X VSS 6 -900 -100 150 R 50 50 1 1 W
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X DAT0 7 -900 -200 150 R 50 50 1 1 I
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X DAT1 8 -900 -300 150 R 50 50 1 1 I
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X DET 9 -900 -400 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# GW_Logic_74245BQ
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#
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DEF GW_Logic_74245BQ U 0 40 Y Y 1 F N
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F0 "U" 0 600 50 H V C CNN
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F1 "GW_Logic_74245BQ" 0 -600 50 H V C CNN
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F2 "stdpads:Nexperia_DHVFQFN-20_SOT764-1" 0 -650 50 H I C TNN
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F3 "" 0 100 60 H I C CNN
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DRAW
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S -200 550 200 -550 0 1 10 f
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X AtoB 1 -400 450 200 R 50 50 1 1 I
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X GND 10 -400 -450 200 R 50 50 1 1 W
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X B7 11 400 -450 200 L 50 50 1 1 B
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X B6 12 400 -350 200 L 50 50 1 1 B
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X B5 13 400 -250 200 L 50 50 1 1 B
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X B4 14 400 -150 200 L 50 50 1 1 B
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X B3 15 400 -50 200 L 50 50 1 1 B
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X B2 16 400 50 200 L 50 50 1 1 B
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X B1 17 400 150 200 L 50 50 1 1 B
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X B0 18 400 250 200 L 50 50 1 1 B
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X ~OE~ 19 400 350 200 L 50 50 1 1 I
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X A0 2 -400 350 200 R 50 50 1 1 B
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X Vcc 20 400 450 200 L 50 50 1 1 W
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X pad 21 -400 -450 200 R 50 50 1 1 W N
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X A1 3 -400 250 200 R 50 50 1 1 B
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X A2 4 -400 150 200 R 50 50 1 1 B
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X A3 5 -400 50 200 R 50 50 1 1 B
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X A4 6 -400 -50 200 R 50 50 1 1 B
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X A5 7 -400 -150 200 R 50 50 1 1 B
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X A6 8 -400 -250 200 R 50 50 1 1 B
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X A7 9 -400 -350 200 R 50 50 1 1 B
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ENDDRAW
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ENDDEF
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#
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# GW_Logic_Oscillator_4P
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#
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DEF GW_Logic_Oscillator_4P U 0 40 Y Y 1 F N
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F0 "U" 0 250 50 H V C CNN
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F1 "GW_Logic_Oscillator_4P" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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S -250 200 250 -100 0 1 10 f
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X EN 1 -350 100 100 R 50 50 1 1 I
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X GND 2 -350 0 100 R 50 50 1 1 W
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X Output 3 350 0 100 L 50 50 1 1 O
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X Vdd 4 350 100 100 L 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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# GW_PLD_5M80ZE68
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#
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DEF GW_PLD_5M80ZE68 U 0 40 Y Y 1 L N
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F0 "U" 0 -500 50 H V C CNN
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F1 "GW_PLD_5M80ZE68" 0 -600 50 H V C CNN
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F2 "stdpads:EQFP-64_10x10mm_P0.5mm" 0 -650 20 H I C CNN
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F3 "" 0 -550 50 H I C CNN
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$FPLIST
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*QFP*P0.5mm*
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$ENDFPLIST
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DRAW
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S -800 1650 800 -1650 1 1 10 f
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X IO1_2 1 -1000 1450 200 R 50 50 1 1 B
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X IO1_9 10 -1000 750 200 R 50 50 1 1 B
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X IO1_10 11 -1000 650 200 R 50 50 1 1 B
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X IO1_11 12 -1000 550 200 R 50 50 1 1 B
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X IO1_12 13 -1000 450 200 R 50 50 1 1 B
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X TMS 14 -1000 -1250 200 R 50 50 1 1 I
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X TDI 15 -1000 -1350 200 R 50 50 1 1 I
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X TCK 16 -1000 -1450 200 R 50 50 1 1 I C
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X TDO 17 -1000 -1550 200 R 50 50 1 1 O
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X IO1_13 18 -1000 350 200 R 50 50 1 1 B
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X IO1_14 19 -1000 250 200 R 50 50 1 1 B
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X IO1_3 2 -1000 1350 200 R 50 50 1 1 B
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X IO1_15 20 -1000 150 200 R 50 50 1 1 B
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X IO1_16 21 -1000 50 200 R 50 50 1 1 B
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X IO1_17 22 -1000 -50 200 R 50 50 1 1 B
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X VCCIO1 23 0 1850 200 D 50 50 1 1 W
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X IO1_18 24 -1000 -150 200 R 50 50 1 1 B
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X IO1_19 25 -1000 -250 200 R 50 50 1 1 B
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X IO1_20 26 -1000 -350 200 R 50 50 1 1 B
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X IO1_21 27 -1000 -450 200 R 50 50 1 1 B
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X IO1_22 28 -1000 -550 200 R 50 50 1 1 B
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X IO1_23 29 -1000 -650 200 R 50 50 1 1 B
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X IO1_4 3 -1000 1250 200 R 50 50 1 1 B
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X IO1_24 30 -1000 -750 200 R 50 50 1 1 B
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X IO1_25 31 -1000 -850 200 R 50 50 1 1 B
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X IO1_26 32 -1000 -950 200 R 50 50 1 1 B
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X IO1_27 33 -1000 -1050 200 R 50 50 1 1 B
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X IO2_52 34 1000 1550 200 L 50 50 1 1 B
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X IO2_53 35 1000 1450 200 L 50 50 1 1 B
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X IO2_54 36 1000 1350 200 L 50 50 1 1 B
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X IO2_55 37 1000 1250 200 L 50 50 1 1 B
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X IO2_56 38 1000 1150 200 L 50 50 1 1 B
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X VCCIO2 39 100 1850 200 D 50 50 1 1 W
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X IO1_5 4 -1000 1150 200 R 50 50 1 1 B
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X IO2_62/GCLK2 40 1000 1050 200 L 50 50 1 1 B C
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X VCCINT 41 -200 1850 200 D 50 50 1 1 W
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X IO2_64/GCLK3 42 1000 950 200 L 50 50 1 1 B C
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X IO2_66 43 1000 850 200 L 50 50 1 1 B
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X IO2_67 44 1000 750 200 L 50 50 1 1 B
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X IO2_68 45 1000 650 200 L 50 50 1 1 B
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X IO2_69 46 1000 550 200 L 50 50 1 1 B
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X IO2_70 47 1000 450 200 L 50 50 1 1 B
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X IO2_71 48 1000 350 200 L 50 50 1 1 B
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X IO2_72 49 1000 250 200 L 50 50 1 1 B
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X IO1_6 5 -1000 1050 200 R 50 50 1 1 B
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X IO2_73 50 1000 150 200 L 50 50 1 1 B
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X IO2_74 51 1000 50 200 L 50 50 1 1 B
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X IO2_75 52 1000 -50 200 L 50 50 1 1 B
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X IO2_76 53 1000 -150 200 L 50 50 1 1 B
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X IO2_77 54 1000 -250 200 L 50 50 1 1 B
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X IO2_78 55 1000 -350 200 L 50 50 1 1 B
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X IO2_81 56 1000 -450 200 L 50 50 1 1 B
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X VCCIO2 57 200 1850 200 D 50 50 1 1 W
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X IO2_82 58 1000 -550 200 L 50 50 1 1 B
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X IO2_83 59 1000 -650 200 L 50 50 1 1 B
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X VCCIO1 6 -100 1850 200 D 50 50 1 1 W
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X IO2_84 60 1000 -750 200 L 50 50 1 1 B
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X IO2_85 61 1000 -850 200 L 50 50 1 1 B
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X IO2_86 62 1000 -950 200 L 50 50 1 1 B
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X IO2_87 63 1000 -1050 200 L 50 50 1 1 B
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X IO1_1 64 -1000 1550 200 R 50 50 1 1 B
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X GND 65 0 -1850 200 U 50 50 1 1 W
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X IO1_7/GCLK0 7 -1000 950 200 R 50 50 1 1 B C
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X VCCINT 8 -300 1850 200 D 50 50 1 1 W
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X IO1_8/GCLK1 9 -1000 850 200 R 50 50 1 1 B C
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||||
ENDDRAW
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ENDDEF
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#
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# GW_RAM_Flash-4Mx16-TSOP1-48
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#
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DEF GW_RAM_Flash-4Mx16-TSOP1-48 U 0 20 Y Y 1 F N
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F0 "U" 0 1050 50 H V C CNN
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F1 "GW_RAM_Flash-4Mx16-TSOP1-48" 0 0 50 V V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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S -300 1000 300 -1700 0 1 10 f
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X GND 27 -500 -1600 200 R 50 50 0 0 W
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X VCC 37 -500 900 200 R 50 50 0 0 W
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||||
X A15 1 -500 -800 200 R 50 50 1 1 I
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X A20 10 -500 -1300 200 R 50 50 1 1 I
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X ~WE~ 11 500 -1500 200 L 50 50 1 1 I L
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X ~RESET~ 12 500 -800 200 L 50 50 1 1 I L
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X A21 13 -500 -1400 200 R 50 50 1 1 I
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X ~WP~ 14 500 -1100 200 L 50 50 1 1 I L
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X ~BY~ 15 500 -1200 200 L 50 50 1 1 I L
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X A18 16 -500 -1100 200 R 50 50 1 1 I
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X A17 17 -500 -1000 200 R 50 50 1 1 I
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X A7 18 -500 0 200 R 50 50 1 1 I
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X A6 19 -500 100 200 R 50 50 1 1 I
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X A14 2 -500 -700 200 R 50 50 1 1 I
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X A5 20 -500 200 200 R 50 50 1 1 I
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X A4 21 -500 300 200 R 50 50 1 1 I
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X A3 22 -500 400 200 R 50 50 1 1 I
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X A2 23 -500 500 200 R 50 50 1 1 I
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X A1 24 -500 600 200 R 50 50 1 1 I
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X A0 25 -500 700 200 R 50 50 1 1 I
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X ~CS~ 26 500 -1400 200 L 50 50 1 1 I L
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X ~OE~ 28 500 -1600 200 L 50 50 1 1 I L
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X D0 29 500 900 200 L 50 50 1 1 B
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X A13 3 -500 -600 200 R 50 50 1 1 I
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X D8 30 500 100 200 L 50 50 1 1 B
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X D1 31 500 800 200 L 50 50 1 1 B
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||||
X D9 32 500 0 200 L 50 50 1 1 B
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X D2 33 500 700 200 L 50 50 1 1 B
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||||
X D10 34 500 -100 200 L 50 50 1 1 B
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X D3 35 500 600 200 L 50 50 1 1 B
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X D11 36 500 -200 200 L 50 50 1 1 B
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X D4 38 500 500 200 L 50 50 1 1 B
|
||||
X D12 39 500 -300 200 L 50 50 1 1 B
|
||||
X A12 4 -500 -500 200 R 50 50 1 1 I
|
||||
X D5 40 500 400 200 L 50 50 1 1 B
|
||||
X D13 41 500 -400 200 L 50 50 1 1 B
|
||||
X D6 42 500 300 200 L 50 50 1 1 B
|
||||
X D14 43 500 -500 200 L 50 50 1 1 B
|
||||
X D7 44 500 200 200 L 50 50 1 1 B
|
||||
X D15/A22 45 500 -600 200 L 50 50 1 1 B
|
||||
X GND 46 -500 -1600 200 R 50 50 1 1 W
|
||||
X ~BYTE~ 47 500 -900 200 L 50 50 1 1 I L
|
||||
X A16 48 -500 -900 200 R 50 50 1 1 I
|
||||
X A11 5 -500 -400 200 R 50 50 1 1 I
|
||||
X A10 6 -500 -300 200 R 50 50 1 1 I
|
||||
X A9 7 -500 -200 200 R 50 50 1 1 I
|
||||
X A8 8 -500 -100 200 R 50 50 1 1 I
|
||||
X A19 9 -500 -1200 200 R 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Mechanical_Fiducial
|
||||
#
|
||||
DEF Mechanical_Fiducial FID 0 20 Y Y 1 F N
|
||||
F0 "FID" 0 200 50 H V C CNN
|
||||
F1 "Mechanical_Fiducial" 0 125 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Fiducial*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 0 0 50 0 1 20 f
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Mechanical_MountingHole_Pad
|
||||
#
|
||||
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
|
||||
F0 "H" 0 250 50 H V C CNN
|
||||
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
MountingHole*Pad*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C 0 50 50 0 1 50 N
|
||||
X 1 1 0 -100 100 U 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Regulator_Linear_LD1117S33TR_SOT223
|
||||
#
|
||||
DEF Regulator_Linear_LD1117S33TR_SOT223 U 0 10 Y Y 1 F N
|
||||
F0 "U" -150 125 50 H V C CNN
|
||||
F1 "Regulator_Linear_LD1117S33TR_SOT223" 0 125 50 H V L CNN
|
||||
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 200 50 H I C CNN
|
||||
F3 "" 100 -250 50 H I C CNN
|
||||
ALIAS AP1117-18 AP1117-25 AP1117-33 AP1117-50 LD1117S33TR_SOT223 LD1117S12TR_SOT223 LD1117S18TR_SOT223 LD1117S25TR_SOT223 LD1117S50TR_SOT223 NCP1117-12_SOT223 NCP1117-1.5_SOT223 NCP1117-1.8_SOT223 NCP1117-2.0_SOT223 NCP1117-2.5_SOT223 NCP1117-2.85_SOT223 NCP1117-3.3_SOT223 NCP1117-5.0_SOT223 AMS1117-1.5 AMS1117-1.8 AMS1117-2.5 AMS1117-2.85 AMS1117-3.3 AMS1117-5.0
|
||||
$FPLIST
|
||||
SOT?223*TabPin2*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -200 -200 200 75 0 1 10 f
|
||||
X GND 1 0 -300 100 U 50 50 1 1 W
|
||||
X VO 2 300 0 100 L 50 50 1 1 w
|
||||
X VI 3 -300 0 100 R 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+3V3
|
||||
#
|
||||
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+3V3" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS +3.3V
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +3V3 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+5V
|
||||
#
|
||||
DEF power_+5V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+5V" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +5V 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_GND
|
||||
#
|
||||
DEF power_GND #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -250 50 H I C CNN
|
||||
F1 "power_GND" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
|
||||
X GND 1 0 0 0 D 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,265 +0,0 @@
|
|||
update=Wednesday, June 24, 2020 at 09:41:54 PM
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=ROMSIMM.net
|
||||
CopperLayerCount=4
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.15
|
||||
MinViaDiameter=0.5
|
||||
MinViaDrill=0.2
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.15
|
||||
TrackWidth2=0.2
|
||||
TrackWidth3=0.24
|
||||
TrackWidth4=0.25
|
||||
TrackWidth5=0.3
|
||||
TrackWidth6=0.35
|
||||
TrackWidth7=0.4
|
||||
TrackWidth8=0.45
|
||||
TrackWidth9=0.5
|
||||
TrackWidth10=0.6
|
||||
TrackWidth11=0.8
|
||||
TrackWidth12=1
|
||||
ViaDiameter1=0.5
|
||||
ViaDrill1=0.2
|
||||
ViaDiameter2=0.6
|
||||
ViaDrill2=0.3
|
||||
ViaDiameter3=0.8
|
||||
ViaDrill3=0.4
|
||||
ViaDiameter4=1
|
||||
ViaDrill4=0.5
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.15
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.15
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.07619999999999999
|
||||
SolderMaskMinWidth=0.1524
|
||||
SolderPasteClearance=-0.03809999999999999
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=1
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=1
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.15
|
||||
TrackWidth=0.15
|
||||
ViaDiameter=0.5
|
||||
ViaDrill=0.2
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,3 +0,0 @@
|
|||
(fp_lib_table
|
||||
(lib (name stdpads)(type KiCad)(uri "$(KIPRJMOD)/../../stdpads.pretty")(options "")(descr ""))
|
||||
)
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
(sym_lib_table
|
||||
(lib (name GW_RAM)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_RAM.lib")(options "")(descr ""))
|
||||
(lib (name GW_Logic)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_Logic.lib")(options "")(descr ""))
|
||||
(lib (name GW_PLD)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_PLD.lib")(options "")(descr ""))
|
||||
(lib (name GW_Connector)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_Connector.lib")(options "")(descr ""))
|
||||
)
|
||||
Loading…
Reference in New Issue