Migrate to KiCAD 6
This commit is contained in:
Zane Kaminski
parent
31e25097b3
commit
ed6829c92a
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@ -14,6 +14,7 @@ _autosave-*
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*-save.pro
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*-save.kicad_pcb
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fp-info-cache
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ROMSIMM-backups/*
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# Netlist files (exported from Eeschema)
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*.net
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Binary file not shown.
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Before Width: | Height: | Size: 271 KiB |
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Before Width: | Height: | Size: 420 KiB |
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@ -200,7 +200,7 @@ ENDDEF
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#
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DEF GW_Logic_74245 U 0 40 Y Y 1 F N
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F0 "U" 0 600 50 H V C CNN
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F1 "GW_Logic_74245" 0 -600 50 H V C CNN
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F1 "GW_Logic_74245" 0 0 50 V V C CNN
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F2 "" 0 -650 50 H I C TNN
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F3 "" 0 100 60 H I C CNN
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DRAW
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@ -338,28 +338,33 @@ X VI 3 -300 0 100 R 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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# Switch_SW_DIP_x02
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# Switch_SW_DIP_x03
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#
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DEF Switch_SW_DIP_x02 SW 0 0 Y N 1 F N
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F0 "SW" 0 250 50 H V C CNN
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F1 "Switch_SW_DIP_x02" 0 -150 50 H V C CNN
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DEF Switch_SW_DIP_x03 SW 0 0 Y N 1 F N
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F0 "SW" 0 350 50 H V C CNN
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F1 "Switch_SW_DIP_x03" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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SW?DIP?x2*
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SW?DIP?x3*
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$ENDFPLIST
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DRAW
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C -80 0 20 0 0 0 N
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C -80 100 20 0 0 0 N
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C -80 200 20 0 0 0 N
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C 80 0 20 0 0 0 N
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C 80 100 20 0 0 0 N
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S -150 200 150 -100 0 1 10 f
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C 80 200 20 0 0 0 N
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S -150 300 150 -100 0 1 10 f
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P 2 0 0 0 -60 5 93 46 N
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P 2 0 0 0 -60 105 93 146 N
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X ~ 1 -300 100 200 R 50 50 1 1 P
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X ~ 2 -300 0 200 R 50 50 1 1 P
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X ~ 3 300 0 200 L 50 50 1 1 P
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X ~ 4 300 100 200 L 50 50 1 1 P
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P 2 0 0 0 -60 205 93 246 N
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X ~ 1 -300 200 200 R 50 50 1 1 P
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X ~ 2 -300 100 200 R 50 50 1 1 P
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X ~ 3 -300 0 200 R 50 50 1 1 P
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X ~ 4 300 0 200 L 50 50 1 1 P
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X ~ 5 300 100 200 L 50 50 1 1 P
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X ~ 6 300 200 200 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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43179
ROMSIMM.kicad_pcb
43179
ROMSIMM.kicad_pcb
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,75 @@
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{
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"board": {
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"active_layer": 0,
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"active_layer_preset": "All Layers",
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"auto_track_width": true,
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"hidden_nets": [],
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"high_contrast_mode": 0,
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"net_color_mode": 1,
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"opacity": {
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"pads": 1.0,
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"tracks": 1.0,
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"vias": 1.0,
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"zones": 0.6
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},
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"ratsnest_display_mode": 0,
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"selection_filter": {
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"dimensions": true,
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"footprints": true,
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"graphics": true,
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"keepouts": true,
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"lockedItems": true,
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"otherItems": true,
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"pads": true,
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"text": true,
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"tracks": true,
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"vias": true,
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"zones": true
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},
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"visible_items": [
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0,
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1,
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2,
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3,
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4,
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5,
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8,
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9,
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10,
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11,
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12,
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13,
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14,
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15,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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27,
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28,
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33,
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34,
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35,
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36
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],
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"visible_layers": "fffffff_ffffffff",
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"zone_display_mode": 0
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},
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"meta": {
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"filename": "ROMSIMM.kicad_prl",
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"version": 3
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},
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"project": {
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"files": []
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}
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}
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@ -0,0 +1,218 @@
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{
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"board": {
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"design_settings": {
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"defaults": {
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"board_outline_line_width": 0.15,
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"copper_line_width": 0.19999999999999998,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_upright": false,
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"courtyard_line_width": 0.049999999999999996,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": false,
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.09999999999999999,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 0.0,
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"height": 1.12,
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"width": 2.44
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},
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"silk_line_width": 0.15,
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"silk_text_italic": false,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.15,
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"silk_text_upright": false,
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"zones": {
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"45_degree_only": false,
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"min_clearance": 0.154
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}
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},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"meta": {
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"filename": "board_design_settings.json",
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"copper_edge_clearance": "error",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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},
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"rule_severitieslegacy_courtyards_overlap": true,
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"rule_severitieslegacy_no_courtyard_defined": false,
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"rules": {
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"allow_blind_buried_vias": false,
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"allow_microvias": false,
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_copper_edge_clearance": 0.075,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_silk_clearance": 0.0,
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"min_through_hole_diameter": 0.19999999999999998,
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"min_track_width": 0.15,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.5,
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"use_height_for_length_calcs": true
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},
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"track_widths": [
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0.0,
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0.2,
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0.25,
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0.3,
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0.35,
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0.4,
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0.45,
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0.5,
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0.6,
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0.8,
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1.0
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],
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"via_dimensions": [
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||||
{
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"diameter": 0.0,
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||||
"drill": 0.0
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||||
},
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||||
{
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||||
"diameter": 0.6,
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||||
"drill": 0.3
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||||
},
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||||
{
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||||
"diameter": 0.8,
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||||
"drill": 0.4
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||||
},
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||||
{
|
||||
"diameter": 1.0,
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||||
"drill": 0.5
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||||
}
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||||
],
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||||
"zones_allow_external_fillets": false,
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||||
"zones_use_no_outline": true
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||||
},
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"layer_presets": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_symbol_libs": []
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},
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"meta": {
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"filename": "ROMSIMM.kicad_pro",
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"version": 1
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},
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"net_settings": {
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"classes": [
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{
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"bus_width": 12.0,
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"clearance": 0.15,
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||||
"diff_pair_gap": 0.25,
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||||
"diff_pair_via_gap": 0.25,
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||||
"diff_pair_width": 0.2,
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||||
"line_style": 0,
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||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
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"name": "Default",
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||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
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||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.15,
|
||||
"via_diameter": 0.5,
|
||||
"via_drill": 0.2,
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"wire_width": 6.0
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||||
}
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],
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"meta": {
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"version": 2
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||||
},
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"net_colors": null
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},
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"pcbnew": {
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"last_paths": {
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||||
"gencad": "",
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||||
"idf": "",
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"netlist": "ROMSIMM.net",
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"specctra_dsn": "",
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"step": "",
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"vrml": ""
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},
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||||
"page_layout_descr_file": ""
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},
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"schematic": {
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"drawing": {
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||||
"default_text_size": 50,
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||||
"label_size_ratio": 0.25,
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||||
"pin_symbol_size": 0,
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||||
"text_offset_ratio": 0.08
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||||
},
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||||
"legacy_lib_dir": "",
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"legacy_lib_list": [],
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"net_format_name": "Pcbnew",
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||||
"page_layout_descr_file": "",
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"plot_directory": "",
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||||
"spice_adjust_passive_values": false,
|
||||
"subpart_first_id": 65,
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||||
"subpart_id_separator": 0
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},
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||||
"sheets": [],
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||||
"text_variables": {}
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}
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264
ROMSIMM.pro
264
ROMSIMM.pro
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@ -1,264 +0,0 @@
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update=Saturday, April 03, 2021 at 03:29:41 AM
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=ROMSIMM.net
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CopperLayerCount=4
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||||
BoardThickness=1.6
|
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AllowMicroVias=0
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AllowBlindVias=0
|
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RequireCourtyardDefinitions=0
|
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ProhibitOverlappingCourtyards=1
|
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MinTrackWidth=0.15
|
||||
MinViaDiameter=0.5
|
||||
MinViaDrill=0.2
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.15
|
||||
TrackWidth2=0.2
|
||||
TrackWidth3=0.25
|
||||
TrackWidth4=0.3
|
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TrackWidth5=0.35
|
||||
TrackWidth6=0.4
|
||||
TrackWidth7=0.45
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||||
TrackWidth8=0.5
|
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TrackWidth9=0.6
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TrackWidth10=0.8
|
||||
TrackWidth11=1
|
||||
ViaDiameter1=0.5
|
||||
ViaDrill1=0.2
|
||||
ViaDiameter2=0.6
|
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ViaDrill2=0.3
|
||||
ViaDiameter3=0.8
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ViaDrill3=0.4
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ViaDiameter4=1
|
||||
ViaDrill4=0.5
|
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dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
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SilkLineWidth=0.15
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.15
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.075
|
||||
SolderMaskMinWidth=0.09999999999999999
|
||||
SolderPasteClearance=-0.03809999999999999
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=1
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
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206
ROMSIMM.sch
206
ROMSIMM.sch
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$EndSCHEMATC
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|
|
|
|||
Loading…
Reference in New Issue