|
ROMSIMM-B_Cu.gbl
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-B_Mask.gbs
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-B_Paste.gbp
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-B_SilkS.gbo
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-bottom-pos.csv
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-bottom.pos
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-drl_map.ps
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-Edge_Cuts.gm1
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-F_Cu.gtl
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-F_Mask.gts
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-F_Paste.gtp
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-F_SilkS.gto
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-In1_Cu.g2
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-In2_Cu.g3
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-top-pos.csv
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM-top.pos
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
|
ROMSIMM.drl
|
As submitted to JLCPCB
|
2020-05-17 14:51:52 -04:00 |
