45 lines
1.4 KiB
Coq
45 lines
1.4 KiB
Coq
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// out_mix.v
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`timescale 1 ps / 1 ps
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module out_mix (
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input wire clk, // Output.clk
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output reg de, // .de
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output reg h_sync, // .h_sync
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output reg v_sync, // .v_sync
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output reg [23:0] data, // .data
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output reg vid_clk, // input.vid_clk
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input wire [1:0] vid_datavalid, // .vid_datavalid
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input wire [1:0] vid_h_sync, // .vid_h_sync
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input wire [1:0] vid_v_sync, // .vid_v_sync
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input wire [47:0] vid_data, // .vid_data
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input wire underflow, // .underflow
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input wire vid_mode_change, // .vid_mode_change
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input wire [1:0] vid_std, // .vid_std
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input wire [1:0] vid_f, // .vid_f
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input wire [1:0] vid_h, // .vid_h
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input wire [1:0] vid_v // .vid_v
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);
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reg r_de;
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reg r_h_sync;
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reg r_v_sync;
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reg [23:0] r_data;
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always @(posedge clk) begin
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vid_clk <= ~vid_clk;
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if(~vid_clk) begin
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{r_de,de} <= vid_datavalid;
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{r_h_sync, h_sync} <= vid_h_sync;
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{r_v_sync, v_sync} <= vid_v_sync;
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{r_data, data} <= vid_data;
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end else begin
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de <= r_de;
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h_sync <= r_h_sync;
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v_sync <= r_v_sync;
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data <= r_data;
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end
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end
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endmodule
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