Move sources to src.

files.qip

@@ -1,18 +1,16 @@
-set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
+set_global_assignment -name QIP_FILE src/tg68k/TG68K.qip
-set_global_assignment -name VERILOG_FILE scsi.v
+set_global_assignment -name SYSTEMVERILOG_FILE src/sdram.sv
-set_global_assignment -name VERILOG_FILE ncr5380.v
+set_global_assignment -name VERILOG_FILE src/scsi.v
-set_global_assignment -name VERILOG_FILE floppy_track_encoder.v
+set_global_assignment -name VERILOG_FILE src/ncr5380.v
-set_global_assignment -name VERILOG_FILE floppy.v
+set_global_assignment -name VERILOG_FILE src/floppy_track_encoder.v
-set_global_assignment -name SYSTEMVERILOG_FILE ps2_kbd.sv
+set_global_assignment -name VERILOG_FILE src/floppy.v
-set_global_assignment -name VERILOG_FILE ps2_mouse.v
+set_global_assignment -name SYSTEMVERILOG_FILE src/ps2_kbd.sv
-set_global_assignment -name VHDL_FILE TG68K_Pack.vhd
+set_global_assignment -name VERILOG_FILE src/ps2_mouse.v
-set_global_assignment -name VHDL_FILE TG68K_ALU.vhd
+set_global_assignment -name VERILOG_FILE src/scc.v
-set_global_assignment -name VHDL_FILE TG68KdotC_Kernel.vhd
+set_global_assignment -name VERILOG_FILE src/iwm.v
-set_global_assignment -name VERILOG_FILE scc.v
+set_global_assignment -name VERILOG_FILE src/via.v
-set_global_assignment -name VERILOG_FILE iwm.v
+set_global_assignment -name VERILOG_FILE src/addrDecoder.v
-set_global_assignment -name VERILOG_FILE via.v
+set_global_assignment -name VERILOG_FILE src/addrController_top.v
-set_global_assignment -name VERILOG_FILE addrDecoder.v
+set_global_assignment -name VERILOG_FILE src/dataController_top.v
-set_global_assignment -name VERILOG_FILE addrController_top.v
+set_global_assignment -name VERILOG_FILE src/video.v
-set_global_assignment -name VERILOG_FILE dataController_top.v
-set_global_assignment -name VERILOG_FILE video.v
 set_global_assignment -name SYSTEMVERILOG_FILE MacPlus.sv

src/floppy_track_encoder.v

@@ -19,17 +19,19 @@ module floppy_track_encoder (
    input 			sides,
    input [6:0] 	track, // current track
 
-	output [21:0] 	addr,   // address to fetch from
+	output reg [21:0] 	addr,   // address to fetch from
    input [7:0] 	idata,
 			     
    output [7:0] 	odata 
 );
 
-assign addr = 
+always @(posedge clk) begin
-	{ 3'b00, soff, 9'd0 } +                 // sector offset * 512 for two sides
+	addr <= 
-	(sides?{ 3'b00, soff, 9'd0 }:22'd0) +   // another sector offset * 512 for two sides
+		{ 3'b00, soff, 9'd0 } +                 // sector offset * 512 for two sides
-	(side?{ 9'd0, spt, 9'd0 }:22'd0) +      // side * sectors * 512
+		(sides?{ 3'b00, soff, 9'd0 }:22'd0) +   // another sector offset * 512 for two sides
-	{ 9'd0, sector, src_offset };           // offset within track
+		(side?{ 9'd0, spt, 9'd0 }:22'd0) +      // side * sectors * 512
+		{ 9'd0, sector, src_offset };           // offset within track
+end
 
    // number of sectors on current track
    wire [3:0] spt =

src/tg68k/TG68K.qip

@@ -0,0 +1,3 @@
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) TG68K_ALU.vhd ]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) TG68K_Pack.vhd ]
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) TG68KdotC_Kernel.vhd ]