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Update sys.

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sorgelig 2019-03-09 05:31:23 +08:00
parent f05ae1457a
commit 6ae0f8d4f1
44 changed files with 5585 additions and 9009 deletions
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376
MacPlus-lite.qsf
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@ -1,376 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
# Date created = 01:53:32 April 20, 2017
#
# -------------------------------------------------------------------------- #
set_global_assignment -name VERILOG_MACRO "LITE=1"
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.1 Standard Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_global_assignment -name SEED 1
#============================================================
# ADC
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
set_location_assignment PIN_U9 -to ADC_CONVST
set_location_assignment PIN_V10 -to ADC_SCK
set_location_assignment PIN_AC4 -to ADC_SDI
set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
#============================================================
# SDIO
#============================================================
set_location_assignment PIN_AF25 -to SDIO_DAT[0]
set_location_assignment PIN_AF23 -to SDIO_DAT[1]
set_location_assignment PIN_AD26 -to SDIO_DAT[2]
set_location_assignment PIN_AF28 -to SDIO_DAT[3]
set_location_assignment PIN_AF27 -to SDIO_CMD
set_location_assignment PIN_AH26 -to SDIO_CLK
set_location_assignment PIN_AH7 -to SDIO_CD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD
#============================================================
# VGA
#============================================================
set_location_assignment PIN_AE17 -to VGA_R[0]
set_location_assignment PIN_AE20 -to VGA_R[1]
set_location_assignment PIN_AF20 -to VGA_R[2]
set_location_assignment PIN_AH18 -to VGA_R[3]
set_location_assignment PIN_AH19 -to VGA_R[4]
set_location_assignment PIN_AF21 -to VGA_R[5]
set_location_assignment PIN_AE19 -to VGA_G[0]
set_location_assignment PIN_AG15 -to VGA_G[1]
set_location_assignment PIN_AF18 -to VGA_G[2]
set_location_assignment PIN_AG18 -to VGA_G[3]
set_location_assignment PIN_AG19 -to VGA_G[4]
set_location_assignment PIN_AG20 -to VGA_G[5]
set_location_assignment PIN_AG21 -to VGA_B[0]
set_location_assignment PIN_AA20 -to VGA_B[1]
set_location_assignment PIN_AE22 -to VGA_B[2]
set_location_assignment PIN_AF22 -to VGA_B[3]
set_location_assignment PIN_AH23 -to VGA_B[4]
set_location_assignment PIN_AH21 -to VGA_B[5]
set_location_assignment PIN_AH22 -to VGA_HS
set_location_assignment PIN_AG24 -to VGA_VS
set_location_assignment PIN_AH27 -to VGA_EN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_*
#============================================================
# AUDIO
#============================================================
set_location_assignment PIN_AC24 -to AUDIO_L
set_location_assignment PIN_AE25 -to AUDIO_R
set_location_assignment PIN_AG26 -to AUDIO_SPDIF
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_*
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_*
#============================================================
# SDRAM
#============================================================
set_location_assignment PIN_Y11 -to SDRAM_A[0]
set_location_assignment PIN_AA26 -to SDRAM_A[1]
set_location_assignment PIN_AA13 -to SDRAM_A[2]
set_location_assignment PIN_AA11 -to SDRAM_A[3]
set_location_assignment PIN_W11 -to SDRAM_A[4]
set_location_assignment PIN_Y19 -to SDRAM_A[5]
set_location_assignment PIN_AB23 -to SDRAM_A[6]
set_location_assignment PIN_AC23 -to SDRAM_A[7]
set_location_assignment PIN_AC22 -to SDRAM_A[8]
set_location_assignment PIN_C12 -to SDRAM_A[9]
set_location_assignment PIN_AB26 -to SDRAM_A[10]
set_location_assignment PIN_AD17 -to SDRAM_A[11]
set_location_assignment PIN_D12 -to SDRAM_A[12]
set_location_assignment PIN_Y17 -to SDRAM_BA[0]
set_location_assignment PIN_AB25 -to SDRAM_BA[1]
set_location_assignment PIN_E8 -to SDRAM_DQ[0]
set_location_assignment PIN_V12 -to SDRAM_DQ[1]
set_location_assignment PIN_D11 -to SDRAM_DQ[2]
set_location_assignment PIN_W12 -to SDRAM_DQ[3]
set_location_assignment PIN_AH13 -to SDRAM_DQ[4]
set_location_assignment PIN_D8 -to SDRAM_DQ[5]
set_location_assignment PIN_AH14 -to SDRAM_DQ[6]
set_location_assignment PIN_AF7 -to SDRAM_DQ[7]
set_location_assignment PIN_AE24 -to SDRAM_DQ[8]
set_location_assignment PIN_AD23 -to SDRAM_DQ[9]
set_location_assignment PIN_AE6 -to SDRAM_DQ[10]
set_location_assignment PIN_AE23 -to SDRAM_DQ[11]
set_location_assignment PIN_AG14 -to SDRAM_DQ[12]
set_location_assignment PIN_AD5 -to SDRAM_DQ[13]
set_location_assignment PIN_AF4 -to SDRAM_DQ[14]
set_location_assignment PIN_AH3 -to SDRAM_DQ[15]
set_location_assignment PIN_AG13 -to SDRAM_DQML
set_location_assignment PIN_AF13 -to SDRAM_DQMH
set_location_assignment PIN_AD20 -to SDRAM_CLK
set_location_assignment PIN_AG10 -to SDRAM_CKE
set_location_assignment PIN_AA19 -to SDRAM_nWE
set_location_assignment PIN_AA18 -to SDRAM_nCAS
set_location_assignment PIN_Y18 -to SDRAM_nCS
set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
# I/O
#============================================================
set_location_assignment PIN_Y15 -to LED_USER
set_location_assignment PIN_AA15 -to LED_HDD
set_location_assignment PIN_AG28 -to LED_POWER
set_location_assignment PIN_AH24 -to BTN_USER
set_location_assignment PIN_AG25 -to BTN_OSD
set_location_assignment PIN_AG23 -to BTN_RESET
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_*
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_*
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
set_location_assignment PIN_T11 -to HDMI_LRCLK
set_location_assignment PIN_U11 -to HDMI_MCLK
set_location_assignment PIN_T12 -to HDMI_SCLK
set_location_assignment PIN_AG5 -to HDMI_TX_CLK
set_location_assignment PIN_AD19 -to HDMI_TX_DE
set_location_assignment PIN_AD12 -to HDMI_TX_D[0]
set_location_assignment PIN_AE12 -to HDMI_TX_D[1]
set_location_assignment PIN_W8 -to HDMI_TX_D[2]
set_location_assignment PIN_Y8 -to HDMI_TX_D[3]
set_location_assignment PIN_AD11 -to HDMI_TX_D[4]
set_location_assignment PIN_AD10 -to HDMI_TX_D[5]
set_location_assignment PIN_AE11 -to HDMI_TX_D[6]
set_location_assignment PIN_Y5 -to HDMI_TX_D[7]
set_location_assignment PIN_AF10 -to HDMI_TX_D[8]
set_location_assignment PIN_Y4 -to HDMI_TX_D[9]
set_location_assignment PIN_AE9 -to HDMI_TX_D[10]
set_location_assignment PIN_AB4 -to HDMI_TX_D[11]
set_location_assignment PIN_AE7 -to HDMI_TX_D[12]
set_location_assignment PIN_AF6 -to HDMI_TX_D[13]
set_location_assignment PIN_AF8 -to HDMI_TX_D[14]
set_location_assignment PIN_AF5 -to HDMI_TX_D[15]
set_location_assignment PIN_AE4 -to HDMI_TX_D[16]
set_location_assignment PIN_AH2 -to HDMI_TX_D[17]
set_location_assignment PIN_AH4 -to HDMI_TX_D[18]
set_location_assignment PIN_AH5 -to HDMI_TX_D[19]
set_location_assignment PIN_AH6 -to HDMI_TX_D[20]
set_location_assignment PIN_AG6 -to HDMI_TX_D[21]
set_location_assignment PIN_AF9 -to HDMI_TX_D[22]
set_location_assignment PIN_AE8 -to HDMI_TX_D[23]
set_location_assignment PIN_T8 -to HDMI_TX_HS
set_location_assignment PIN_AF11 -to HDMI_TX_INT
set_location_assignment PIN_V13 -to HDMI_TX_VS
#============================================================
# KEY
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
set_location_assignment PIN_AH17 -to KEY[0]
set_location_assignment PIN_AH16 -to KEY[1]
#============================================================
# LED
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
set_location_assignment PIN_W15 -to LED[0]
set_location_assignment PIN_AA24 -to LED[1]
set_location_assignment PIN_V16 -to LED[2]
set_location_assignment PIN_V15 -to LED[3]
set_location_assignment PIN_AF26 -to LED[4]
set_location_assignment PIN_AE26 -to LED[5]
set_location_assignment PIN_Y16 -to LED[6]
set_location_assignment PIN_AA23 -to LED[7]
#============================================================
# SW
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_location_assignment PIN_Y24 -to SW[0]
set_location_assignment PIN_W24 -to SW[1]
set_location_assignment PIN_W21 -to SW[2]
set_location_assignment PIN_W20 -to SW[3]
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
set_global_assignment -name VERILOG_FILE scsi.v
set_global_assignment -name VERILOG_FILE ncr5380.v
set_global_assignment -name VERILOG_FILE floppy_track_encoder.v
set_global_assignment -name VERILOG_FILE floppy.v
set_global_assignment -name SYSTEMVERILOG_FILE ps2_kbd.sv
set_global_assignment -name VERILOG_FILE ps2_mouse.v
set_global_assignment -name VHDL_FILE TG68K_Pack.vhd
set_global_assignment -name VHDL_FILE TG68K_ALU.vhd
set_global_assignment -name VHDL_FILE TG68KdotC_Kernel.vhd
set_global_assignment -name VERILOG_FILE scc.v
set_global_assignment -name VERILOG_FILE iwm.v
set_global_assignment -name VERILOG_FILE via.v
set_global_assignment -name VERILOG_FILE addrDecoder.v
set_global_assignment -name VERILOG_FILE addrController_top.v
set_global_assignment -name VERILOG_FILE dataController_top.v
set_global_assignment -name VERILOG_FILE video.v
set_global_assignment -name SYSTEMVERILOG_FILE MacPlus.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

16
MacPlus-lite.srf
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@ -1,16 +0,0 @@
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Synthesized away node \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|outclk_wire\[2\]\"" { } { } 0 14320 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(129): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(134): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21074 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
{ "" "" "" "sysmem_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}

1
MacPlus.qpf
View File

@ -29,4 +29,3 @@ DATE = "04:04:47 October 16, 2017"
# Revisions
PROJECT_REVISION = "MacPlus"
PROJECT_REVISION = "MacPlus-lite"

42
MacPlus.qsf
View File

@ -27,7 +27,7 @@ set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA6U23I7
set_global_assignment -name TOP_LEVEL_ENTITY sys_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.1 Standard Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
@ -50,6 +50,8 @@ set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
set_global_assignment -name SEED 1
#============================================================
@ -67,19 +69,6 @@ set_location_assignment PIN_AD4 -to ADC_SDO
#============================================================
# ARDUINO
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
set_location_assignment PIN_U14 -to ARDUINO_IO[4]
set_location_assignment PIN_U13 -to ARDUINO_IO[5]
@ -87,12 +76,22 @@ set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
#============================================================
# USER PORT
#============================================================
set_location_assignment PIN_AF15 -to USER_IO[5]
set_location_assignment PIN_AG16 -to USER_IO[4]
set_location_assignment PIN_AH11 -to USER_IO[3]
set_location_assignment PIN_AH12 -to USER_IO[2]
set_location_assignment PIN_AH9 -to USER_IO[1]
set_location_assignment PIN_AG11 -to USER_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_IO[*]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to USER_IO[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to USER_IO[*]
#============================================================
# SDIO
@ -353,8 +352,7 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
set_global_assignment -name CDF_FILE jtag.cdf
set_global_assignment -name QIP_FILE sys/sys.qip
set_global_assignment -name QSYS_FILE sys/vip.qsys
set_global_assignment -name SYSTEMVERILOG_FILE sdram.sv
set_global_assignment -name QIP_FILE sdram.qip
set_global_assignment -name VERILOG_FILE scsi.v
set_global_assignment -name VERILOG_FILE ncr5380.v
set_global_assignment -name VERILOG_FILE floppy_track_encoder.v

27
MacPlus.sv
View File

@ -48,6 +48,8 @@ module emu
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
output LED_USER, // 1 - ON, 0 - OFF.
@ -94,9 +96,28 @@ module emu
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE
output SDRAM_nWE,
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR,
// Open-drain User port.
// 0 - D+/RX
// 1 - D-/TX
// 2..5 - USR1..USR4
// Set USER_OUT to 1 to read from USER_IN.
input [5:0] USER_IN,
output [5:0] USER_OUT,
input OSD_STATUS
);
assign USER_OUT = '1;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
@ -121,7 +142,7 @@ localparam CONF_STR = {
"O5,Speed,Normal,Turbo;",
"-;",
"R6,Reset;",
"V,v1.00.",`BUILD_DATE
"V,v",`BUILD_DATE
};
//////////////////// CLOCKS ///////////////////
@ -284,6 +305,8 @@ assign VGA_G = {8{pixelOut}};
assign VGA_B = {8{pixelOut}};
assign CLK_VIDEO = clk_sys;
assign CE_PIXEL = cepix;
assign VGA_F1 = 0;
assign VGA_SL = 0;
wire screenWrite;
always @(*) begin

2
sdram.qip Normal file
View File

@ -0,0 +1,2 @@
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sdram.sv ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sdram.sdc ]

17
sdram.sdc Normal file
View File

@ -0,0 +1,17 @@
derive_pll_clocks
create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-name SDRAM_CLK [get_ports {SDRAM_CLK}]
derive_clock_uncertainty
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
set_multicycle_path -from [get_clocks {SDRAM_CLK}] \
-to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-setup 2
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]

128
sys/alsa.sv Normal file
View File

@ -0,0 +1,128 @@
//============================================================================
//
// ALSA sound support for MiSTer
// (c)2019 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module alsa
(
input reset,
input ram_clk,
output reg [28:0] ram_address,
output reg [7:0] ram_burstcount,
input ram_waitrequest,
input [63:0] ram_readdata,
input ram_readdatavalid,
output reg ram_read,
input spi_ss,
input spi_sck,
input spi_mosi,
output reg [15:0] pcm_l,
output reg [15:0] pcm_r
);
reg spi_new = 0;
reg [127:0] spi_data;
always @(posedge spi_sck, posedge spi_ss) begin
reg [7:0] mosi;
reg [6:0] spicnt = 0;
if(spi_ss) spicnt <= 0;
else begin
mosi <= {mosi[6:0],spi_mosi};
spicnt <= spicnt + 1'd1;
if(&spicnt[2:0]) begin
spi_data[{spicnt[6:3],3'b000} +:8] <= {mosi[6:0],spi_mosi};
spi_new <= &spicnt;
end
end
end
reg [31:0] buf_addr;
reg [31:0] buf_len;
reg [31:0] buf_wptr = 0;
always @(posedge ram_clk) begin
reg n1,n2,n3;
reg [127:0] data1,data2;
n1 <= spi_new;
n2 <= n1;
n3 <= n2;
data1 <= spi_data;
data2 <= data1;
if(~n3 & n2) {buf_wptr,buf_len,buf_addr} <= data2[95:0];
end
reg [31:0] buf_rptr = 0;
always @(posedge ram_clk) begin
reg got_first = 0;
reg ready = 0;
reg ud;
reg [31:0] readdata;
if(~ram_waitrequest) ram_read <= 0;
if(ram_readdatavalid && ram_burstcount) begin
ram_burstcount <= 0;
ready <= 1;
readdata <= ud ? ram_readdata[63:32] : ram_readdata[31:0];
if(buf_rptr[31:2] >= buf_len[31:2]) buf_rptr <= 0;
end
if(reset) {ready, got_first} <= 0;
else
if(buf_rptr[31:2] != buf_wptr[31:2]) begin
if(~got_first) begin
buf_rptr <= buf_wptr;
got_first <= 1;
end
else
if(!ram_burstcount && ~ram_waitrequest && ~ready) begin
ram_address <= buf_addr[31:3] + buf_rptr[31:3];
ud <= buf_rptr[2];
ram_burstcount <= 1;
ram_read <= 1;
buf_rptr <= buf_rptr + 4;
end
end
if(ready & ce_48k) begin
{pcm_r,pcm_l} <= readdata;
ready <= 0;
end
end
reg ce_48k;
always @(posedge ram_clk) begin
reg [15:0] acc = 0;
ce_48k <= 0;
acc <= acc + 16'd48;
if(acc >= 50000) begin
acc <= acc - 16'd50000;
ce_48k <= 1;
end
end
endmodule

2312
sys/ascal.vhd Normal file
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File diff suppressed because it is too large Load Diff

157
sys/audio_out.v Normal file
View File

@ -0,0 +1,157 @@
module audio_out
#(
parameter CLK_RATE = 50000000
)
(
input reset,
input clk,
//0 - 48KHz, 1 - 96KHz
input sample_rate,
input [15:0] left_in,
input [15:0] right_in,
// I2S
output i2s_bclk,
output i2s_lrclk,
output i2s_data,
// SPDIF
output spdif,
// Sigma-Delta DAC
output dac_l,
output dac_r
);
localparam AUDIO_RATE = 48000;
localparam AUDIO_DW = 16;
localparam CE_RATE = AUDIO_RATE*AUDIO_DW*8;
localparam FILTER_DIV = (CE_RATE/(AUDIO_RATE*32))-1;
wire [31:0] real_ce = sample_rate ? {CE_RATE[30:0],1'b0} : CE_RATE[31:0];
reg mclk_ce;
always @(posedge clk) begin
reg [31:0] cnt;
mclk_ce <= 0;
cnt = cnt + real_ce;
if(cnt >= CLK_RATE) begin
cnt = cnt - CLK_RATE;
mclk_ce <= 1;
end
end
reg i2s_ce;
always @(posedge clk) begin
reg div;
i2s_ce <= 0;
if(mclk_ce) begin
div <= ~div;
i2s_ce <= div;
end
end
reg lpf_ce;
always @(posedge clk) begin
integer div;
lpf_ce <= 0;
if(mclk_ce) begin
div <= div + 1;
if(div == FILTER_DIV) begin
div <= 0;
lpf_ce <= 1;
end
end
end
i2s i2s
(
.reset(reset),
.clk(clk),
.ce(i2s_ce),
.sclk(i2s_bclk),
.lrclk(i2s_lrclk),
.sdata(i2s_data),
.left_chan(al),
.right_chan(ar)
);
spdif toslink
(
.rst_i(reset),
.clk_i(clk),
.bit_out_en_i(mclk_ce),
.sample_i({ar,al}),
.spdif_o(spdif)
);
sigma_delta_dac #(15) sd_l
(
.CLK(clk),
.RESET(reset),
.DACin({~al[15], al[14:0]}),
.DACout(dac_l)
);
sigma_delta_dac #(15) sd_r
(
.CLK(clk),
.RESET(reset),
.DACin({~ar[15], ar[14:0]}),
.DACout(dac_r)
);
wire [15:0] al, ar;
lpf_aud lpf_l
(
.CLK(clk),
.CE(lpf_ce),
.IDATA(left_in),
.ODATA(al)
);
lpf_aud lpf_r
(
.CLK(clk),
.CE(lpf_ce),
.IDATA(right_in),
.ODATA(ar)
);
endmodule
module lpf_aud
(
input CLK,
input CE,
input [15:0] IDATA,
output reg [15:0] ODATA
);
reg [511:0] acc;
reg [20:0] sum;
always @(*) begin
integer i;
sum = 0;
for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
end
always @(posedge CLK) begin
if(CE) begin
acc <= {acc[495:0], IDATA};
ODATA <= sum[20:5];
end
end
endmodule

4
sys/hdmi_config.sv
View File

@ -142,9 +142,9 @@ wire [15:0] init_data[58] =
16'hAA00, // ADI required Write.
16'hAB40, // ADI required Write.
{8'hAF, 6'b0001_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
{8'hAF, 6'b0000_01,~dvi_mode,1'b0}, // [7]=0 HDCP Disabled.
// [6:5] must be b00!
// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
// [4]=0 Current frame is unencrypted
// [3:2] must be b01!
// [1]=1 HDMI Mode.
// [0] must be b0!

395
sys/hdmi_lite.sv
View File

@ -1,395 +0,0 @@
//============================================================================
//
// HDMI Lite output module
// Copyright (C) 2017 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
//============================================================================
module hdmi_lite
(
input reset,
input clk_video,
input ce_pixel,
input video_vs,
input video_de,
input [23:0] video_d,
input clk_hdmi,
input hdmi_hde,
input hdmi_vde,
output reg hdmi_de,
output [23:0] hdmi_d,
input [11:0] screen_w,
input [11:0] screen_h,
input quadbuf,
// 0-3 => scale 1-4
input [1:0] scale_x,
input [1:0] scale_y,
input scale_auto,
input clk_vbuf,
output [27:0] vbuf_address,
input [127:0] vbuf_readdata,
output [127:0] vbuf_writedata,
output [7:0] vbuf_burstcount,
output [15:0] vbuf_byteenable,
input vbuf_waitrequest,
input vbuf_readdatavalid,
output reg vbuf_read,
output reg vbuf_write
);
localparam [7:0] burstsz = 64;
reg [1:0] nbuf = 0;
wire [27:0] read_buf = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0};
wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0};
assign vbuf_address = vbuf_write ? vbuf_waddress : vbuf_raddress;
assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount;
wire [95:0] hf_out;
wire [7:0] hf_usedw;
reg hf_reset = 0;
vbuf_fifo out_fifo
(
.aclr(hf_reset),
.wrclk(clk_vbuf),
.wrreq(vbuf_readdatavalid),
.data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}),
.wrusedw(hf_usedw),
.rdclk(~clk_hdmi),
.rdreq(hf_rdreq),
.q(hf_out)
);
reg [11:0] rd_stride;
wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0];
reg [27:0] vbuf_raddress;
reg [7:0] vbuf_rburstcount;
always @(posedge clk_vbuf) begin
reg [18:0] rdcnt;
reg [7:0] bcnt;
reg vde1, vde2;
reg [1:0] mcnt;
reg [1:0] my;
reg [18:0] fsz;
reg [11:0] strd;
vde1 <= hdmi_vde;
vde2 <= vde1;
if(vbuf_readdatavalid) begin
rdcnt <= rdcnt + 1'd1;
if(bcnt) bcnt <= bcnt - 1'd1;
vbuf_raddress <= vbuf_raddress + 1'd1;
end
if(!bcnt && reading) reading <= 0;
vbuf_read <= 0;
if(~vbuf_waitrequest) begin
if(!hf_reset && rdcnt<fsz && !bcnt && hf_usedw < burstsz && allow_rd) begin
vbuf_read <= 1;
reading <= 1;
bcnt <= rd_burst;
vbuf_rburstcount <= rd_burst;
rd_stride <= rd_stride - rd_burst;
if(!(rd_stride - rd_burst)) rd_stride <= strd;
if(!rdcnt) begin
vbuf_raddress <= read_buf;
mcnt <= my;
end
else if (rd_stride == strd) begin
mcnt <= mcnt - 1'd1;
if(!mcnt) mcnt <= my;
else vbuf_raddress <= vbuf_raddress - strd;
end
end
end
hf_reset <= 0;
if(vde2 & ~vde1) begin
hf_reset <= 1;
rdcnt <= 0;
bcnt <= 0;
rd_stride <= stride;
strd <= stride;
fsz <= framesz;
my <= mult_y;
end
end
reg [11:0] off_x, off_y;
reg [11:0] x, y;
reg [11:0] vh_height;
reg [11:0] vh_width;
reg [1:0] pcnt;
reg [1:0] hload;
wire hf_rdreq = (x>=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt;
wire de_in = hdmi_hde & hdmi_vde;
always @(posedge clk_hdmi) begin
reg [71:0] px_out;
reg [1:0] mx;
reg vde;
vde <= hdmi_vde;
if(vde & ~hdmi_vde) begin
off_x <= (screen_w>v_width) ? (screen_w - v_width)>>1 : 12'd0;
off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0;
vh_height <= v_height;
vh_width <= v_width;
mx <= mult_x;
end
pcnt <= pcnt + 1'd1;
if(pcnt == mx) begin
pcnt <= 0;
hload <= hload + 1'd1;
end
if(~de_in || x<off_x || y<off_y) begin
hload <= 0;
pcnt <= 0;
end
hdmi_de <= de_in;
x <= x + 1'd1;
if(~hdmi_de & de_in) x <= 0;
if(hdmi_de & ~de_in) y <= y + 1'd1;
if(~hdmi_vde) y <= 0;
if(!pcnt) {px_out, hdmi_d} <= {24'd0, px_out};
if(hf_rdreq) {px_out, hdmi_d} <= hf_out;
end
//////////////////////////////////////////////////////////////////////////////
reg reading = 0;
reg writing = 0;
reg op_split = 0;
always @(posedge clk_vbuf) op_split <= ~op_split;
wire allow_rd = ~reading & ~writing & op_split & ~reset;
wire allow_wr = ~reading & ~writing & ~op_split & ~reset;
//////////////////////////////////////////////////////////////////////////////
reg vf_rdreq = 0;
wire [95:0] vf_out;
assign vbuf_writedata = {8'h00, vf_out[95:72], 8'h00, vf_out[71:48], 8'h00, vf_out[47:24], 8'h00, vf_out[23:0]};
vbuf_fifo in_fifo
(
.aclr(video_vs),
.rdclk(clk_vbuf),
.rdreq(vf_rdreq & ~vbuf_waitrequest),
.q(vf_out),
.wrclk(clk_video),
.wrreq(infifo_wr),
.data({video_de ? video_d : 24'd0, pix_acc})
);
assign vbuf_byteenable = '1;
reg [35:0] addrque[3:0] = '{0,0,0,0};
reg [7:0] flush_size;
reg [27:0] flush_addr;
reg flush_req = 0;
reg flush_ack = 0;
reg [27:0] vbuf_waddress;
reg [7:0] vbuf_wburstcount;
always @(posedge clk_vbuf) begin
reg [7:0] ibcnt = 0;
reg reqd = 0;
reqd <= flush_req;
if(~vbuf_waitrequest) begin
vbuf_write <= vf_rdreq;
if(~vf_rdreq && writing) writing <= 0;
if(!vf_rdreq && !vbuf_write && addrque[0] && allow_wr) begin
{vbuf_waddress, vbuf_wburstcount} <= addrque[0];
ibcnt <= addrque[0][7:0];
addrque[0] <= addrque[1];
addrque[1] <= addrque[2];
addrque[2] <= addrque[3];
addrque[3] <= 0;
vf_rdreq <= 1;
writing <= 1;
end
else if(flush_ack != reqd) begin
if(!addrque[0]) addrque[0] <= {flush_addr, flush_size};
else if(!addrque[1]) addrque[1] <= {flush_addr, flush_size};
else if(!addrque[2]) addrque[2] <= {flush_addr, flush_size};
else if(!addrque[3]) addrque[3] <= {flush_addr, flush_size};
flush_ack <= reqd;
end
if(vf_rdreq) begin
if(ibcnt == 1) vf_rdreq <= 0;
ibcnt <= ibcnt - 1'd1;
end
end
end
reg [11:0] stride;
reg [18:0] framesz;
reg [11:0] v_height;
reg [11:0] v_width;
reg [1:0] mult_x;
reg [1:0] mult_y;
reg [71:0] pix_acc;
wire pix_wr = ce_pixel && video_de;
reg [27:0] cur_addr;
reg [11:0] video_x;
reg [11:0] video_y;
wire infifo_tail = ~video_de && video_x[1:0];
wire infifo_wr = (pix_wr && &video_x[1:0]) || infifo_tail;
wire [1:0] tm_y = (video_y > (screen_h/2)) ? 2'b00 : (video_y > (screen_h/3)) ? 2'b01 : (video_y > (screen_h/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_x = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11;
wire [1:0] tm_xy = (tm_x < tm_y) ? tm_x : tm_y;
wire [1:0] tmf_y = scale_auto ? tm_xy : scale_y;
wire [1:0] tmf_x = scale_auto ? tm_xy : scale_x;
wire [11:0] t_height = video_y + (tmf_y[0] ? video_y : 12'd0) + (tmf_y[1] ? video_y<<1 : 12'd0);
wire [11:0] t_width = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0);
wire [23:0] t_fsz = l1_stride * t_height;
reg [11:0] l1_width;
reg [11:0] l1_stride;
always @(posedge clk_video) begin
reg [7:0] loaded = 0;
reg [11:0] strd = 0;
reg old_de = 0;
reg old_vs = 0;
old_vs <= video_vs;
if(~old_vs & video_vs) begin
cur_addr<= write_buf;
video_x <= 0;
video_y <= 0;
loaded <= 0;
strd <= 0;
nbuf <= nbuf + 1'd1;
stride <= l1_stride;
framesz <= t_fsz[18:0];
v_height<= t_height;
v_width <= t_width;
mult_x <= tmf_x;
mult_y <= tmf_y;
end
if(pix_wr) begin
case(video_x[1:0])
0: pix_acc <= video_d; // zeroes upper bits too
1: pix_acc[47:24] <= video_d;
2: pix_acc[71:48] <= video_d;
3: loaded <= loaded + 1'd1;
endcase
if(video_x<screen_w) video_x <= video_x + 1'd1;
end
old_de <= video_de;
if((!video_x[1:0] && loaded >= burstsz) || (old_de & ~video_de)) begin
if(loaded + infifo_tail) begin
flush_size <= loaded + infifo_tail;
flush_addr <= cur_addr;
flush_req <= ~flush_req;
loaded <= 0;
strd <= strd + loaded;
end
cur_addr <= cur_addr + loaded + infifo_tail;
if(~video_de) begin
if(video_y<screen_h) video_y <= video_y + 1'd1;
video_x <= 0;
strd <= 0;
// measure width by first line (same as VIP)
if(!video_y) begin
l1_width <= video_x;
l1_stride <= strd + loaded + infifo_tail;
end
end
end
end
endmodule
module vbuf_fifo
(
input aclr,
input rdclk,
input rdreq,
output [95:0] q,
input wrclk,
input wrreq,
input [95:0] data,
output [7:0] wrusedw
);
dcfifo dcfifo_component
(
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (q),
.wrusedw (wrusedw),
.eccstatus (),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ()
);
defparam
dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 96,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule

158
sys/hps_io.v
View File

@ -1,10 +1,10 @@
//
// hps_io.v
//
// mist_io-like module for the Terasic DE10 board
// mist_io-like module for MiSTer
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig (port to DE10-nano)
// Copyright (c) 2017,2018 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
@ -40,13 +40,26 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
output reg [15:0] joystick_0,
output reg [15:0] joystick_1,
output reg [15:0] joystick_2,
output reg [15:0] joystick_3,
output reg [15:0] joystick_4,
output reg [15:0] joystick_5,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output reg [15:0] joystick_analog_2,
output reg [15:0] joystick_analog_3,
output reg [15:0] joystick_analog_4,
output reg [15:0] joystick_analog_5,
output [1:0] buttons,
output forced_scandoubler,
output reg [31:0] status,
input [31:0] status_in,
input status_set,
//toggle to force notify of video mode change
input new_vmode,
// SD config
output reg [VD:0] img_mounted, // signaling that new image has been mounted
@ -58,7 +71,7 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
input [VD:0] sd_rd, // only single sd_rd can be active at any given time
input [VD:0] sd_wr, // only single sd_wr can be active at any given time
output reg sd_ack,
// do not use in new projects.
// CID and CSD are fake except CSD image size field.
input sd_conf,
@ -76,6 +89,7 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
output reg ioctl_wr,
output reg [24:0] ioctl_addr, // in WIDE mode address will be incremented by 2
output reg [DW:0] ioctl_dout,
output reg [31:0] ioctl_file_ext,
input ioctl_wait,
// RTC MSM6242B layout
@ -84,6 +98,9 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
// Seconds since 1970-01-01 00:00:00
output reg [32:0] TIMESTAMP,
// UART flags
input [15:0] uart_mode,
// ps2 keyboard emulation
output ps2_kbd_clk_out,
output ps2_kbd_data_out,
@ -102,7 +119,7 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
output reg [10:0] ps2_key = 0,
// [24] - toggles with every event
output reg [24:0] ps2_mouse = 0
);
@ -131,7 +148,7 @@ assign forced_scandoubler = cfg[4];
//cfg[5] - ypbpr handled in sys_top
// command byte read by the io controller
wire [15:0] sd_cmd =
wire [15:0] sd_cmd =
{
2'b00,
(VDNUM>=4) ? sd_wr[3] : 1'b0,
@ -141,7 +158,7 @@ wire [15:0] sd_cmd =
(VDNUM>=4) ? sd_rd[3] : 1'b0,
(VDNUM>=3) ? sd_rd[2] : 1'b0,
(VDNUM>=2) ? sd_rd[1] : 1'b0,
4'h5, sd_conf, 1'b1,
sd_wr[0],
sd_rd[0]
@ -164,7 +181,7 @@ integer hcnt;
always @(posedge clk_vid) begin
integer vcnt;
reg old_vs= 0, old_de = 0;
reg old_vs= 0, old_de = 0, old_vmode = 0;
reg calch = 0;
if(ce_pix) begin
@ -177,7 +194,8 @@ always @(posedge clk_vid) begin
if(old_vs & ~vs) begin
if(hcnt && vcnt) begin
if(vid_hcnt != hcnt || vid_vcnt != vcnt) vid_nres <= vid_nres + 1'd1;
old_vmode <= new_vmode;
if(vid_hcnt != hcnt || vid_vcnt != vcnt || old_vmode != new_vmode) vid_nres <= vid_nres + 1'd1;
vid_hcnt <= hcnt;
vid_vcnt <= vcnt;
end
@ -256,13 +274,22 @@ always@(posedge clk_sys) begin
reg [2:0] b_wr;
reg [2:0] stick_idx;
reg ps2skip = 0;
reg [3:0] stflg = 0;
reg [31:0] status_req;
reg old_status_set = 0;
old_status_set <= status_set;
if(~old_status_set & status_set) begin
stflg <= stflg + 1'd1;
status_req <= status_in;
end
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
{kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
if(~io_enable) begin
if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
if(cmd == 5 && !ps2skip) begin
@ -292,6 +319,8 @@ always@(posedge clk_sys) begin
'h19: sd_ack_conf <= 1;
'h17,
'h18: sd_ack <= 1;
'h29: io_dout <= {4'hA, stflg};
'h2B: io_dout <= 1;
endcase
sd_buff_addr <= 0;
@ -301,11 +330,15 @@ always@(posedge clk_sys) begin
case(cmd)
// buttons and switches
'h01: cfg <= io_din[7:0];
'h01: cfg <= io_din[7:0];
'h02: joystick_0 <= io_din;
'h03: joystick_1 <= io_din;
'h10: joystick_2 <= io_din;
'h11: joystick_3 <= io_din;
'h12: joystick_4 <= io_din;
'h13: joystick_5 <= io_din;
// store incoming ps2 mouse bytes
// store incoming ps2 mouse bytes
'h04: begin
mouse_data <= io_din[7:0];
mouse_we <= 1;
@ -319,7 +352,7 @@ always@(posedge clk_sys) begin
end
end
// store incoming ps2 keyboard bytes
// store incoming ps2 keyboard bytes
'h05: begin
if(&io_din[15:8]) ps2skip <= 1;
if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
@ -327,20 +360,15 @@ always@(posedge clk_sys) begin
kbd_we <= 1;
end
// reading config string
'h14: begin
// returning a byte from string
if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
end
// reading config string, returning a byte from string
'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
// reading sd card status
'h16: begin
case(byte_cnt)
'h16: case(byte_cnt)
1: io_dout <= sd_cmd;
2: io_dout <= sd_lba[15:0];
3: io_dout <= sd_lba[31:16];
endcase
end
// send SD config IO -> FPGA
// flag that download begins
@ -361,14 +389,17 @@ always@(posedge clk_sys) begin
end
// joystick analog
'h1a: begin
// first byte is joystick index
if(byte_cnt == 1) stick_idx <= io_din[2:0];
if(byte_cnt == 2) begin
if(stick_idx == 0) joystick_analog_0 <= io_din;
if(stick_idx == 1) joystick_analog_1 <= io_din;
end
end
'h1a: case(byte_cnt)
1: stick_idx <= io_din[2:0]; // first byte is joystick index
2: case(stick_idx)
0: joystick_analog_0 <= io_din;
1: joystick_analog_1 <= io_din;
2: joystick_analog_2 <= io_din;
3: joystick_analog_3 <= io_din;
4: joystick_analog_4 <= io_din;
5: joystick_analog_5 <= io_din;
endcase
endcase
// notify image selection
'h1c: begin
@ -387,41 +418,46 @@ always@(posedge clk_sys) begin
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
// reading ps2 keyboard/mouse control
'h21: begin
if(byte_cnt == 1) begin
'h21: if(byte_cnt == 1) begin
io_dout <= kbd_data_host;
kbd_rd <= 1;
end
else
if(byte_cnt == 2) begin
io_dout <= mouse_data_host;
mouse_rd <= 1;
end
end
//RTC
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//Video res.
'h23: begin
case(byte_cnt)
1: io_dout <= vid_nres;
2: io_dout <= vid_hcnt[15:0];
3: io_dout <= vid_hcnt[31:16];
4: io_dout <= vid_vcnt[15:0];
5: io_dout <= vid_vcnt[31:16];
6: io_dout <= vid_htime[15:0];
7: io_dout <= vid_htime[31:16];
8: io_dout <= vid_vtime[15:0];
9: io_dout <= vid_vtime[31:16];
10: io_dout <= vid_pix[15:0];
11: io_dout <= vid_pix[31:16];
12: io_dout <= vid_vtime_hdmi[15:0];
13: io_dout <= vid_vtime_hdmi[31:16];
endcase
end
'h23: case(byte_cnt)
1: io_dout <= vid_nres;
2: io_dout <= vid_hcnt[15:0];
3: io_dout <= vid_hcnt[31:16];
4: io_dout <= vid_vcnt[15:0];
5: io_dout <= vid_vcnt[31:16];
6: io_dout <= vid_htime[15:0];
7: io_dout <= vid_htime[31:16];
8: io_dout <= vid_vtime[15:0];
9: io_dout <= vid_vtime[31:16];
10: io_dout <= vid_pix[15:0];
11: io_dout <= vid_pix[31:16];
12: io_dout <= vid_vtime_hdmi[15:0];
13: io_dout <= vid_vtime_hdmi[31:16];
endcase
//RTC
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//UART flags
'h28: io_dout <= uart_mode;
//status set
'h29: case(byte_cnt)
1: io_dout <= status_req[15:0];
2: io_dout <= status_req[31:16];
endcase
endcase
end
end
@ -455,7 +491,7 @@ ps2_device keyboard
.ps2_clk(clk_ps2),
.ps2_clk_out(ps2_kbd_clk_out),
.ps2_dat_out(ps2_kbd_data_out),
.ps2_clk_in(ps2_kbd_clk_in || !PS2WE),
.ps2_dat_in(ps2_kbd_data_in || !PS2WE),
@ -492,9 +528,11 @@ ps2_device mouse
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
localparam UIO_FILE_INFO = 8'h56;
always@(posedge clk_sys) begin
reg [15:0] cmd;
reg [2:0] cnt;
reg has_cmd;
reg [24:0] addr;
reg wr;
@ -509,9 +547,19 @@ always@(posedge clk_sys) begin
if(!has_cmd) begin
cmd <= io_din;
has_cmd <= 1;
cnt <= 0;
end else begin
case(cmd)
UIO_FILE_INFO:
if(~cnt[1]) begin
case(cnt)
0: ioctl_file_ext[31:16] <= io_din;
1: ioctl_file_ext[15:00] <= io_din;
endcase
cnt <= cnt + 1'd1;
end
UIO_FILE_INDEX:
begin
ioctl_index <= io_din[7:0];
@ -521,7 +569,7 @@ always@(posedge clk_sys) begin
begin
if(io_din[7:0]) begin
addr <= 0;
ioctl_download <= 1;
ioctl_download <= 1;
end else begin
ioctl_addr <= addr;
ioctl_download <= 0;
@ -560,7 +608,7 @@ module ps2_device #(parameter PS2_FIFO_BITS=5)
input ps2_clk_in,
input ps2_dat_in,
output [8:0] rdata,
input rd
);
@ -615,7 +663,7 @@ always@(posedge clk_sys) begin
rx_state <= rx_state + 1'b1;
rx_cnt <= 0;
end
2: begin
if(rx_cnt <= 7) data <= {d1, data[7:1]};
else rx_state <= rx_state + 1'b1;
@ -626,7 +674,7 @@ always@(posedge clk_sys) begin
rx_state <= rx_state + 1'b1;
ps2_dat_out <= 0;
end
4: begin
ps2_dat_out <= 1;
has_data <= 1;
@ -661,7 +709,7 @@ always@(posedge clk_sys) begin
if((tx_state >= 1)&&(tx_state < 9)) begin
ps2_dat_out <= tx_byte[0]; // data bits
tx_byte[6:0] <= tx_byte[7:1]; // shift down
if(tx_byte[0])
if(tx_byte[0])
parity <= !parity;
end

183
sys/hq2x.sv
View File

@ -1,7 +1,7 @@
//
//
// Copyright (c) 2012-2013 Ludvig Strigeus
// Copyright (c) 2017 Sorgelig
// Copyright (c) 2017,2018 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
@ -12,36 +12,24 @@
`timescale 1 ps / 1 ps
// synopsys translate_on
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <= 1024 ? 9 : \
N <= 2048 ?10 : 11 )
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input [AWIDTH+1:0] read_x,
output [DWIDTH:0] outpixel
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input hblank,
output [DWIDTH:0] outpixel
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
localparam AWIDTH = $clog2(LENGTH)-1;
localparam DWIDTH = HALF_DEPTH ? 11 : 23;
localparam DWIDTH1 = DWIDTH+1;
wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
@ -62,30 +50,29 @@ wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
reg [23:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] i;
reg [7:0] y;
reg [1:0] cyc;
wire curbuf = y[0];
reg curbuf;
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
DiffCheck diffcheck0(Curr1, (cyc == 0) ? Prev0 : (cyc == 1) ? Curr0 : (cyc == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (cyc == 0) ? Prev1 : (cyc == 1) ? Next0 : (cyc == 2) ? Curr2 : Next2, diff1);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [23:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
wire [23:0] blend_result;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
wire [23:0] blend_result_pre;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result_pre);
reg Curr2_addr1;
reg [AWIDTH:0] Curr2_addr2;
wire [23:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
wire [DWIDTH:0] Curr2tmp;
wire [DWIDTH:0] Curr20tmp;
wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
wire [DWIDTH:0] Curr21tmp;
wire [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
@ -109,9 +96,11 @@ hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(Curr2_addr2),
.rdbuf(Curr2_addr1),
.q(Curr2tmp),
.rdaddr(offs),
.rdbuf0(prevbuf),
.rdbuf1(curbuf),
.q0(Curr20tmp),
.q1(Curr21tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
@ -119,27 +108,31 @@ hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
.wren(wrin_en)
);
reg [1:0] wrout_addr1;
reg [AWIDTH+1:0] wrout_addr2;
reg wrout_en;
reg [DWIDTH:0] wrdata;
reg [AWIDTH+1:0] read_x;
reg [AWIDTH+1:0] wrout_addr;
reg wrout_en;
reg [DWIDTH1*4-1:0] wrdata, wrdata_pre;
wire [DWIDTH1*4-1:0] outpixel_x4;
reg [DWIDTH1*2-1:0] outpixel_x2;
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out
(
.clk(clk),
.clock(clk),
.rdaddr(read_x),
.rdbuf(read_y),
.q(outpixel),
.rdaddress({read_x[AWIDTH+1:1],read_y[1]}),
.q(outpixel_x4),
.wraddr(wrout_addr2),
.wrbuf(wrout_addr1),
.data(wrdata),
.wraddress(wrout_addr),
.wren(wrout_en)
);
wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
reg [AWIDTH:0] offs;
always @(posedge clk) begin
reg [AWIDTH:0] offs;
reg old_reset_line;
reg old_reset_frame;
@ -149,36 +142,33 @@ always @(posedge clk) begin
if(ce_x4) begin
pattern <= new_pattern;
if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
if(~&offs) begin
if (i == 0) begin
Curr2_addr1 <= prevbuf;
Curr2_addr2 <= offs;
end
if (i == 1) begin
Prev2 <= Curr2;
Curr2_addr1 <= curbuf;
Curr2_addr2 <= offs;
end
if (i == 2) begin
if (cyc == 1) begin
Prev2 <= Curr20;
Curr2 <= Curr21;
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
if (i == 3) begin
case({cyc[1],^cyc})
0: wrdata[DWIDTH:0] <= blend_result;
1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
2: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
3: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
endcase
if(cyc==3) begin
offs <= offs + 1'd1;
wrout_addr <= {offs, curbuf};
wrout_en <= 1;
end
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
else wrdata <= blend_result;
wrout_addr1 <= {curbuf, i[1]};
wrout_addr2 <= {offs, i[1]^i[0]};
wrout_en <= 1;
end
if(i==3) begin
if(cyc==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
@ -190,18 +180,22 @@ always @(posedge clk) begin
{B, F, H, D} <= {F, H, D, B};
end
i <= i + 1'b1;
cyc <= cyc + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
i <= 0;
y <= y + 1'd1;
cyc <= 0;
curbuf <= ~curbuf;
prevbuf <= curbuf;
{Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0;
if(old_reset_frame & ~reset_frame) begin
y <= 0;
curbuf <= 0;
prevbuf <= 0;
end
end
if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
if(hblank) read_x <= 0;
old_reset_line <= reset_line;
end
@ -216,8 +210,8 @@ module hq2x_in #(parameter LENGTH, parameter DWIDTH)
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf,
output[DWIDTH:0] q,
input rdbuf0, rdbuf1,
output[DWIDTH:0] q0,q1,
input [AWIDTH:0] wraddr,
input wrbuf,
@ -225,40 +219,15 @@ module hq2x_in #(parameter LENGTH, parameter DWIDTH)
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
wire [DWIDTH:0] out[2];
assign q = out[rdbuf];
localparam AWIDTH = $clog2(LENGTH)-1;
wire [DWIDTH:0] out[2];
assign q0 = out[rdbuf0];
assign q1 = out[rdbuf1];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input [1:0] rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input [1:0] wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
wire [DWIDTH:0] out[4];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,

190
sys/i2s.v
View File

@ -1,136 +1,54 @@
module i2s
#(
parameter CLK_RATE = 50000000,
parameter AUDIO_DW = 16,
parameter AUDIO_RATE = 96000
)
(
input reset,
input clk_sys,
input half_rate,
output reg sclk,
output reg lrclk,
output reg sdata,
input [AUDIO_DW-1:0] left_chan,
input [AUDIO_DW-1:0] right_chan
);
localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
localparam ERROR_BASE = 10000;
localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
reg lpf_ce;
wire [AUDIO_DW-1:0] al, ar;
lpf_i2s lpf_l
(
.CLK(clk_sys),
.CE(lpf_ce),
.IDATA(left_chan),
.ODATA(al)
);
lpf_i2s lpf_r
(
.CLK(clk_sys),
.CE(lpf_ce),
.IDATA(right_chan),
.ODATA(ar)
);
always @(posedge clk_sys) begin
reg [31:0] count_q;
reg [31:0] error_q;
reg [7:0] bit_cnt;
reg skip = 0;
reg [AUDIO_DW-1:0] left;
reg [AUDIO_DW-1:0] right;
reg msclk;
reg ce;
lpf_ce <= 0;
if (reset) begin
count_q <= 0;
error_q <= 0;
ce <= 0;
bit_cnt <= 1;
lrclk <= 1;
sclk <= 1;
msclk <= 1;
end
else
begin
if(count_q == WHOLE_CYCLES-1) begin
if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
error_q <= error_q + ERRORS_PER_BIT[31:0];
count_q <= 0;
end else begin
error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
count_q <= count_q + 1;
end
end else if(count_q == WHOLE_CYCLES) begin
count_q <= 0;
end else begin
count_q <= count_q + 1;
end
sclk <= msclk;
if(!count_q) begin
ce <= ~ce;
if(~half_rate || ce) begin
msclk <= ~msclk;
if(msclk) begin
skip <= ~skip;
if(skip) lpf_ce <= 1;
if(bit_cnt >= AUDIO_DW) begin
bit_cnt <= 1;
lrclk <= ~lrclk;
if(lrclk) begin
left <= al;
right <= ar;
end
end
else begin
bit_cnt <= bit_cnt + 1'd1;
end
sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
end
end
end
end
end
endmodule
module lpf_i2s
(
input CLK,
input CE,
input [15:0] IDATA,
output reg [15:0] ODATA
);
reg [511:0] acc;
reg [20:0] sum;
always @(*) begin
integer i;
sum = 0;
for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
end
always @(posedge CLK) begin
if(CE) begin
acc <= {acc[495:0], IDATA};
ODATA <= sum[20:5];
end
end
endmodule
module i2s
#(
parameter AUDIO_DW = 16
)
(
input reset,
input clk,
input ce,
output reg sclk,
output reg lrclk,
output reg sdata,
input [AUDIO_DW-1:0] left_chan,
input [AUDIO_DW-1:0] right_chan
);
always @(posedge clk) begin
reg [7:0] bit_cnt;
reg msclk;
reg [AUDIO_DW-1:0] left;
reg [AUDIO_DW-1:0] right;
if (reset) begin
bit_cnt <= 1;
lrclk <= 1;
sclk <= 1;
msclk <= 1;
end
else begin
sclk <= msclk;
if(ce) begin
msclk <= ~msclk;
if(msclk) begin
if(bit_cnt >= AUDIO_DW) begin
bit_cnt <= 1;
lrclk <= ~lrclk;
if(lrclk) begin
left <= left_chan;
right <= right_chan;
end
end
else begin
bit_cnt <= bit_cnt + 1'd1;
end
sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
end
end
end
end
endmodule

60
sys/ip/avalon_combiner.v
View File

@ -1,60 +0,0 @@
// avalon_combiner.v
`timescale 1 ps / 1 ps
module avalon_combiner
(
input wire clk, // clock.clk
input wire rst, // reset.reset
output wire [6:0] mixer_address, // ctl_mixer.address
output wire [3:0] mixer_byteenable, // .byteenable
output wire mixer_write, // .write
output wire [31:0] mixer_writedata, // .writedata
input wire mixer_waitrequest, // .waitrequest
output wire [6:0] scaler_address, // ctl_scaler.address
output wire [3:0] scaler_byteenable, // .byteenable
input wire scaler_waitrequest, // .waitrequest
output wire scaler_write, // .write
output wire [31:0] scaler_writedata, // .writedata
output wire [7:0] video_address, // ctl_video.address
output wire [3:0] video_byteenable, // .byteenable
input wire video_waitrequest, // .waitrequest
output wire video_write, // .write
output wire [31:0] video_writedata, // .writedata
output wire clock, // control.clock
output wire reset, // .reset
input wire [8:0] address, // .address
input wire write, // .write
input wire [31:0] writedata, // .writedata
output wire waitrequest // .waitrequest
);
assign clock = clk;
assign reset = rst;
assign mixer_address = address[6:0];
assign scaler_address = address[6:0];
assign video_address = address[7:0];
assign mixer_byteenable = 4'b1111;
assign scaler_byteenable = 4'b1111;
assign video_byteenable = 4'b1111;
wire en_scaler = (address[8:7] == 0);
wire en_mixer = (address[8:7] == 1);
wire en_video = address[8];
assign mixer_write = en_mixer & write;
assign scaler_write = en_scaler & write;
assign video_write = en_video & write;
assign mixer_writedata = writedata;
assign scaler_writedata = writedata;
assign video_writedata = writedata;
assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest);
endmodule

204
sys/ip/avalon_combiner_hw.tcl
View File

@ -1,204 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Wed Dec 13 01:40:49 CST 2017
# DO NOT MODIFY
#
# avalon_combiner "avalon_combiner" v17.0
# sorgelig 2017.12.13.01:40:49
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module avalon_combiner
#
set_module_property DESCRIPTION ""
set_module_property NAME avalon_combiner
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR sorgelig
set_module_property DISPLAY_NAME avalon_combiner
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_combiner
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file avalon_combiner.v VERILOG PATH avalon_combiner.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset rst reset Input 1
#
# connection point ctl_mixer
#
add_interface ctl_mixer avalon start
set_interface_property ctl_mixer addressUnits WORDS
set_interface_property ctl_mixer associatedClock clock
set_interface_property ctl_mixer associatedReset reset
set_interface_property ctl_mixer bitsPerSymbol 8
set_interface_property ctl_mixer burstOnBurstBoundariesOnly false
set_interface_property ctl_mixer burstcountUnits WORDS
set_interface_property ctl_mixer doStreamReads false
set_interface_property ctl_mixer doStreamWrites false
set_interface_property ctl_mixer holdTime 0
set_interface_property ctl_mixer linewrapBursts false
set_interface_property ctl_mixer maximumPendingReadTransactions 0
set_interface_property ctl_mixer maximumPendingWriteTransactions 0
set_interface_property ctl_mixer readLatency 0
set_interface_property ctl_mixer readWaitTime 1
set_interface_property ctl_mixer setupTime 0
set_interface_property ctl_mixer timingUnits Cycles
set_interface_property ctl_mixer writeWaitTime 0
set_interface_property ctl_mixer ENABLED true
set_interface_property ctl_mixer EXPORT_OF ""
set_interface_property ctl_mixer PORT_NAME_MAP ""
set_interface_property ctl_mixer CMSIS_SVD_VARIABLES ""
set_interface_property ctl_mixer SVD_ADDRESS_GROUP ""
add_interface_port ctl_mixer mixer_address address Output 7
add_interface_port ctl_mixer mixer_byteenable byteenable Output 4
add_interface_port ctl_mixer mixer_write write Output 1
add_interface_port ctl_mixer mixer_writedata writedata Output 32
add_interface_port ctl_mixer mixer_waitrequest waitrequest Input 1
#
# connection point ctl_scaler
#
add_interface ctl_scaler avalon start
set_interface_property ctl_scaler addressUnits WORDS
set_interface_property ctl_scaler associatedClock clock
set_interface_property ctl_scaler associatedReset reset
set_interface_property ctl_scaler bitsPerSymbol 8
set_interface_property ctl_scaler burstOnBurstBoundariesOnly false
set_interface_property ctl_scaler burstcountUnits WORDS
set_interface_property ctl_scaler doStreamReads false
set_interface_property ctl_scaler doStreamWrites false
set_interface_property ctl_scaler holdTime 0
set_interface_property ctl_scaler linewrapBursts false
set_interface_property ctl_scaler maximumPendingReadTransactions 0
set_interface_property ctl_scaler maximumPendingWriteTransactions 0
set_interface_property ctl_scaler readLatency 0
set_interface_property ctl_scaler readWaitTime 1
set_interface_property ctl_scaler setupTime 0
set_interface_property ctl_scaler timingUnits Cycles
set_interface_property ctl_scaler writeWaitTime 0
set_interface_property ctl_scaler ENABLED true
set_interface_property ctl_scaler EXPORT_OF ""
set_interface_property ctl_scaler PORT_NAME_MAP ""
set_interface_property ctl_scaler CMSIS_SVD_VARIABLES ""
set_interface_property ctl_scaler SVD_ADDRESS_GROUP ""
add_interface_port ctl_scaler scaler_address address Output 7
add_interface_port ctl_scaler scaler_byteenable byteenable Output 4
add_interface_port ctl_scaler scaler_waitrequest waitrequest Input 1
add_interface_port ctl_scaler scaler_write write Output 1
add_interface_port ctl_scaler scaler_writedata writedata Output 32
#
# connection point ctl_video
#
add_interface ctl_video avalon start
set_interface_property ctl_video addressUnits WORDS
set_interface_property ctl_video associatedClock clock
set_interface_property ctl_video associatedReset reset
set_interface_property ctl_video bitsPerSymbol 8
set_interface_property ctl_video burstOnBurstBoundariesOnly false
set_interface_property ctl_video burstcountUnits WORDS
set_interface_property ctl_video doStreamReads false
set_interface_property ctl_video doStreamWrites false
set_interface_property ctl_video holdTime 0
set_interface_property ctl_video linewrapBursts false
set_interface_property ctl_video maximumPendingReadTransactions 0
set_interface_property ctl_video maximumPendingWriteTransactions 0
set_interface_property ctl_video readLatency 0
set_interface_property ctl_video readWaitTime 1
set_interface_property ctl_video setupTime 0
set_interface_property ctl_video timingUnits Cycles
set_interface_property ctl_video writeWaitTime 0
set_interface_property ctl_video ENABLED true
set_interface_property ctl_video EXPORT_OF ""
set_interface_property ctl_video PORT_NAME_MAP ""
set_interface_property ctl_video CMSIS_SVD_VARIABLES ""
set_interface_property ctl_video SVD_ADDRESS_GROUP ""
add_interface_port ctl_video video_address address Output 8
add_interface_port ctl_video video_byteenable byteenable Output 4
add_interface_port ctl_video video_waitrequest waitrequest Input 1
add_interface_port ctl_video video_write write Output 1
add_interface_port ctl_video video_writedata writedata Output 32
#
# connection point control
#
add_interface control conduit end
set_interface_property control associatedClock clock
set_interface_property control associatedReset reset
set_interface_property control ENABLED true
set_interface_property control EXPORT_OF ""
set_interface_property control PORT_NAME_MAP ""
set_interface_property control CMSIS_SVD_VARIABLES ""
set_interface_property control SVD_ADDRESS_GROUP ""
add_interface_port control address address Input 9
add_interface_port control write write Input 1
add_interface_port control writedata writedata Input 32
add_interface_port control waitrequest waitrequest Output 1
add_interface_port control clock clock Output 1
add_interface_port control reset reset Output 1

3706
sys/ip/de10_hps_hw.tcl
View File

File diff suppressed because it is too large Load Diff

52
sys/ip/in_split.v
View File

@ -1,52 +0,0 @@
// in_split.v
`timescale 1 ps / 1 ps
module in_split (
input wire clk, // input.clk
input wire ce, // .ce
input wire de, // .de
input wire h_sync, // .h_sync
input wire v_sync, // .v_sync
input wire f, // .f
input wire [23:0] data, // .data
output wire vid_clk, // Output.vid_clk
output reg vid_datavalid, // .vid_datavalid
output reg [1:0] vid_de, // .vid_de
output reg [1:0] vid_f, // .vid_f
output reg [1:0] vid_h_sync, // .vid_h_sync
output reg [1:0] vid_v_sync, // .vid_v_sync
output reg [47:0] vid_data, // .vid_data
output wire vid_locked, // .vid_locked
output wire [7:0] vid_color_encoding, // .vid_color_encoding
output wire [7:0] vid_bit_width, // .vid_bit_width
input wire clipping, // .clipping
input wire overflow, // .overflow
input wire sof, // .sof
input wire sof_locked, // .sof_locked
input wire refclk_div, // .refclk_div
input wire padding // .padding
);
assign vid_bit_width = 0;
assign vid_color_encoding = 0;
assign vid_locked = 1;
assign vid_clk = clk;
always @(posedge clk) begin
reg odd = 0;
vid_datavalid <= 0;
if(ce) begin
vid_de[odd] <= de;
vid_f[odd] <= f;
vid_h_sync[odd] <= h_sync;
vid_v_sync[odd] <= v_sync;
if(odd) vid_data[47:24] <= data;
else vid_data[23:0] <= data;
odd <= ~odd;
vid_datavalid <= odd;
end
end
endmodule

104
sys/ip/in_split_hw.tcl
View File

@ -1,104 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Thu Jan 25 18:50:29 CST 2018
# DO NOT MODIFY
#
# in_split "Input Splitter" v17.0
# Sorgelig 2018.01.25.18:50:29
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module in_split
#
set_module_property DESCRIPTION ""
set_module_property NAME in_split
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME "Input Splitter"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL in_split
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file in_split.v VERILOG PATH in_split.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point input
#
add_interface input conduit end
set_interface_property input associatedClock ""
set_interface_property input associatedReset ""
set_interface_property input ENABLED true
set_interface_property input EXPORT_OF ""
set_interface_property input PORT_NAME_MAP ""
set_interface_property input CMSIS_SVD_VARIABLES ""
set_interface_property input SVD_ADDRESS_GROUP ""
add_interface_port input clk clk Input 1
add_interface_port input ce ce Input 1
add_interface_port input de de Input 1
add_interface_port input h_sync h_sync Input 1
add_interface_port input v_sync v_sync Input 1
add_interface_port input f f Input 1
add_interface_port input data data Input 24
#
# connection point Output
#
add_interface Output conduit end
set_interface_property Output associatedClock ""
set_interface_property Output associatedReset ""
set_interface_property Output ENABLED true
set_interface_property Output EXPORT_OF ""
set_interface_property Output PORT_NAME_MAP ""
set_interface_property Output CMSIS_SVD_VARIABLES ""
set_interface_property Output SVD_ADDRESS_GROUP ""
add_interface_port Output vid_clk vid_clk Output 1
add_interface_port Output vid_datavalid vid_datavalid Output 1
add_interface_port Output vid_de vid_de Output 2
add_interface_port Output vid_f vid_f Output 2
add_interface_port Output vid_h_sync vid_h_sync Output 2
add_interface_port Output vid_v_sync vid_v_sync Output 2
add_interface_port Output vid_data vid_data Output 48
add_interface_port Output vid_locked vid_locked Output 1
add_interface_port Output vid_color_encoding vid_color_encoding Output 8
add_interface_port Output vid_bit_width vid_bit_width Output 8
add_interface_port Output clipping clipping Input 1
add_interface_port Output overflow overflow Input 1
add_interface_port Output sof sof Input 1
add_interface_port Output sof_locked sof_locked Input 1
add_interface_port Output refclk_div refclk_div Input 1
add_interface_port Output padding padding Input 1

44
sys/ip/out_mix.v
View File

@ -1,44 +0,0 @@
// out_mix.v
`timescale 1 ps / 1 ps
module out_mix (
input wire clk, // Output.clk
output reg de, // .de
output reg h_sync, // .h_sync
output reg v_sync, // .v_sync
output reg [23:0] data, // .data
output reg vid_clk, // input.vid_clk
input wire [1:0] vid_datavalid, // .vid_datavalid
input wire [1:0] vid_h_sync, // .vid_h_sync
input wire [1:0] vid_v_sync, // .vid_v_sync
input wire [47:0] vid_data, // .vid_data
input wire underflow, // .underflow
input wire vid_mode_change, // .vid_mode_change
input wire [1:0] vid_std, // .vid_std
input wire [1:0] vid_f, // .vid_f
input wire [1:0] vid_h, // .vid_h
input wire [1:0] vid_v // .vid_v
);
reg r_de;
reg r_h_sync;
reg r_v_sync;
reg [23:0] r_data;
always @(posedge clk) begin
vid_clk <= ~vid_clk;
if(~vid_clk) begin
{r_de,de} <= vid_datavalid;
{r_h_sync, h_sync} <= vid_h_sync;
{r_v_sync, v_sync} <= vid_v_sync;
{r_data, data} <= vid_data;
end else begin
de <= r_de;
h_sync <= r_h_sync;
v_sync <= r_v_sync;
data <= r_data;
end
end
endmodule

97
sys/ip/out_mix_hw.tcl
View File

@ -1,97 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Thu Jan 25 06:51:26 CST 2018
# DO NOT MODIFY
#
# out_mix "Output Mixer" v1.0
# Sorgelig 2018.01.25.06:51:26
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module out_mix
#
set_module_property DESCRIPTION ""
set_module_property NAME out_mix
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME "Output Mixer"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL out_mix
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file out_mix.v VERILOG PATH out_mix.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point Output
#
add_interface Output conduit end
set_interface_property Output associatedClock ""
set_interface_property Output associatedReset ""
set_interface_property Output ENABLED true
set_interface_property Output EXPORT_OF ""
set_interface_property Output PORT_NAME_MAP ""
set_interface_property Output CMSIS_SVD_VARIABLES ""
set_interface_property Output SVD_ADDRESS_GROUP ""
add_interface_port Output clk clk Input 1
add_interface_port Output de de Output 1
add_interface_port Output h_sync h_sync Output 1
add_interface_port Output v_sync v_sync Output 1
add_interface_port Output data data Output 24
#
# connection point input
#
add_interface input conduit end
set_interface_property input associatedClock ""
set_interface_property input associatedReset ""
set_interface_property input ENABLED true
set_interface_property input EXPORT_OF ""
set_interface_property input PORT_NAME_MAP ""
set_interface_property input CMSIS_SVD_VARIABLES ""
set_interface_property input SVD_ADDRESS_GROUP ""
add_interface_port input vid_clk vid_clk Output 1
add_interface_port input vid_datavalid vid_datavalid Input 2
add_interface_port input vid_h_sync vid_h_sync Input 2
add_interface_port input vid_v_sync vid_v_sync Input 2
add_interface_port input vid_data vid_data Input 48
add_interface_port input underflow underflow Input 1
add_interface_port input vid_mode_change vid_mode_change Input 1
add_interface_port input vid_std vid_std Input 2
add_interface_port input vid_f vid_f Input 2
add_interface_port input vid_h vid_h Input 2
add_interface_port input vid_v vid_v Input 2

50
sys/ip/reset_source.v
View File

@ -1,50 +0,0 @@
// reset_source.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module reset_source
(
input wire clk, // clock.clk
input wire reset_hps, // reset_hps.reset
output wire reset_sys, // reset_sys.reset
output wire reset_cold, // reset_cold.reset
input wire cold_req, // reset_ctl.cold_req
output wire reset, // .reset
input wire reset_req, // .reset_req
input wire reset_vip, // .reset_vip
input wire warm_req, // .warm_req
output wire reset_warm // reset_warm.reset
);
assign reset_cold = cold_req;
assign reset_warm = warm_req;
wire reset_m = sys_reset | reset_hps | reset_req;
assign reset = reset_m;
assign reset_sys = reset_m | reset_vip;
reg sys_reset = 1;
always @(posedge clk) begin
integer timeout = 0;
reg reset_lock = 0;
reset_lock <= reset_lock | cold_req;
if(timeout < 2000000) begin
sys_reset <= 1;
timeout <= timeout + 1;
reset_lock <= 0;
end
else begin
sys_reset <= reset_lock;
end
end
endmodule

152
sys/ip/reset_source_hw.tcl
View File

@ -1,152 +0,0 @@
# TCL File Generated by Component Editor 17.0
# Tue Feb 20 07:55:55 CST 2018
# DO NOT MODIFY
#
# reset_source "reset_source" v17.0
# Sorgelig 2018.02.20.07:55:55
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module reset_source
#
set_module_property DESCRIPTION ""
set_module_property NAME reset_source
set_module_property VERSION 17.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR Sorgelig
set_module_property DISPLAY_NAME reset_source
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL reset_source
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file reset_source.v VERILOG PATH reset_source.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset_hps
#
add_interface reset_hps reset end
set_interface_property reset_hps associatedClock ""
set_interface_property reset_hps synchronousEdges NONE
set_interface_property reset_hps ENABLED true
set_interface_property reset_hps EXPORT_OF ""
set_interface_property reset_hps PORT_NAME_MAP ""
set_interface_property reset_hps CMSIS_SVD_VARIABLES ""
set_interface_property reset_hps SVD_ADDRESS_GROUP ""
add_interface_port reset_hps reset_hps reset Input 1
#
# connection point reset_sys
#
add_interface reset_sys reset start
set_interface_property reset_sys associatedClock ""
set_interface_property reset_sys associatedDirectReset ""
set_interface_property reset_sys associatedResetSinks ""
set_interface_property reset_sys synchronousEdges NONE
set_interface_property reset_sys ENABLED true
set_interface_property reset_sys EXPORT_OF ""
set_interface_property reset_sys PORT_NAME_MAP ""
set_interface_property reset_sys CMSIS_SVD_VARIABLES ""
set_interface_property reset_sys SVD_ADDRESS_GROUP ""
add_interface_port reset_sys reset_sys reset Output 1
#
# connection point reset_ctl
#
add_interface reset_ctl conduit end
set_interface_property reset_ctl associatedClock ""
set_interface_property reset_ctl associatedReset ""
set_interface_property reset_ctl ENABLED true
set_interface_property reset_ctl EXPORT_OF ""
set_interface_property reset_ctl PORT_NAME_MAP ""
set_interface_property reset_ctl CMSIS_SVD_VARIABLES ""
set_interface_property reset_ctl SVD_ADDRESS_GROUP ""
add_interface_port reset_ctl cold_req cold_req Input 1
add_interface_port reset_ctl reset reset Output 1
add_interface_port reset_ctl reset_req reset_req Input 1
add_interface_port reset_ctl warm_req warm_req Input 1
add_interface_port reset_ctl reset_vip reset_vip Input 1
#
# connection point reset_warm
#
add_interface reset_warm reset start
set_interface_property reset_warm associatedClock ""
set_interface_property reset_warm associatedDirectReset ""
set_interface_property reset_warm associatedResetSinks ""
set_interface_property reset_warm synchronousEdges NONE
set_interface_property reset_warm ENABLED true
set_interface_property reset_warm EXPORT_OF ""
set_interface_property reset_warm PORT_NAME_MAP ""
set_interface_property reset_warm CMSIS_SVD_VARIABLES ""
set_interface_property reset_warm SVD_ADDRESS_GROUP ""
add_interface_port reset_warm reset_warm reset Output 1
#
# connection point reset_cold
#
add_interface reset_cold reset start
set_interface_property reset_cold associatedClock ""
set_interface_property reset_cold associatedDirectReset ""
set_interface_property reset_cold associatedResetSinks ""
set_interface_property reset_cold synchronousEdges NONE
set_interface_property reset_cold ENABLED true
set_interface_property reset_cold EXPORT_OF ""
set_interface_property reset_cold PORT_NAME_MAP ""
set_interface_property reset_cold CMSIS_SVD_VARIABLES ""
set_interface_property reset_cold SVD_ADDRESS_GROUP ""
add_interface_port reset_cold reset_cold reset Output 1

100
sys/lpf48k.sv
View File

@ -1,100 +0,0 @@
// low pass filter
// Revision 1.00
//
// Copyright (c) 2008 Takayuki Hara.
// All rights reserved.
//
// Redistribution and use of this source code or any derivative works, are
// permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// 3. Redistributions may not be sold, nor may they be used in a commercial
// product or activity without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// LPF (cut off 48kHz at 3.58MHz)
module lpf48k #(parameter MSB = 15)
(
input RESET,
input CLK,
input CE,
input ENABLE,
input [MSB:0] IDATA,
output [MSB:0] ODATA
);
wire [7:0] LPF_TAP_DATA[0:71] =
'{
8'h51, 8'h07, 8'h07, 8'h08, 8'h08, 8'h08, 8'h09, 8'h09,
8'h09, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h0B, 8'h0B, 8'h0B,
8'h0B, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0D, 8'h0D, 8'h0D,
8'h0D, 8'h0D, 8'h0D, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E,
8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E,
8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0D, 8'h0D, 8'h0D,
8'h0D, 8'h0D, 8'h0D, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0B,
8'h0B, 8'h0B, 8'h0B, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h09,
8'h09, 8'h09, 8'h08, 8'h08, 8'h08, 8'h07, 8'h07, 8'h51
};
reg [7:0] FF_ADDR = 0;
reg [MSB+10:0] FF_INTEG = 0;
wire [MSB+8:0] W_DATA;
wire W_ADDR_END;
assign W_ADDR_END = ((FF_ADDR == 71));
reg [MSB:0] OUT;
assign ODATA = ENABLE ? OUT : IDATA;
always @(posedge RESET or posedge CLK) begin
if (RESET) FF_ADDR <= 0;
else
begin
if (CE) begin
if (W_ADDR_END) FF_ADDR <= 0;
else FF_ADDR <= FF_ADDR + 1'd1;
end
end
end
assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA;
always @(posedge RESET or posedge CLK) begin
if (RESET) FF_INTEG <= 0;
else
begin
if (CE) begin
if (W_ADDR_END) FF_INTEG <= 0;
else FF_INTEG <= FF_INTEG + W_DATA;
end
end
end
always @(posedge RESET or posedge CLK) begin
if (RESET) OUT <= 0;
else
begin
if (CE && W_ADDR_END) OUT <= FF_INTEG[MSB + 10:10];
end
end
endmodule

130
sys/osd.v
View File

@ -13,7 +13,8 @@ module osd
input [23:0] din,
output [23:0] dout,
input de_in,
output reg de_out
output reg de_out,
output reg osd_status
);
parameter OSD_COLOR = 3'd4;
@ -23,21 +24,24 @@ parameter OSD_Y_OFFSET = 12'd0;
localparam OSD_WIDTH = 12'd256;
localparam OSD_HEIGHT = 12'd64;
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096];
reg osd_enable;
reg [7:0] osd_buffer[4096];
reg highres = 0;
reg info = 0;
reg [8:0] infoh;
reg [8:0] infow;
reg [11:0] infox;
reg [21:0] infoy;
reg [21:0] hrheight;
always@(posedge clk_sys) begin
reg [11:0] bcnt;
reg [7:0] cmd;
reg has_cmd;
reg old_strobe;
reg highres = 0;
hrheight <= info ? infoh : (OSD_HEIGHT<<highres);
old_strobe <= io_strobe;
@ -53,9 +57,9 @@ always@(posedge clk_sys) begin
cmd <= io_din[7:0];
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(io_din[7:4] == 4) begin
if(!io_din[0]) highres <= 0;
info <= io_din[2];
bcnt <= 0;
if(!io_din[0]) {osd_status,highres} <= 0;
else {osd_status,info} <= {~io_din[2],io_din[2]};
bcnt <= 0;
end
// command 0x20: OSDCMDWRITE
if(io_din[7:4] == 2) begin
@ -101,98 +105,90 @@ always @(negedge clk_video) begin
end
end
reg [23:0] h_cnt;
reg [21:0] v_cnt;
reg [21:0] dsp_width;
reg [21:0] dsp_height;
reg [7:0] osd_byte;
reg [21:0] osd_vcnt;
reg [21:0] fheight;
reg [21:0] finfoy;
wire [21:0] hrheight = info ? infoh : (OSD_HEIGHT<<highres);
reg [2:0] osd_de;
reg osd_pixel;
always @(posedge clk_video) begin
reg deD;
reg [1:0] osd_div;
reg [1:0] multiscan;
reg deD;
reg [1:0] osd_div;
reg [1:0] multiscan;
reg [7:0] osd_byte;
reg [23:0] h_cnt;
reg [21:0] v_cnt;
reg [21:0] dsp_width;
reg [21:0] osd_vcnt;
reg [21:0] h_osd_start;
reg [21:0] v_osd_start;
reg [21:0] osd_hcnt;
reg osd_de1,osd_de2;
reg [1:0] osd_en;
if(ce_pix) begin
deD <= de_in;
if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1;
if (h_cnt == h_osd_start) begin
osd_de[0] <= osd_en[1] && hrheight && (osd_vcnt < hrheight);
osd_hcnt <= 0;
end
if (osd_hcnt+1 == (info ? infow : OSD_WIDTH)) osd_de[0] <= 0;
// falling edge of de
if(!de_in && deD) dsp_width <= h_cnt[21:0];
// rising edge of de
if(de_in && !deD) begin
h_cnt <= 0;
v_cnt <= v_cnt + 1'd1;
h_osd_start <= info ? infox : (((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET - 2'd2);
if(h_cnt > {dsp_width, 2'b00}) begin
v_cnt <= 0;
dsp_height <= v_cnt;
if(osd_enable) begin
if(v_cnt<320) begin
multiscan <= 0;
fheight <= hrheight;
finfoy <= infoy;
end
else if(v_cnt<640) begin
multiscan <= 1;
fheight <= hrheight << 1;
finfoy <= infoy << 1;
end
else if(v_cnt<960) begin
multiscan <= 2;
fheight <= hrheight + (hrheight<<1);
finfoy <= infoy + (infoy << 1);
end
else begin
multiscan <= 3;
fheight <= hrheight << 2;
finfoy <= infoy << 2;
end
osd_en <= (osd_en << 1) | osd_enable;
if(~osd_enable) osd_en <= 0;
if(v_cnt<320) begin
multiscan <= 0;
v_osd_start <= info ? infoy : (((v_cnt-hrheight)>>1) + OSD_Y_OFFSET);
end
else if(v_cnt<640) begin
multiscan <= 1;
v_osd_start <= info ? (infoy<<1) : (((v_cnt-(hrheight<<1))>>1) + OSD_Y_OFFSET);
end
else if(v_cnt<960) begin
multiscan <= 2;
v_osd_start <= info ? (infoy + (infoy << 1)) : (((v_cnt-(hrheight + (hrheight<<1)))>>1) + OSD_Y_OFFSET);
end
else begin
fheight <= 0;
multiscan <= 3;
v_osd_start <= info ? (infoy<<2) : (((v_cnt-(hrheight<<2))>>1) + OSD_Y_OFFSET);
end
end
h_cnt <= 0;
osd_div <= osd_div + 1'd1;
if(osd_div == multiscan) begin
osd_div <= 0;
osd_vcnt <= osd_vcnt + 1'd1;
if(~&osd_vcnt) osd_vcnt <= osd_vcnt + 1'd1;
end
if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0;
end
osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
osd_pixel <= osd_byte[osd_vcnt[2:0]];
osd_de[2:1] <= osd_de[1:0];
end
end
// area in which OSD is being displayed
wire [21:0] h_osd_start = info ? infox : ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET;
wire [21:0] h_osd_end = info ? (h_osd_start + infow) : (h_osd_start + OSD_WIDTH);
wire [21:0] v_osd_start = info ? finfoy : ((dsp_height- fheight)>>1) + OSD_Y_OFFSET;
wire [21:0] v_osd_end = v_osd_start + fheight;
wire [21:0] osd_hcnt = h_cnt[21:0] - h_osd_start + 1'd1;
wire osd_de = osd_enable && fheight &&
(h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
wire osd_pixel = osd_byte[osd_vcnt[2:0]];
reg [23:0] rdout;
assign dout = rdout;
always @(posedge clk_video) begin
rdout <= !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
rdout <= ~osd_de[2] ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
de_out <= de_in;
end

120
sys/pattern_vg.v
View File

@ -1,120 +0,0 @@
module pattern_vg
#(
parameter B=8, // number of bits per channel
X_BITS=13,
Y_BITS=13,
FRACTIONAL_BITS = 12
)
(
input reset, clk_in,
input wire [X_BITS-1:0] x,
input wire [Y_BITS-1:0] y,
input wire vn_in, hn_in, dn_in,
input wire [B-1:0] r_in, g_in, b_in,
output reg vn_out, hn_out, den_out,
output reg [B-1:0] r_out, g_out, b_out,
input wire [X_BITS-1:0] total_active_pix,
input wire [Y_BITS-1:0] total_active_lines,
input wire [7:0] pattern,
input wire [B+FRACTIONAL_BITS-1:0] ramp_step
);
reg [B+FRACTIONAL_BITS-1:0] ramp_values; // 12-bit fractional end for ramp values
//wire bar_0 = y<90;
wire bar_1 = y>=90 & y<180;
wire bar_2 = y>=180 & y<270;
wire bar_3 = y>=270 & y<360;
wire bar_4 = y>=360 & y<450;
wire bar_5 = y>=450 & y<540;
wire bar_6 = y>=540 & y<630;
wire bar_7 = y>=630 & y<720;
wire red_enable = bar_1 | bar_3 | bar_5 | bar_7;
wire green_enable = bar_2 | bar_3 | bar_6 | bar_7;
wire blue_enable = bar_4 | bar_5 | bar_6 | bar_7;
always @(posedge clk_in)
begin
vn_out <= vn_in;
hn_out <= hn_in;
den_out <= dn_in;
if (reset)
ramp_values <= 0;
else if (pattern == 8'b0) // no pattern
begin
r_out <= r_in;
g_out <= g_in;
b_out <= b_in;
end
else if (pattern == 8'b1) // border
begin
if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1)))
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else // Double-border (OzOnE)...
if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20)))
begin
r_out <= 8'hD0;
g_out <= 8'hB0;
b_out <= 8'hB0;
end
else
begin
r_out <= r_in;
g_out <= g_in;
b_out <= b_in;
end
end
else if (pattern == 8'd2) // moireX
begin
if ((dn_in) && x[0] == 1'b1)
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else
begin
r_out <= 8'b0;
g_out <= 8'b0;
b_out <= 8'b0;
end
end
else if (pattern == 8'd3) // moireY
begin
if ((dn_in) && y[0] == 1'b1)
begin
r_out <= 8'hFF;
g_out <= 8'hFF;
b_out <= 8'hFF;
end
else
begin
r_out <= 8'b0;
g_out <= 8'b0;
b_out <= 8'b0;
end
end
else if (pattern == 8'd4) // Simple RAMP
begin
r_out <= (red_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
g_out <= (green_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
b_out <= (blue_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
if ((x == total_active_pix - 1) && (dn_in))
ramp_values <= 0;
else if ((x == 0) && (dn_in))
ramp_values <= ramp_step;
else if (dn_in)
ramp_values <= ramp_values + ramp_step;
end
end
endmodule

4
sys/pll_hdmi/pll_hdmi_0002_q13.qip Normal file
View File

@ -0,0 +1,4 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

360
sys/pll_hdmi_adj.vhd Normal file
View File

@ -0,0 +1,360 @@
--------------------------------------------------------------------------------
-- HDMI PLL Adjust
--------------------------------------------------------------------------------
-- Changes the HDMI PLL frequency according to the scaler suggestions.
--------------------------------------------
-- LLTUNE :
-- 0 : Input Syncline
-- 1 :
-- 2 : Input Interlaced mode
-- 3 : Input Interlaced field
-- 4 : Output Syncline
-- 5 :
-- 6 : Input clock
-- 7 : Output clock
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY pll_hdmi_adj IS
PORT (
-- Scaler
llena : IN std_logic; -- 0=Disabled 1=Enabled
lltune : IN unsigned(15 DOWNTO 0); -- Outputs from scaler
locked : OUT std_logic;
-- Signals from reconfig commands
i_waitrequest : OUT std_logic;
i_write : IN std_logic;
i_address : IN unsigned(5 DOWNTO 0);
i_writedata : IN unsigned(31 DOWNTO 0);
-- Outputs to PLL_HDMI_CFG
o_waitrequest : IN std_logic;
o_write : OUT std_logic;
o_address : OUT unsigned(5 DOWNTO 0);
o_writedata : OUT unsigned(31 DOWNTO 0);
------------------------------------
clk : IN std_logic;
reset_na : IN std_logic
);
BEGIN
END ENTITY pll_hdmi_adj;
--##############################################################################
ARCHITECTURE rtl OF pll_hdmi_adj IS
SIGNAL pwrite : std_logic;
SIGNAL paddress : unsigned(5 DOWNTO 0);
SIGNAL pdata : unsigned(31 DOWNTO 0);
TYPE enum_state IS (sIDLE,sW1,sW2,sW3,sW4,sW5,sW6);
SIGNAL state : enum_state;
SIGNAL tune_freq,tune_phase : unsigned(5 DOWNTO 0);
SIGNAL lltune_sync,lltune_sync2,lltune_sync3 : unsigned(15 DOWNTO 0);
SIGNAL mfrac,mfrac_mem,mfrac_ref,diff : unsigned(40 DOWNTO 0);
SIGNAL mul : unsigned(15 DOWNTO 0);
SIGNAL sign,sign_pre : std_logic;
SIGNAL up,modo,phm,dir : std_logic;
SIGNAL cpt : natural RANGE 0 TO 3;
SIGNAL col : natural RANGE 0 TO 15;
SIGNAL icpt,ocpt,ssh : natural RANGE 0 TO 2**24-1;
SIGNAL isync,isync2,itog,ipulse : std_logic;
SIGNAL osync,osync2,otog,opulse : std_logic;
SIGNAL sync,pulse,los,lop : std_logic;
SIGNAL osize,isize,offset,osizep : signed(23 DOWNTO 0);
SIGNAL logcpt : natural RANGE 0 TO 31;
SIGNAL udiff : integer RANGE -2**23 TO 2**23-1 :=0;
BEGIN
----------------------------------------------------------------------------
-- Sample image sizes
Sampler:PROCESS(clk,reset_na) IS
BEGIN
IF reset_na='0' THEN
--pragma synthesis_off
otog<='0';
itog<='0';
isync<='0';
isync2<='0';
osync<='0';
osync2<='0';
--pragma synthesis_on
ELSIF rising_edge(clk) THEN
-- Clock domain crossing
isync<=lltune(0); -- <ASYNC>
isync2<=isync;
osync<=lltune(4); -- <ASYNC>
osync2<=osync;
itog<=itog XOR (isync AND NOT isync2);
otog<=otog XOR (osync AND NOT osync2);
--ipulse<=isync AND NOT isync2 AND itog;
--opulse<=osync AND NOT osync2 AND otog;
-- Measure output image size
IF osync='1' AND osync2='0' AND otog='1' THEN
ocpt<=0;
osizep<=to_signed(ocpt,24);
ELSE
ocpt<=ocpt+1;
END IF;
-- Measure input image size
IF isync='1' AND isync2='0' AND itog='1' THEN
icpt<=0;
--isize<=to_signed(icpt,24);
osize<=osizep;
offset<=to_signed(ocpt,24);
udiff<=integer(to_integer(osizep)) - integer(icpt);
sync<='1';
ELSE
icpt<=icpt+1;
sync<='0';
END IF;
--------------------------------------------
pulse<='0';
IF sync='1' THEN
logcpt<=0;
ssh<=to_integer(osize);
los<='0';
lop<='0';
ELSIF logcpt<24 THEN
-- Frequency difference
IF udiff>0 AND ssh<udiff AND los='0' THEN
tune_freq<='0' & to_unsigned(logcpt,5);
los<='1';
ELSIF udiff<=0 AND ssh<-udiff AND los='0' THEN
tune_freq<='1' & to_unsigned(logcpt,5);
los<='1';
END IF;
-- Phase difference
IF offset<osize/2 AND ssh<offset AND lop='0' THEN
tune_phase<='0' & to_unsigned(logcpt,5);
lop<='1';
ELSIF offset>=osize/2 AND ssh<(osize-offset) AND lop='0' THEN
tune_phase<='1' & to_unsigned(logcpt,5);
lop<='1';
END IF;
ssh<=ssh/2;
logcpt<=logcpt+1;
ELSIF logcpt=24 THEN
pulse<='1';
ssh<=ssh/2;
logcpt<=logcpt+1;
END IF;
END IF;
END PROCESS Sampler;
----------------------------------------------------------------------------
-- 000010 : Start reg "Write either 0 or 1 to start fractional PLL reconf.
-- 000100 : M counter
-- 000111 : M counter Fractional Value K
Comb:PROCESS(i_write,i_address,
i_writedata,pwrite,paddress,pdata) IS
BEGIN
IF i_write='1' THEN
o_write <=i_write;
o_address <=i_address;
o_writedata <=i_writedata;
ELSE
o_write <=pwrite;
o_address <=paddress;
o_writedata<=pdata;
END IF;
END PROCESS Comb;
i_waitrequest<=o_waitrequest WHEN state=sIDLE ELSE '0';
----------------------------------------------------------------------------
Schmurtz:PROCESS(clk,reset_na) IS
VARIABLE off_v,ofp_v : natural RANGE 0 TO 63;
VARIABLE diff_v : unsigned(40 DOWNTO 0);
VARIABLE mulco : unsigned(15 DOWNTO 0);
VARIABLE up_v,sign_v : std_logic;
BEGIN
IF reset_na='0' THEN
modo<='0';
state<=sIDLE;
ELSIF rising_edge(clk) THEN
------------------------------------------------------
-- Snoop accesses to PLL reconfiguration
IF i_address="000100" AND i_write='1' THEN
mfrac (40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
('0' & i_writedata(7 DOWNTO 0));
mfrac_ref(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
('0' & i_writedata(7 DOWNTO 0));
mfrac_mem(40 DOWNTO 32)<=('0' & i_writedata(15 DOWNTO 8)) +
('0' & i_writedata(7 DOWNTO 0));
mul<=i_writedata(15 DOWNTO 0);
modo<='1';
END IF;
IF i_address="000111" AND i_write='1' THEN
mfrac (31 DOWNTO 0)<=i_writedata;
mfrac_ref(31 DOWNTO 0)<=i_writedata;
mfrac_mem(31 DOWNTO 0)<=i_writedata;
modo<='1';
END IF;
------------------------------------------------------
-- Tuning
off_v:=to_integer('0' & tune_freq(4 DOWNTO 0));
ofp_v:=to_integer('0' & tune_phase(4 DOWNTO 0));
--IF off_v<8 THEN off_v:=8; END IF;
--IF ofp_v<7 THEN ofp_v:=7; END IF;
IF off_v<4 THEN off_v:=4; END IF;
IF ofp_v<4 THEN ofp_v:=4; END IF;
IF off_v>=18 AND ofp_v>=18 THEN
locked<=llena;
ELSE
locked<='0';
END IF;
up_v:='0';
IF pulse='1' THEN
cpt<=(cpt+1) MOD 4;
IF llena='0' THEN
-- Recover original freq when disabling low lag mode
cpt<=0;
col<=0;
IF modo='1' THEN
mfrac<=mfrac_mem;
mfrac_ref<=mfrac_mem;
up<='1';
modo<='0';
END IF;
ELSIF phm='0' AND cpt=0 THEN
-- Frequency adjust
sign_v:=tune_freq(5);
IF col<10 THEN col<=col+1; END IF;
IF off_v>=16 AND col>=10 THEN
phm<='1';
col<=0;
ELSE
off_v:=off_v+1;
IF off_v>17 THEN
off_v:=off_v + 3;
END IF;
up_v:='1';
up<='1';
END IF;
ELSIF cpt=0 THEN
-- Phase adjust
sign_v:=NOT tune_phase(5);
col<=col+1;
IF col>=10 THEN
phm<='0';
up_v:='1';
off_v:=31;
col<=0;
ELSE
off_v:=ofp_v + 1;
IF ofp_v>7 THEN
off_v:=off_v + 1;
END IF;
IF ofp_v>14 THEN
off_v:=off_v + 2;
END IF;
IF ofp_v>17 THEN
off_v:=off_v + 3;
END IF;
up_v:='1';
END IF;
up<='1';
END IF;
END IF;
diff_v:=shift_right(mfrac_ref,off_v);
IF sign_v='0' THEN
diff_v:=mfrac_ref + diff_v;
ELSE
diff_v:=mfrac_ref - diff_v;
END IF;
IF up_v='1' THEN
mfrac<=diff_v;
END IF;
IF up_v='1' AND phm='0' THEN
mfrac_ref<=diff_v;
END IF;
------------------------------------------------------
-- Update PLL registers
mulco:=mfrac(40 DOWNTO 33) & (mfrac(40 DOWNTO 33) + ('0' & mfrac(32)));
CASE state IS
WHEN sIDLE =>
pwrite<='0';
IF up='1' THEN
up<='0';
IF mulco/=mul THEN
state<=sW1;
ELSE
state<=sW3;
END IF;
END IF;
WHEN sW1 => -- Change M multiplier
mul<=mulco;
pdata<=x"0000" & mulco;
paddress<="000100";
pwrite<='1';
state<=sW2;
WHEN sW2 =>
IF pwrite='1' AND o_waitrequest='0' THEN
state<=sW3;
pwrite<='0';
END IF;
WHEN sW3 => -- Change M fractional value
pdata<=mfrac(31 DOWNTO 0);
paddress<="000111";
pwrite<='1';
state<=sW4;
WHEN sW4 =>
IF pwrite='1' AND o_waitrequest='0' THEN
state<=sW5;
pwrite<='0';
END IF;
WHEN sW5 =>
pdata<=x"0000_0001";
paddress<="000010";
pwrite<='1';
state<=sW6;
WHEN sW6 =>
IF pwrite='1' AND o_waitrequest='0' THEN
pwrite<='0';
state<=sIDLE;
END IF;
END CASE;
END IF;
END PROCESS Schmurtz;
----------------------------------------------------------------------------
END ARCHITECTURE rtl;

13
sys/pll_hdmi_q13.qip Normal file
View File

@ -0,0 +1,13 @@
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"]
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"

181
sys/scandoubler.v
View File

@ -2,7 +2,7 @@
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
// Copyright (c) 2017-2019 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
@ -31,8 +31,8 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
// shifter video interface
input hs_in,
input vs_in,
input hb_in,
input vb_in,
input hb_in,
input vb_in,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
@ -42,8 +42,8 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
// output interface
output reg hs_out,
output vs_out,
output hb_out,
output vb_out,
output hb_out,
output vb_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
@ -52,48 +52,58 @@ module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
assign vs_out = vs_in;
assign ce_pix_out = ce_x4;
assign vs_out = vso[3];
assign ce_pix_out = hq2x ? ce_x4 : ce_x2;
//Compensate picture shift after HQ2x
assign vb_out = vbo[2];
assign hb_out = &hbo[5:4];
assign vb_out = vbo[3];
assign hb_out = hbo[6];
reg [7:0] pix_len = 0;
reg [7:0] pix_cnt = 0;
wire [7:0] pl = pix_len + 1'b1;
wire [7:0] pc = pix_cnt + 1'b1;
reg ce_x1, ce_x4;
reg req_line_reset;
reg ce_x4, ce_x2, ce_x1;
always @(negedge clk_sys) begin
reg old_ce;
reg old_ce, valid, hs;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
reg [7:0] pixsz, pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
if(~&pix_len) pix_len <= pl;
if(~&pix_cnt) pix_cnt <= pc;
ce_x4 <= 0;
ce_x2 <= 0;
ce_x1 <= 0;
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
ce_x4 <= 1;
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple of 4.
if((pc == pixsz4) || (pc == pixsz2) || (pc == (pixsz2+pixsz4))) ce_x4 <= 1;
if( pc == pixsz2) ce_x2 <= 1;
old_ce <= ce_pix;
if(~old_ce & ce_pix) begin
if(valid & ~hb_in & ~vb_in) begin
pixsz <= pl;
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
end
pix_len <= 0;
valid <= 1;
end
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
ce_x4 <= 1;
pix_len <= 0;
req_line_reset <= 0;
if(hb_in | vb_in) valid <= 0;
if(hb_in) req_line_reset <= 1;
hs <= hs_out;
if((~hs & hs_out) || (pc >= pixsz)) begin
ce_x2 <= 1;
ce_x4 <= 1;
ce_x1 <= 1;
pix_cnt <= 0;
end
end
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
@ -101,86 +111,85 @@ Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
.inputpixel({b_d,g_d,r_d}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_frame(vb_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.read_x(sd_h),
.hblank(hbo[0]&hbo[8]),
.outpixel({b_out,g_out,r_out})
);
reg [10:0] sd_h;
reg [1:0] sd_line;
reg [2:0] vbo;
reg [5:0] hbo;
reg [DWIDTH:0] r_d;
reg [DWIDTH:0] g_d;
reg [DWIDTH:0] b_d;
reg [1:0] sd_line;
reg [3:0] vbo;
reg [3:0] vso;
reg [8:0] hbo;
reg req_line_reset;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg [11:0] hde_start, hde_end;
reg [31:0] hcnt;
reg [30:0] sd_hcnt;
reg [30:0] hs_start, hs_end;
reg [30:0] hde_start, hde_end;
reg hs, hs2, vs, hb;
reg hs, hb;
if(ce_x4) begin
hbo[8:1] <= hbo[7:0];
end
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
if(sd_hcnt == hde_start) begin
sd_hcnt <= 0;
vbo[3:1] <= vbo[2:0];
end
if(sd_hcnt == hs_end) begin
sd_line <= sd_line + 1'd1;
if(&vbo[3:2]) sd_line <= 1;
vso[3:1] <= vso[2:0];
end
if(sd_hcnt == hde_start)hbo[0] <= 0;
if(sd_hcnt == hde_end) hbo[0] <= 1;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_end) hs_out <= 0;
if(sd_hcnt == hs_start) hs_out <= 1;
hs <= hs_in;
hb <= hb_in;
if(ce_x1) begin
hs <= hs_in;
hb <= hb_in;
req_line_reset <= hb_in;
r_d <= r_in;
g_d <= g_in;
b_d <= b_in;
if(hb && !hb_in) begin
hde_start <= {hcnt,1'b0};
vbo <= {vbo[1:0], vb_in};
end
if(!hb && hb_in) hde_end <= {hcnt,1'b0};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_max <= {hcnt,1'b1};
hcnt <= 0;
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
hbo[5:1] <= hbo[4:0];
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
if(~&hbo) sd_h <= sd_h + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
//prepare to read in advance
if(sd_hcnt == (hde_start-2)) begin
sd_h <= 0;
sd_line <= sd_line + 1'd1;
end
if(sd_hcnt == hde_start) hbo[0] <= 0;
if(sd_hcnt == hde_end) hbo[0] <= 1;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
hcnt <= hcnt + 1'd1;
if(hb && !hb_in) begin
hde_start <= hcnt[31:1];
hbo[0] <= 0;
hcnt <= 0;
sd_hcnt <= 0;
vbo <= {vbo[2:0],vb_in};
end
if(!hb && hb_in) hde_end <= hcnt[31:1];
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_end <= hcnt[31:1];
vso[0] <= vs_in;
end
// save position of rising edge
if(!hs && hs_in) hs_start <= hcnt[31:1];
end
endmodule

52
sys/scanlines.v Normal file
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@ -0,0 +1,52 @@
module scanlines #(parameter v2=0)
(
input clk,
input [1:0] scanlines,
input [23:0] din,
output reg [23:0] dout,
input hs,vs
);
reg [1:0] scanline;
always @(posedge clk) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) begin
if(v2) begin
scanline <= scanline + 1'd1;
if (scanline == scanlines) scanline <= 0;
end
else scanline <= scanline ^ scanlines;
end
if(old_vs && ~vs) scanline <= 0;
end
wire [7:0] r,g,b;
assign {r,g,b} = din;
always @(*) begin
case(scanline)
1: // reduce 25% = 1/2 + 1/4
dout = {{1'b0, r[7:1]} + {2'b00, r[7:2]},
{1'b0, g[7:1]} + {2'b00, g[7:2]},
{1'b0, b[7:1]} + {2'b00, b[7:2]}};
2: // reduce 50% = 1/2
dout = {{1'b0, r[7:1]},
{1'b0, g[7:1]},
{1'b0, b[7:1]}};
3: // reduce 75% = 1/4
dout = {{2'b00, r[7:2]},
{2'b00, g[7:2]},
{2'b00, b[7:2]}};
default: dout = {r,g,b};
endcase
end
endmodule

538
sys/sd_card.v Normal file
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@ -0,0 +1,538 @@
//
// sd_card.v
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
// Copyright (c) 2015-2018 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the Lesser GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// http://elm-chan.org/docs/mmc/mmc_e.html
//
/////////////////////////////////////////////////////////////////////////
//
// Made module syncrhronous. Total code refactoring. (Sorgelig)
// clk_spi must be at least 4 x sck for proper work.
module sd_card
(
input clk_sys,
input reset,
input sdhc,
output [31:0] sd_lba,
output reg sd_rd,
output reg sd_wr,
input sd_ack,
input sd_ack_conf,
input [8:0] sd_buff_addr,
input [7:0] sd_buff_dout,
output [7:0] sd_buff_din,
input sd_buff_wr,
// SPI interface
input clk_spi,
input ss,
input sck,
input mosi,
output reg miso
);
assign sd_lba = sdhc ? lba : {9'd0, lba[31:9]};
wire[31:0] OCR = { 1'b1, sdhc, 30'd0 }; // bit30 = 1 -> high capaciry card (sdhc) // bit31 = 0 -> card power up finished
wire [7:0] READ_DATA_TOKEN = 8'hfe;
wire [7:0] WRITE_DATA_RESPONSE = 8'h05;
// number of bytes to wait after a command before sending the reply
localparam NCR=3;
localparam RD_STATE_IDLE = 0;
localparam RD_STATE_WAIT_IO = 1;
localparam RD_STATE_SEND_TOKEN = 2;
localparam RD_STATE_SEND_DATA = 3;
localparam RD_STATE_WAIT_M = 4;
localparam WR_STATE_IDLE = 0;
localparam WR_STATE_EXP_DTOKEN = 1;
localparam WR_STATE_RECV_DATA = 2;
localparam WR_STATE_RECV_CRC0 = 3;
localparam WR_STATE_RECV_CRC1 = 4;
localparam WR_STATE_SEND_DRESP = 5;
localparam WR_STATE_BUSY = 6;
sdbuf buffer
(
.clock_a(clk_sys),
.address_a(sd_buff_addr),
.data_a(sd_buff_dout),
.wren_a(sd_ack & sd_buff_wr),
.q_a(sd_buff_din),
.clock_b(clk_spi),
.address_b(buffer_ptr),
.data_b(buffer_din),
.wren_b(buffer_wr),
.q_b(buffer_dout)
);
sdbuf conf
(
.clock_a(clk_sys),
.address_a(sd_buff_addr),
.data_a(sd_buff_dout),
.wren_a(sd_ack_conf & sd_buff_wr),
.clock_b(clk_spi),
.address_b(buffer_ptr),
.q_b(config_dout)
);
reg [31:0] lba, new_lba;
reg [8:0] buffer_ptr;
reg [7:0] buffer_din;
wire [7:0] buffer_dout;
wire [7:0] config_dout;
reg buffer_wr;
always @(posedge clk_spi) begin
reg [2:0] read_state;
reg [2:0] write_state;
reg [6:0] sbuf;
reg cmd55;
reg [7:0] cmd;
reg [2:0] bit_cnt;
reg [3:0] byte_cnt;
reg [7:0] reply;
reg [7:0] reply0, reply1, reply2, reply3;
reg [3:0] reply_len;
reg tx_finish;
reg rx_finish;
reg old_sck;
reg synced;
reg [5:0] ack;
reg io_ack;
reg [4:0] idle_cnt = 0;
reg [2:0] wait_m_cnt;
if(buffer_wr & ~&buffer_ptr) buffer_ptr <= buffer_ptr + 1'd1;
buffer_wr <= 0;
ack <= {ack[4:0], sd_ack};
if(ack[5:4] == 2'b10) io_ack <= 1;
if(ack[5:4] == 2'b01) {sd_rd,sd_wr} <= 0;
old_sck <= sck;
if(~ss) idle_cnt <= 31;
else if(~old_sck && sck && idle_cnt) idle_cnt <= idle_cnt - 1'd1;
if(reset || !idle_cnt) begin
bit_cnt <= 0;
byte_cnt <= 15;
synced <= 0;
miso <= 1;
sbuf <= 7'b1111111;
tx_finish <= 0;
rx_finish <= 0;
read_state <= RD_STATE_IDLE;
write_state <= WR_STATE_IDLE;
end
if(old_sck & ~sck & ~ss) begin
tx_finish <= 0;
miso <= 1; // default: send 1's (busy/wait)
if(byte_cnt == 5+NCR) begin
miso <= reply[~bit_cnt];
if(bit_cnt == 7) begin
// these three commands all have a reply_len of 0 and will thus
// not send more than a single reply byte
// CMD9: SEND_CSD
// CMD10: SEND_CID
if((cmd == 'h49) | (cmd == 'h4a))
read_state <= RD_STATE_SEND_TOKEN; // jump directly to data transmission
// CMD17/CMD18
if((cmd == 'h51) | (cmd == 'h52)) begin
io_ack <= 0;
read_state <= RD_STATE_WAIT_IO; // start waiting for data from io controller
lba <= new_lba;
sd_rd <= 1; // trigger request to io controller
end
end
end
else if((reply_len > 0) && (byte_cnt == 5+NCR+1)) miso <= reply0[~bit_cnt];
else if((reply_len > 1) && (byte_cnt == 5+NCR+2)) miso <= reply1[~bit_cnt];
else if((reply_len > 2) && (byte_cnt == 5+NCR+3)) miso <= reply2[~bit_cnt];
else if((reply_len > 3) && (byte_cnt == 5+NCR+4)) miso <= reply3[~bit_cnt];
else begin
if(byte_cnt > 5+NCR && read_state==RD_STATE_IDLE && write_state==WR_STATE_IDLE) tx_finish <= 1;
end
// ---------- read state machine processing -------------
case(read_state)
RD_STATE_IDLE: ; // do nothing
// waiting for io controller to return data
RD_STATE_WAIT_IO: begin
if(io_ack & (bit_cnt == 7)) read_state <= RD_STATE_SEND_TOKEN;
end
// send data token
RD_STATE_SEND_TOKEN: begin
miso <= READ_DATA_TOKEN[~bit_cnt];
if(bit_cnt == 7) begin
read_state <= RD_STATE_SEND_DATA; // next: send data
buffer_ptr <= 0;
if(cmd == 'h49) buffer_ptr <= 16;
end
end
// send data
RD_STATE_SEND_DATA: begin
miso <= ((cmd == 'h49) | (cmd == 'h4A)) ? config_dout[~bit_cnt] : buffer_dout[~bit_cnt];
if(bit_cnt == 7) begin
// sent 512 sector data bytes?
if((cmd == 'h51) & &buffer_ptr) read_state <= RD_STATE_IDLE;
else if((cmd == 'h52) & &buffer_ptr) begin
read_state <= RD_STATE_WAIT_M;
wait_m_cnt <= 0;
end
// sent 16 cid/csd data bytes?
else if(((cmd == 'h49) | (cmd == 'h4a)) & (&buffer_ptr[3:0])) read_state <= RD_STATE_IDLE;
// not done yet -> trigger read of next data byte
else buffer_ptr <= buffer_ptr + 1'd1;
end
end
RD_STATE_WAIT_M: begin
if(bit_cnt == 7) begin
wait_m_cnt <= wait_m_cnt + 1'd1;
if(&wait_m_cnt) begin
lba <= lba + 1;
io_ack <= 0;
sd_rd <= 1;
read_state <= RD_STATE_WAIT_IO;
end
end
end
endcase
// ------------------ write support ----------------------
// send write data response
if(write_state == WR_STATE_SEND_DRESP) miso <= WRITE_DATA_RESPONSE[~bit_cnt];
// busy after write until the io controller sends ack
if(write_state == WR_STATE_BUSY) miso <= 0;
end
if(~old_sck & sck & ~ss) begin
if(synced) bit_cnt <= bit_cnt + 1'd1;
// assemble byte
if(bit_cnt != 7) begin
sbuf[6:0] <= { sbuf[5:0], mosi };
// resync while waiting for token
if(write_state==WR_STATE_EXP_DTOKEN) begin
if(cmd == 'h58) begin
if({sbuf,mosi} == 8'hfe) begin
write_state <= WR_STATE_RECV_DATA;
buffer_ptr <= 0;
bit_cnt <= 0;
end
end
else begin
if({sbuf,mosi} == 8'hfc) begin
write_state <= WR_STATE_RECV_DATA;
buffer_ptr <= 0;
bit_cnt <= 0;
end
if({sbuf,mosi} == 8'hfd) begin
write_state <= WR_STATE_IDLE;
rx_finish <= 1;
bit_cnt <= 0;
end
end
end
end
else begin
// finished reading one byte
// byte counter runs against 15 byte boundary
if(byte_cnt != 15) byte_cnt <= byte_cnt + 1'd1;
// byte_cnt > 6 -> complete command received
// first byte of valid command is 01xxxxxx
// don't accept new commands once a write or read command has been accepted
if((byte_cnt > 5) & (write_state == WR_STATE_IDLE) & (read_state == RD_STATE_IDLE) && !rx_finish) begin
byte_cnt <= 0;
cmd <= { sbuf, mosi};
// set cmd55 flag if previous command was 55
cmd55 <= (cmd == 'h77);
end
if((byte_cnt > 5) & (read_state == RD_STATE_WAIT_M) && ({sbuf, mosi} == 8'h4c)) begin
byte_cnt <= 0;
rx_finish <= 0;
cmd <= {sbuf, mosi};
read_state <= RD_STATE_IDLE;
end
// parse additional command bytes
if(byte_cnt == 0) new_lba[31:24] <= { sbuf, mosi};
if(byte_cnt == 1) new_lba[23:16] <= { sbuf, mosi};
if(byte_cnt == 2) new_lba[15:8] <= { sbuf, mosi};
if(byte_cnt == 3) new_lba[7:0] <= { sbuf, mosi};
// last byte (crc) received, evaluate
if(byte_cnt == 4) begin
// default:
reply <= 4; // illegal command
reply_len <= 0; // no extra reply bytes
rx_finish <= 1;
case(cmd)
// CMD0: GO_IDLE_STATE
'h40: reply <= 1; // ok, busy
// CMD1: SEND_OP_COND
'h41: reply <= 0; // ok, not busy
// CMD8: SEND_IF_COND (V2 only)
'h48: begin
reply <= 1; // ok, busy
reply0 <= 'h00;
reply1 <= 'h00;
reply2 <= 'h01;
reply3 <= 'hAA;
reply_len <= 4;
end
// CMD9: SEND_CSD
'h49: reply <= 0; // ok
// CMD10: SEND_CID
'h4a: reply <= 0; // ok
// CMD12: STOP_TRANSMISSION
'h4c: reply <= 0; // ok
// CMD16: SET_BLOCKLEN
'h50: begin
// we only support a block size of 512
if(new_lba == 512) reply <= 0; // ok
else reply <= 'h40; // parmeter error
end
// CMD17: READ_SINGLE_BLOCK
'h51: reply <= 0; // ok
// CMD18: READ_MULTIPLE
'h52: reply <= 0; // ok
// CMD24: WRITE_BLOCK
'h58,
// CMD25: WRITE_MULTIPLE
'h59: begin
reply <= 0; // ok
write_state <= WR_STATE_EXP_DTOKEN; // expect data token
rx_finish <=0;
lba <= new_lba;
end
// ACMD41: APP_SEND_OP_COND
'h69: if(cmd55) reply <= 0; // ok, not busy
// CMD55: APP_COND
'h77: reply <= 1; // ok, busy
// CMD58: READ_OCR
'h7a: begin
reply <= 0; // ok
reply0 <= OCR[31:24]; // bit 30 = 1 -> high capacity card
reply1 <= OCR[23:16];
reply2 <= OCR[15:8];
reply3 <= OCR[7:0];
reply_len <= 4;
end
// CMD59: CRC_ON_OFF
'h7b: reply <= 0; // ok
endcase
end
// ---------- handle write -----------
case(write_state)
// do nothing in idle state
WR_STATE_IDLE: ;
// waiting for data token
WR_STATE_EXP_DTOKEN: begin
buffer_ptr <= 0;
if(cmd == 'h58) begin
if({sbuf,mosi} == 8'hfe) write_state <= WR_STATE_RECV_DATA;
end
else begin
if({sbuf,mosi} == 8'hfc) write_state <= WR_STATE_RECV_DATA;
if({sbuf,mosi} == 8'hfd) begin
write_state <= WR_STATE_IDLE;
rx_finish <= 1;
end
end
end
// transfer 512 bytes
WR_STATE_RECV_DATA: begin
// push one byte into local buffer
buffer_wr <= 1;
buffer_din <= {sbuf, mosi};
// all bytes written?
if(&buffer_ptr) write_state <= WR_STATE_RECV_CRC0;
end
// transfer 1st crc byte
WR_STATE_RECV_CRC0:
write_state <= WR_STATE_RECV_CRC1;
// transfer 2nd crc byte
WR_STATE_RECV_CRC1:
write_state <= WR_STATE_SEND_DRESP;
// send data response
WR_STATE_SEND_DRESP: begin
write_state <= WR_STATE_BUSY;
io_ack <= 0;
sd_wr <= 1;
end
// wait for io controller to accept data
WR_STATE_BUSY:
if(io_ack) begin
if(cmd == 'h59) begin
write_state <= WR_STATE_EXP_DTOKEN;
lba <= lba + 1;
end
else begin
write_state <= WR_STATE_IDLE;
rx_finish <= 1;
end
end
endcase
end
// wait for first 0 bit until start counting bits
if(!synced && !mosi) begin
synced <= 1;
bit_cnt <= 1; // byte assembly prepare for next time loop
sbuf <= 7'b1111110; // byte assembly prepare for next time loop
rx_finish<= 0;
end else if (synced && tx_finish && rx_finish ) begin
synced <= 0;
bit_cnt <= 0;
rx_finish<= 0;
end
end
end
endmodule
module sdbuf
(
input clock_a,
input clock_b,
input [8:0] address_a,
input [8:0] address_b,
input [7:0] data_a,
input [7:0] data_b,
input wren_a,
input wren_b,
output [7:0] q_a,
output [7:0] q_b
);
altsyncram altsyncram_component
(
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (q_a),
.q_b (q_b),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1)
);
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule

126
sys/spdif.v
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@ -31,132 +31,6 @@
// altera message_off 10240
module spdif
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter CLK_RATE = 50000000,
parameter AUDIO_RATE = 48000,
// Generated params
parameter WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*128),
parameter ERROR_BASE = 10000,
parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE)
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
input half_rate,
// Output
output spdif_o,
// Audio interface (16-bit x 2 = RL)
input [15:0] audio_r,
input [15:0] audio_l,
output sample_req_o
);
reg lpf_ce;
always @(negedge clk_i) begin
reg [3:0] div;
div <= div + 1'd1;
if(div == 13) div <= 0;
lpf_ce <= !div;
end
wire [15:0] al, ar;
lpf48k #(15) lpf_l
(
.RESET(rst_i),
.CLK(clk_i),
.CE(lpf_ce),
.ENABLE(1),
.IDATA(audio_l),
.ODATA(al)
);
lpf48k #(15) lpf_r
(
.RESET(rst_i),
.CLK(clk_i),
.CE(lpf_ce),
.ENABLE(1),
.IDATA(audio_r),
.ODATA(ar)
);
reg bit_clk_q;
// Clock pulse generator
always @ (posedge rst_i or posedge clk_i) begin
reg [31:0] count_q;
reg [31:0] error_q;
reg ce;
if (rst_i) begin
count_q <= 0;
error_q <= 0;
bit_clk_q <= 1;
ce <= 0;
end
else
begin
if(count_q == WHOLE_CYCLES-1) begin
if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
error_q <= error_q + ERRORS_PER_BIT[31:0];
count_q <= 0;
end else begin
error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
count_q <= count_q + 1;
end
end else if(count_q == WHOLE_CYCLES) begin
count_q <= 0;
end else begin
count_q <= count_q + 1;
end
bit_clk_q <= 0;
if(!count_q) begin
ce <= ~ce;
if(~half_rate || ce) bit_clk_q <= 1;
end
end
end
//-----------------------------------------------------------------
// Core SPDIF
//-----------------------------------------------------------------
wire [31:0] sample_i = {ar, al};
spdif_core
u_core
(
.clk_i(clk_i),
.rst_i(rst_i),
.bit_out_en_i(bit_clk_q),
.spdif_o(spdif_o),
.sample_i(sample_i),
.sample_req_o(sample_req_o)
);
endmodule
module spdif_core
(
input clk_i,
input rst_i,

78
sys/sync_vg.v
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@ -1,78 +0,0 @@
module sync_vg
#(
parameter X_BITS=12, Y_BITS=12
)
(
input wire clk,
input wire reset,
input wire [Y_BITS-1:0] v_total,
input wire [Y_BITS-1:0] v_fp,
input wire [Y_BITS-1:0] v_bp,
input wire [Y_BITS-1:0] v_sync,
input wire [X_BITS-1:0] h_total,
input wire [X_BITS-1:0] h_fp,
input wire [X_BITS-1:0] h_bp,
input wire [X_BITS-1:0] h_sync,
input wire [X_BITS-1:0] hv_offset,
output reg vs_out,
output reg hs_out,
output reg hde_out,
output reg vde_out,
output reg [Y_BITS-1:0] v_count_out,
output reg [X_BITS-1:0] h_count_out,
output reg [X_BITS-1:0] x_out,
output reg [Y_BITS-1:0] y_out
);
reg [X_BITS-1:0] h_count;
reg [Y_BITS-1:0] v_count;
/* horizontal counter */
always @(posedge clk)
if (reset)
h_count <= 0;
else
if (h_count < h_total - 1)
h_count <= h_count + 1'd1;
else
h_count <= 0;
/* vertical counter */
always @(posedge clk)
if (reset)
v_count <= 0;
else
if (h_count == h_total - 1)
begin
if (v_count == v_total - 1)
v_count <= 0;
else
v_count <= v_count + 1'd1;
end
always @(posedge clk)
if (reset)
{ vs_out, hs_out, hde_out, vde_out } <= 0;
else begin
hs_out <= ((h_count < h_sync));
hde_out <= (h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1);
vde_out <= (v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1);
if ((v_count == 0) && (h_count == hv_offset))
vs_out <= 1'b1;
else if ((v_count == v_sync) && (h_count == hv_offset))
vs_out <= 1'b0;
/* H_COUNT_OUT and V_COUNT_OUT */
h_count_out <= h_count;
v_count_out <= v_count;
/* X and Y coords for a backend pattern generator */
x_out <= h_count - (h_sync + h_bp);
y_out <= v_count - (v_sync + v_bp);
end
endmodule

49
sys/sys.qip
View File

@ -1,23 +1,26 @@
set_global_assignment -name VERILOG_FILE sys/sys_top.v
set_global_assignment -name SDC_FILE sys/sys_top.sdc
set_global_assignment -name QIP_FILE sys/pll.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi.qip
set_global_assignment -name QIP_FILE sys/pll_hdmi_cfg.qip
set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_lite.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv
set_global_assignment -name VERILOG_FILE sys/scandoubler.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv
set_global_assignment -name VERILOG_FILE sys/osd.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/vga_out.sv
set_global_assignment -name VERILOG_FILE sys/sync_vg.v
set_global_assignment -name VERILOG_FILE sys/pattern_vg.v
set_global_assignment -name VERILOG_FILE sys/i2c.v
set_global_assignment -name VERILOG_FILE sys/i2s.v
set_global_assignment -name VERILOG_FILE sys/spdif.v
set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv
set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv
set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v
set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv
set_global_assignment -name VERILOG_FILE sys/hps_io.v
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.qip ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart

30
sys/sys_q13.qip Normal file
View File

@ -0,0 +1,30 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sys_top.v ]
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll/pll_0002.v ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll/pll_0002.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi_q13.qip ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_core.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_hdmi_cfg/altera_pll_reconfig_top.v ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) alsa.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2s.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) spdif.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) audio_out.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart

25
sys/sys_top.sdc
View File

@ -3,44 +3,29 @@ create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
create_clock -period 10.0 [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
derive_pll_clocks
# Specify PLL-generated clock(s)
create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-name SDRAM_CLK [get_ports {SDRAM_CLK}]
create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-name HDMI_CLK [get_ports HDMI_TX_CLK]
create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}]
derive_clock_uncertainty
# Set acceptable delays for SDRAM chip (See correspondent chip datasheet)
set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
set_multicycle_path -from [get_clocks {SDRAM_CLK}] \
-to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-setup 2
set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
# Decouple different clock groups (to simplify routing)
set_clock_groups -asynchronous \
-group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \
-group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
-group [get_clocks { *|h2f_user0_clk}] \
-group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_false_path -from {*} -to [get_registers {wcalc[*] hcalc[*]}]
# Put constraints on input ports
set_false_path -from [get_ports {KEY*}] -to *
set_false_path -from [get_ports {BTN_*}] -to *

1934
sys/sys_top.v
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File diff suppressed because it is too large Load Diff

948
sys/sysmem.sv
View File

@ -1,531 +1,429 @@
`timescale 1 ps / 1 ps
module sysmem_lite
(
input ramclk1_clk, // ramclk1.clk
input [28:0] ram1_address, // ram1.address
input [7:0] ram1_burstcount, // .burstcount
output ram1_waitrequest, // .waitrequest
output [63:0] ram1_readdata, // .readdata
output ram1_readdatavalid, // .readdatavalid
input ram1_read, // .read
input [63:0] ram1_writedata, // .writedata
input [7:0] ram1_byteenable, // .byteenable
input ram1_write, // .write
input ramclk2_clk, // ramclk2.clk
input [28:0] ram2_address, // ram2.address
input [7:0] ram2_burstcount, // .burstcount
output ram2_waitrequest, // .waitrequest
output [63:0] ram2_readdata, // .readdata
output ram2_readdatavalid, // .readdatavalid
input ram2_read, // .read
input [63:0] ram2_writedata, // .writedata
input [7:0] ram2_byteenable, // .byteenable
input ram2_write, // .write
output ctl_clock,
input reset_cold_req, // reset.cold_req
output reset_reset, // .reset
input reset_reset_req, // .reset_req
input reset_warm_req, // .warm_req
input vbuf_clk, // vbuf.clk
input [27:0] vbuf_address, // vbuf.address
input [7:0] vbuf_burstcount, // .burstcount
output vbuf_waitrequest, // .waitrequest
output [127:0] vbuf_readdata, // .readdata
output vbuf_readdatavalid, // .readdatavalid
input vbuf_read, // .read
input [127:0] vbuf_writedata, // .writedata
input [15:0] vbuf_byteenable, // .byteenable
input vbuf_write // .write
);
assign ctl_clock = clk_vip_clk;
wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps
wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n
wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n
wire clk_vip_clk;
sysmem_HPS_fpga_interfaces fpga_interfaces (
.f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n
.f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
.h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (vbuf_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (vbuf_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (vbuf_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (vbuf_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (vbuf_readdata), // .readdata
.f2h_sdram0_READDATAVALID (vbuf_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (vbuf_read), // .read
.f2h_sdram0_WRITEDATA (vbuf_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (vbuf_byteenable), // .byteenable
.f2h_sdram0_WRITE (vbuf_write), // .write
.f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk
.f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount
.f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest
.f2h_sdram1_READDATA (ram1_readdata), // .readdata
.f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid
.f2h_sdram1_READ (ram1_read), // .read
.f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata
.f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable
.f2h_sdram1_WRITE (ram1_write), // .write
.f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk
.f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address
.f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount
.f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest
.f2h_sdram2_READDATA (ram2_readdata), // .readdata
.f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid
.f2h_sdram2_READ (ram2_read), // .read
.f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata
.f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable
.f2h_sdram2_WRITE (ram2_write) // .write
);
reset_source reset_source (
.clk (clk_vip_clk), // clock.clk
.reset_hps (~hps_h2f_reset_reset), // reset_hps.reset
.reset_sys (), // reset_sys.reset
.cold_req (reset_cold_req), // reset_ctl.cold_req
.reset (reset_reset), // .reset
.reset_req (reset_reset_req), // .reset_req
.reset_vip (0), // .reset_vip
.warm_req (reset_warm_req), // .warm_req
.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
.reset_cold (reset_source_reset_cold_reset) // reset_cold.reset
);
endmodule
`timescale 1 ps / 1 ps
module sysmem
(
input ramclk1_clk, // ramclk1.clk
input [28:0] ram1_address, // ram1.address
input [7:0] ram1_burstcount, // .burstcount
output ram1_waitrequest, // .waitrequest
output [63:0] ram1_readdata, // .readdata
output ram1_readdatavalid, // .readdatavalid
input ram1_read, // .read
input [63:0] ram1_writedata, // .writedata
input [7:0] ram1_byteenable, // .byteenable
input ram1_write, // .write
module sysmem_lite
(
output clock,
output reset_out,
input ramclk2_clk, // ramclk2.clk
input [28:0] ram2_address, // ram2.address
input [7:0] ram2_burstcount, // .burstcount
output ram2_waitrequest, // .waitrequest
output [63:0] ram2_readdata, // .readdata
output ram2_readdatavalid, // .readdatavalid
input ram2_read, // .read
input [63:0] ram2_writedata, // .writedata
input [7:0] ram2_byteenable, // .byteenable
input ram2_write, // .write
input reset_hps_cold_req,
input reset_hps_warm_req,
input reset_core_req,
input reset_cold_req, // reset.cold_req
output reset_reset, // .reset
input reset_reset_req, // .reset_req
input reset_warm_req, // .warm_req
input ram1_clk,
input [28:0] ram1_address,
input [7:0] ram1_burstcount,
output ram1_waitrequest,
output [63:0] ram1_readdata,
output ram1_readdatavalid,
input ram1_read,
input [63:0] ram1_writedata,
input [7:0] ram1_byteenable,
input ram1_write,
input [27:0] ram_vip_address, // ram_vip.address
input [7:0] ram_vip_burstcount, // .burstcount
output ram_vip_waitrequest, // .waitrequest
output [127:0] ram_vip_readdata, // .readdata
output ram_vip_readdatavalid, // .readdatavalid
input ram_vip_read, // .read
input [127:0] ram_vip_writedata, // .writedata
input [15:0] ram_vip_byteenable, // .byteenable
input ram_vip_write, // .write
input ram2_clk,
input [28:0] ram2_address,
input [7:0] ram2_burstcount,
output ram2_waitrequest,
output [63:0] ram2_readdata,
output ram2_readdatavalid,
input ram2_read,
input [63:0] ram2_writedata,
input [7:0] ram2_byteenable,
input ram2_write,
input vbuf_clk,
input [27:0] vbuf_address,
input [7:0] vbuf_burstcount,
output vbuf_waitrequest,
output [127:0] vbuf_readdata,
output vbuf_readdatavalid,
input vbuf_read,
input [127:0] vbuf_writedata,
input [15:0] vbuf_byteenable,
input vbuf_write
);
assign reset_out = ~init_reset_n | ~hps_h2f_reset_n | reset_core_req;
output clk_vip_clk, // clk_vip.clk
output reset_vip_reset // reset_vip.reset
);
wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps
wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n
wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n
sysmem_HPS_fpga_interfaces fpga_interfaces (
.f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n
.f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
.h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk
.h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n
.f2h_sdram0_clk (clk_vip_clk), // f2h_sdram0_clock.clk
.f2h_sdram0_ADDRESS (ram_vip_address), // f2h_sdram0_data.address
.f2h_sdram0_BURSTCOUNT (ram_vip_burstcount), // .burstcount
.f2h_sdram0_WAITREQUEST (ram_vip_waitrequest), // .waitrequest
.f2h_sdram0_READDATA (ram_vip_readdata), // .readdata
.f2h_sdram0_READDATAVALID (ram_vip_readdatavalid), // .readdatavalid
.f2h_sdram0_READ (ram_vip_read), // .read
.f2h_sdram0_WRITEDATA (ram_vip_writedata), // .writedata
.f2h_sdram0_BYTEENABLE (ram_vip_byteenable), // .byteenable
.f2h_sdram0_WRITE (ram_vip_write), // .write
.f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk
.f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address
.f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount
.f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest
.f2h_sdram1_READDATA (ram1_readdata), // .readdata
.f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid
.f2h_sdram1_READ (ram1_read), // .read
.f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata
.f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable
.f2h_sdram1_WRITE (ram1_write), // .write
.f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk
.f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address
.f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount
.f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest
.f2h_sdram2_READDATA (ram2_readdata), // .readdata
.f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid
.f2h_sdram2_READ (ram2_read), // .read
.f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata
.f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable
.f2h_sdram2_WRITE (ram2_write) // .write
);
reset_source reset_source (
.clk (clk_vip_clk), // clock.clk
.reset_hps (~hps_h2f_reset_reset), // reset_hps.reset
.reset_sys (reset_vip_reset), // reset_sys.reset
.cold_req (reset_cold_req), // reset_ctl.cold_req
.reset (reset_reset), // .reset
.reset_req (reset_reset_req), // .reset_req
.warm_req (reset_warm_req), // .warm_req
.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
.reset_cold (reset_source_reset_cold_reset) // reset_cold.reset
);
endmodule
module sysmem_HPS_fpga_interfaces
(
// h2f_reset
output wire [1 - 1 : 0 ] h2f_rst_n
// f2h_cold_reset_req
,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
// f2h_warm_reset_req
,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
// h2f_user0_clock
,output wire [1 - 1 : 0 ] h2f_user0_clk
// f2h_sdram0_data
,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram0_READ
,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
// f2h_sdram0_clock
,input wire [1 - 1 : 0 ] f2h_sdram0_clk
// f2h_sdram1_data
,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram1_READ
,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
// f2h_sdram1_clock
,input wire [1 - 1 : 0 ] f2h_sdram1_clk
// f2h_sdram2_data
,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram2_READ
,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
// f2h_sdram2_clock
,input wire [1 - 1 : 0 ] f2h_sdram2_clk
);
wire [29 - 1 : 0] intermediate;
assign intermediate[0:0] = ~intermediate[1:1];
assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
assign intermediate[2:2] = intermediate[9:9];
assign intermediate[3:3] = intermediate[9:9];
assign intermediate[5:5] = intermediate[9:9];
assign intermediate[6:6] = intermediate[9:9];
assign intermediate[10:10] = intermediate[9:9];
assign intermediate[11:11] = ~intermediate[12:12];
assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
assign intermediate[13:13] = intermediate[18:18];
assign intermediate[15:15] = intermediate[18:18];
assign intermediate[19:19] = intermediate[18:18];
assign intermediate[20:20] = ~intermediate[21:21];
assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
assign intermediate[22:22] = intermediate[27:27];
assign intermediate[24:24] = intermediate[27:27];
assign intermediate[28:28] = intermediate[27:27];
assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
assign intermediate[4:4] = f2h_sdram0_READ[0:0];
assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
assign intermediate[9:9] = f2h_sdram0_clk[0:0];
assign intermediate[14:14] = f2h_sdram1_READ[0:0];
assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
assign intermediate[18:18] = f2h_sdram1_clk[0:0];
assign intermediate[23:23] = f2h_sdram2_READ[0:0];
assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
assign intermediate[27:27] = f2h_sdram2_clk[0:0];
cyclonev_hps_interface_clocks_resets clocks_resets(
.f2h_warm_rst_req_n({
f2h_warm_rst_req_n[0:0] // 0:0
})
,.f2h_pending_rst_ack({
1'b1 // 0:0
})
,.f2h_dbg_rst_req_n({
1'b1 // 0:0
})
,.h2f_rst_n({
h2f_rst_n[0:0] // 0:0
})
,.f2h_cold_rst_req_n({
f2h_cold_rst_req_n[0:0] // 0:0
})
,.h2f_user0_clk({
h2f_user0_clk[0:0] // 0:0
})
);
cyclonev_hps_interface_dbg_apb debug_apb(
.DBG_APB_DISABLE({
1'b0 // 0:0
})
,.P_CLK_EN({
1'b0 // 0:0
})
);
cyclonev_hps_interface_tpiu_trace tpiu(
.traceclk_ctl({
1'b1 // 0:0
})
);
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
.boot_from_fpga_ready({
1'b0 // 0:0
})
,.boot_from_fpga_on_failure({
1'b0 // 0:0
})
,.bsel_en({
1'b0 // 0:0
})
,.csel_en({
1'b0 // 0:0
})
,.csel({
2'b01 // 1:0
})
,.bsel({
3'b001 // 2:0
})
);
cyclonev_hps_interface_fpga2hps fpga2hps(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_hps2fpga hps2fpga(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_fpga2sdram f2sdram(
.cfg_rfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.cfg_wfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.rd_ready_3({
1'b1 // 0:0
})
,.cmd_port_clk_2({
intermediate[28:28] // 0:0
})
,.rd_ready_2({
1'b1 // 0:0
})
,.cmd_port_clk_1({
intermediate[19:19] // 0:0
})
,.rd_ready_1({
1'b1 // 0:0
})
,.cmd_port_clk_0({
intermediate[10:10] // 0:0
})
,.rd_ready_0({
1'b1 // 0:0
})
,.wrack_ready_2({
1'b1 // 0:0
})
,.wrack_ready_1({
1'b1 // 0:0
})
,.wrack_ready_0({
1'b1 // 0:0
})
,.cmd_ready_2({
intermediate[21:21] // 0:0
})
,.cmd_ready_1({
intermediate[12:12] // 0:0
})
,.cmd_ready_0({
intermediate[1:1] // 0:0
})
,.cfg_port_width({
12'b000000010110 // 11:0
})
,.rd_valid_3({
f2h_sdram2_READDATAVALID[0:0] // 0:0
})
,.rd_valid_2({
f2h_sdram1_READDATAVALID[0:0] // 0:0
})
,.rd_valid_1({
f2h_sdram0_READDATAVALID[0:0] // 0:0
})
,.rd_clk_3({
intermediate[22:22] // 0:0
})
,.rd_data_3({
f2h_sdram2_READDATA[63:0] // 63:0
})
,.rd_clk_2({
intermediate[13:13] // 0:0
})
,.rd_data_2({
f2h_sdram1_READDATA[63:0] // 63:0
})
,.rd_clk_1({
intermediate[3:3] // 0:0
})
,.rd_data_1({
f2h_sdram0_READDATA[127:64] // 63:0
})
,.rd_clk_0({
intermediate[2:2] // 0:0
})
,.rd_data_0({
f2h_sdram0_READDATA[63:0] // 63:0
})
,.cfg_axi_mm_select({
6'b000000 // 5:0
})
,.cmd_valid_2({
intermediate[26:26] // 0:0
})
,.cmd_valid_1({
intermediate[17:17] // 0:0
})
,.cmd_valid_0({
intermediate[8:8] // 0:0
})
,.cfg_cport_rfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_data_3({
2'b00 // 89:88
,f2h_sdram2_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram2_WRITEDATA[63:0] // 63:0
})
,.wr_data_2({
2'b00 // 89:88
,f2h_sdram1_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram1_WRITEDATA[63:0] // 63:0
})
,.wr_data_1({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[15:8] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[127:64] // 63:0
})
,.cfg_cport_type({
12'b000000111111 // 11:0
})
,.wr_data_0({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[63:0] // 63:0
})
,.cfg_cport_wfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_clk_3({
intermediate[24:24] // 0:0
})
,.wr_clk_2({
intermediate[15:15] // 0:0
})
,.wr_clk_1({
intermediate[6:6] // 0:0
})
,.wr_clk_0({
intermediate[5:5] // 0:0
})
,.cmd_data_2({
18'b000000000000000000 // 59:42
,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram2_ADDRESS[28:0] // 30:2
,intermediate[25:25] // 1:1
,intermediate[23:23] // 0:0
})
,.cmd_data_1({
18'b000000000000000000 // 59:42
,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram1_ADDRESS[28:0] // 30:2
,intermediate[16:16] // 1:1
,intermediate[14:14] // 0:0
})
,.cmd_data_0({
18'b000000000000000000 // 59:42
,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
,4'b0000 // 33:30
,f2h_sdram0_ADDRESS[27:0] // 29:2
,intermediate[7:7] // 1:1
,intermediate[4:4] // 0:0
})
);
endmodule
.f2h_cold_rst_req_n (~reset_hps_cold_req),
.f2h_warm_rst_req_n (~reset_hps_warm_req),
.h2f_user0_clk (clock),
.h2f_rst_n (hps_h2f_reset_n),
.f2h_sdram0_clk (vbuf_clk),
.f2h_sdram0_ADDRESS (vbuf_address),
.f2h_sdram0_BURSTCOUNT (vbuf_burstcount),
.f2h_sdram0_WAITREQUEST (vbuf_waitrequest),
.f2h_sdram0_READDATA (vbuf_readdata),
.f2h_sdram0_READDATAVALID (vbuf_readdatavalid),
.f2h_sdram0_READ (vbuf_read),
.f2h_sdram0_WRITEDATA (vbuf_writedata),
.f2h_sdram0_BYTEENABLE (vbuf_byteenable),
.f2h_sdram0_WRITE (vbuf_write),
.f2h_sdram1_clk (ram1_clk),
.f2h_sdram1_ADDRESS (ram1_address),
.f2h_sdram1_BURSTCOUNT (ram1_burstcount),
.f2h_sdram1_WAITREQUEST (ram1_waitrequest),
.f2h_sdram1_READDATA (ram1_readdata),
.f2h_sdram1_READDATAVALID (ram1_readdatavalid),
.f2h_sdram1_READ (ram1_read),
.f2h_sdram1_WRITEDATA (ram1_writedata),
.f2h_sdram1_BYTEENABLE (ram1_byteenable),
.f2h_sdram1_WRITE (ram1_write),
.f2h_sdram2_clk (ram2_clk),
.f2h_sdram2_ADDRESS (ram2_address),
.f2h_sdram2_BURSTCOUNT (ram2_burstcount),
.f2h_sdram2_WAITREQUEST (ram2_waitrequest),
.f2h_sdram2_READDATA (ram2_readdata),
.f2h_sdram2_READDATAVALID (ram2_readdatavalid),
.f2h_sdram2_READ (ram2_read),
.f2h_sdram2_WRITEDATA (ram2_writedata),
.f2h_sdram2_BYTEENABLE (ram2_byteenable),
.f2h_sdram2_WRITE (ram2_write)
);
wire hps_h2f_reset_n;
reg init_reset_n = 0;
always @(posedge clock) begin
integer timeout = 0;
if(timeout < 2000000) begin
init_reset_n <= 0;
timeout <= timeout + 1;
end
else init_reset_n <= 1;
end
endmodule
module sysmem_HPS_fpga_interfaces
(
// h2f_reset
output wire [1 - 1 : 0 ] h2f_rst_n
// f2h_cold_reset_req
,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n
// f2h_warm_reset_req
,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n
// h2f_user0_clock
,output wire [1 - 1 : 0 ] h2f_user0_clk
// f2h_sdram0_data
,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST
,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram0_READ
,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA
,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE
// f2h_sdram0_clock
,input wire [1 - 1 : 0 ] f2h_sdram0_clk
// f2h_sdram1_data
,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram1_READ
,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE
// f2h_sdram1_clock
,input wire [1 - 1 : 0 ] f2h_sdram1_clk
// f2h_sdram2_data
,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS
,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT
,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST
,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA
,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID
,input wire [1 - 1 : 0 ] f2h_sdram2_READ
,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA
,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE
,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE
// f2h_sdram2_clock
,input wire [1 - 1 : 0 ] f2h_sdram2_clk
);
wire [29 - 1 : 0] intermediate;
assign intermediate[0:0] = ~intermediate[1:1];
assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7];
assign intermediate[2:2] = intermediate[9:9];
assign intermediate[3:3] = intermediate[9:9];
assign intermediate[5:5] = intermediate[9:9];
assign intermediate[6:6] = intermediate[9:9];
assign intermediate[10:10] = intermediate[9:9];
assign intermediate[11:11] = ~intermediate[12:12];
assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16];
assign intermediate[13:13] = intermediate[18:18];
assign intermediate[15:15] = intermediate[18:18];
assign intermediate[19:19] = intermediate[18:18];
assign intermediate[20:20] = ~intermediate[21:21];
assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25];
assign intermediate[22:22] = intermediate[27:27];
assign intermediate[24:24] = intermediate[27:27];
assign intermediate[28:28] = intermediate[27:27];
assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0];
assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11];
assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20];
assign intermediate[4:4] = f2h_sdram0_READ[0:0];
assign intermediate[7:7] = f2h_sdram0_WRITE[0:0];
assign intermediate[9:9] = f2h_sdram0_clk[0:0];
assign intermediate[14:14] = f2h_sdram1_READ[0:0];
assign intermediate[16:16] = f2h_sdram1_WRITE[0:0];
assign intermediate[18:18] = f2h_sdram1_clk[0:0];
assign intermediate[23:23] = f2h_sdram2_READ[0:0];
assign intermediate[25:25] = f2h_sdram2_WRITE[0:0];
assign intermediate[27:27] = f2h_sdram2_clk[0:0];
cyclonev_hps_interface_clocks_resets clocks_resets(
.f2h_warm_rst_req_n({
f2h_warm_rst_req_n[0:0] // 0:0
})
,.f2h_pending_rst_ack({
1'b1 // 0:0
})
,.f2h_dbg_rst_req_n({
1'b1 // 0:0
})
,.h2f_rst_n({
h2f_rst_n[0:0] // 0:0
})
,.f2h_cold_rst_req_n({
f2h_cold_rst_req_n[0:0] // 0:0
})
,.h2f_user0_clk({
h2f_user0_clk[0:0] // 0:0
})
);
cyclonev_hps_interface_dbg_apb debug_apb(
.DBG_APB_DISABLE({
1'b0 // 0:0
})
,.P_CLK_EN({
1'b0 // 0:0
})
);
cyclonev_hps_interface_tpiu_trace tpiu(
.traceclk_ctl({
1'b1 // 0:0
})
);
cyclonev_hps_interface_boot_from_fpga boot_from_fpga(
.boot_from_fpga_ready({
1'b0 // 0:0
})
,.boot_from_fpga_on_failure({
1'b0 // 0:0
})
,.bsel_en({
1'b0 // 0:0
})
,.csel_en({
1'b0 // 0:0
})
,.csel({
2'b01 // 1:0
})
,.bsel({
3'b001 // 2:0
})
);
cyclonev_hps_interface_fpga2hps fpga2hps(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_hps2fpga hps2fpga(
.port_size_config({
2'b11 // 1:0
})
);
cyclonev_hps_interface_fpga2sdram f2sdram(
.cfg_rfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.cfg_wfifo_cport_map({
16'b0010000100000000 // 15:0
})
,.rd_ready_3({
1'b1 // 0:0
})
,.cmd_port_clk_2({
intermediate[28:28] // 0:0
})
,.rd_ready_2({
1'b1 // 0:0
})
,.cmd_port_clk_1({
intermediate[19:19] // 0:0
})
,.rd_ready_1({
1'b1 // 0:0
})
,.cmd_port_clk_0({
intermediate[10:10] // 0:0
})
,.rd_ready_0({
1'b1 // 0:0
})
,.wrack_ready_2({
1'b1 // 0:0
})
,.wrack_ready_1({
1'b1 // 0:0
})
,.wrack_ready_0({
1'b1 // 0:0
})
,.cmd_ready_2({
intermediate[21:21] // 0:0
})
,.cmd_ready_1({
intermediate[12:12] // 0:0
})
,.cmd_ready_0({
intermediate[1:1] // 0:0
})
,.cfg_port_width({
12'b000000010110 // 11:0
})
,.rd_valid_3({
f2h_sdram2_READDATAVALID[0:0] // 0:0
})
,.rd_valid_2({
f2h_sdram1_READDATAVALID[0:0] // 0:0
})
,.rd_valid_1({
f2h_sdram0_READDATAVALID[0:0] // 0:0
})
,.rd_clk_3({
intermediate[22:22] // 0:0
})
,.rd_data_3({
f2h_sdram2_READDATA[63:0] // 63:0
})
,.rd_clk_2({
intermediate[13:13] // 0:0
})
,.rd_data_2({
f2h_sdram1_READDATA[63:0] // 63:0
})
,.rd_clk_1({
intermediate[3:3] // 0:0
})
,.rd_data_1({
f2h_sdram0_READDATA[127:64] // 63:0
})
,.rd_clk_0({
intermediate[2:2] // 0:0
})
,.rd_data_0({
f2h_sdram0_READDATA[63:0] // 63:0
})
,.cfg_axi_mm_select({
6'b000000 // 5:0
})
,.cmd_valid_2({
intermediate[26:26] // 0:0
})
,.cmd_valid_1({
intermediate[17:17] // 0:0
})
,.cmd_valid_0({
intermediate[8:8] // 0:0
})
,.cfg_cport_rfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_data_3({
2'b00 // 89:88
,f2h_sdram2_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram2_WRITEDATA[63:0] // 63:0
})
,.wr_data_2({
2'b00 // 89:88
,f2h_sdram1_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram1_WRITEDATA[63:0] // 63:0
})
,.wr_data_1({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[15:8] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[127:64] // 63:0
})
,.cfg_cport_type({
12'b000000111111 // 11:0
})
,.wr_data_0({
2'b00 // 89:88
,f2h_sdram0_BYTEENABLE[7:0] // 87:80
,16'b0000000000000000 // 79:64
,f2h_sdram0_WRITEDATA[63:0] // 63:0
})
,.cfg_cport_wfifo_map({
18'b000000000011010000 // 17:0
})
,.wr_clk_3({
intermediate[24:24] // 0:0
})
,.wr_clk_2({
intermediate[15:15] // 0:0
})
,.wr_clk_1({
intermediate[6:6] // 0:0
})
,.wr_clk_0({
intermediate[5:5] // 0:0
})
,.cmd_data_2({
18'b000000000000000000 // 59:42
,f2h_sdram2_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram2_ADDRESS[28:0] // 30:2
,intermediate[25:25] // 1:1
,intermediate[23:23] // 0:0
})
,.cmd_data_1({
18'b000000000000000000 // 59:42
,f2h_sdram1_BURSTCOUNT[7:0] // 41:34
,3'b000 // 33:31
,f2h_sdram1_ADDRESS[28:0] // 30:2
,intermediate[16:16] // 1:1
,intermediate[14:14] // 0:0
})
,.cmd_data_0({
18'b000000000000000000 // 59:42
,f2h_sdram0_BURSTCOUNT[7:0] // 41:34
,4'b0000 // 33:30
,f2h_sdram0_ADDRESS[27:0] // 29:2
,intermediate[7:7] // 1:1
,intermediate[4:4] // 0:0
})
);
endmodule

91
sys/video_cleaner.sv Normal file
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@ -0,0 +1,91 @@
//
//
// Copyright (c) 2018 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module video_cleaner
(
input clk_vid,
input ce_pix,
input [7:0] R,
input [7:0] G,
input [7:0] B,
input HSync,
input VSync,
input HBlank,
input VBlank,
// video output signals
output reg [7:0] VGA_R,
output reg [7:0] VGA_G,
output reg [7:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output VGA_DE,
// optional aligned blank
output reg HBlank_out,
output reg VBlank_out
);
wire hs, vs;
s_fix sync_v(clk_vid, HSync, hs);
s_fix sync_h(clk_vid, VSync, vs);
wire hbl = hs | HBlank;
wire vbl = vs | VBlank;
assign VGA_DE = ~(HBlank_out | VBlank_out);
always @(posedge clk_vid) begin
if(ce_pix) begin
HBlank_out <= hbl;
VGA_VS <= vs;
VGA_HS <= hs;
VGA_R <= R;
VGA_G <= G;
VGA_B <= B;
if(HBlank_out & ~hbl) VBlank_out <= vbl;
end
end
endmodule
module s_fix
(
input clk,
input sync_in,
output sync_out
);
assign sync_out = sync_in ^ pol;
reg pol;
always @(posedge clk) begin
integer pos = 0, neg = 0, cnt = 0;
reg s1,s2;
s1 <= sync_in;
s2 <= s1;
if(~s2 & s1) neg <= cnt;
if(s2 & ~s1) pos <= cnt;
cnt <= cnt + 1;
if(s2 != s1) cnt <= 0;
pol <= pos > neg;
end
endmodule

2
sys/video_mixer.sv
View File

@ -160,7 +160,7 @@ always @(posedge clk_sys) begin
VGA_HS <= hs;
old_hde <= hde;
if(~old_hde && hde && vde) VGA_DE <= 1;
if(~old_hde && hde) VGA_DE <= vde;
if(old_hde && ~hde) VGA_DE <= 0;
end

1177
sys/vip.qsys
View File

File diff suppressed because it is too large Load Diff

159
sys/vip_config.sv
View File

@ -1,159 +0,0 @@
module vip_config
(
input clk,
input reset,
input [7:0] ARX,
input [7:0] ARY,
input CFG_SET,
input [11:0] WIDTH,
input [11:0] HFP,
input [11:0] HBP,
input [11:0] HS,
input [11:0] HEIGHT,
input [11:0] VFP,
input [11:0] VBP,
input [11:0] VS,
input [11:0] VSET,
output reg [8:0] address,
output reg write,
output reg [31:0] writedata,
input waitrequest
);
reg newres = 1;
wire [21:0] init[23] =
'{
//video mode
{newres, 2'd2, 7'd04, 12'd0 }, //Bank
{newres, 2'd2, 7'd30, 12'd0 }, //Valid
{newres, 2'd2, 7'd05, 12'd0 }, //Progressive/Interlaced
{newres, 2'd2, 7'd06, w }, //Active pixel count
{newres, 2'd2, 7'd07, h }, //Active line count
{newres, 2'd2, 7'd09, hfp }, //Horizontal Front Porch
{newres, 2'd2, 7'd10, hs }, //Horizontal Sync Length
{newres, 2'd2, 7'd11, hb }, //Horizontal Blanking (HFP+HBP+HSync)
{newres, 2'd2, 7'd12, vfp }, //Vertical Front Porch
{newres, 2'd2, 7'd13, vs }, //Vertical Sync Length
{newres, 2'd2, 7'd14, vb }, //Vertical blanking (VFP+VBP+VSync)
{newres, 2'd2, 7'd30, 12'd1 }, //Valid
{newres, 2'd2, 7'd00, 12'd1 }, //Go
//mixer
{ 1'd1, 2'd1, 7'd03, w }, //Bkg Width
{ 1'd1, 2'd1, 7'd04, h }, //Bkg Height
{ 1'd1, 2'd1, 7'd08, posx }, //Pos X
{ 1'd1, 2'd1, 7'd09, posy }, //Pos Y
{ 1'd1, 2'd1, 7'd10, 12'd1 }, //Enable Video 0
{ 1'd1, 2'd1, 7'd00, 12'd1 }, //Go
//scaler
{ 1'd1, 2'd0, 7'd03, videow }, //Output Width
{ 1'd1, 2'd0, 7'd04, videoh }, //Output Height
{ 1'd1, 2'd0, 7'd00, 12'd1 }, //Go
22'h3FFFFF
};
reg [11:0] w;
reg [11:0] hfp;
reg [11:0] hbp;
reg [11:0] hs;
reg [11:0] hb;
reg [11:0] h;
reg [11:0] vfp;
reg [11:0] vbp;
reg [11:0] vs;
reg [11:0] vb;
reg [11:0] videow;
reg [11:0] videoh;
reg [11:0] posx;
reg [11:0] posy;
always @(posedge clk) begin
reg [7:0] state = 0;
reg [7:0] arx, ary;
reg [7:0] arxd, aryd;
reg [11:0] vset, vsetd;
reg cfg, cfgd;
reg [31:0] wcalc;
reg [31:0] hcalc;
reg [12:0] timeout = 0;
arxd <= ARX;
aryd <= ARY;
vsetd <= VSET;
cfg <= CFG_SET;
cfgd <= cfg;
write <= 0;
if(reset || (arx != arxd) || (ary != aryd) || (vset != vsetd) || (~cfgd && cfg)) begin
arx <= arxd;
ary <= aryd;
vset <= vsetd;
timeout <= '1;
state <= 0;
if(reset || (~cfgd && cfg)) newres <= 1;
end
else
if(timeout > 0)
begin
timeout <= timeout - 1'd1;
state <= 1;
if(!(timeout & 'h1f)) case(timeout>>5)
5: begin
w <= WIDTH;
hfp <= HFP;
hbp <= HBP;
hs <= HS;
h <= HEIGHT;
vfp <= VFP;
vbp <= VBP;
vs <= VS;
end
4: begin
hb <= hfp+hbp+hs;
vb <= vfp+vbp+vs;
end
3: begin
wcalc <= vset ? (vset*arx)/ary : (h*arx)/ary;
hcalc <= (w*ary)/arx;
end
2: begin
videow <= (!vset && (wcalc > w)) ? w : wcalc[11:0];
videoh <= vset ? vset : (hcalc > h) ? h : hcalc[11:0];
end
1: begin
posx <= (w - videow)>>1;
posy <= (h - videoh)>>1;
end
endcase
end
else
if(~waitrequest && state)
begin
state <= state + 1'd1;
write <= 0;
if((state&3)==3) begin
if(init[state>>2] == 22'h3FFFFF) begin
state <= 0;
newres <= 0;
end
else begin
writedata <= 0;
{write, address, writedata[11:0]} <= init[state>>2];
end
end
end
end
endmodule