From 7ca4b6b18373c572c4ef83b3898d44baf63ee408 Mon Sep 17 00:00:00 2001
From: sorgelig <pour.garbage@gmail.com>
Date: Sat, 23 Jan 2021 20:09:42 +0800
Subject: [PATCH] Update sys. Support for custom AR.

---
 MacPlus.sv                       | 111 ++++--
 sys/alsa.sv                      |  12 +-
 sys/arcade_video.v               | 630 +++++++++++++------------------
 sys/ascal.vhd                    | 379 ++++++++++++-------
 sys/audio_out.v                  | 247 +++++++++---
 sys/hdmi_config.sv               |  44 +--
 sys/hps_io.v                     | 100 +++--
 sys/iir_filter.v                 | 213 +++++++++++
 sys/mt32pi.sv                    | 283 ++++++++++++++
 sys/pll_audio.13.qip             |  17 +
 sys/pll_audio.qip                | 337 +++++++++++++++++
 sys/pll_audio.v                  | 252 +++++++++++++
 sys/pll_audio/pll_audio_0002.qip |   4 +
 sys/pll_audio/pll_audio_0002.v   |  87 +++++
 sys/pll_q13.qip                  |   1 +
 sys/pll_q17.qip                  |   1 +
 sys/{sd_card.v => sd_card.sv}    | 141 ++++---
 sys/spdif.v                      |  19 +-
 sys/sys.qip                      |   4 +-
 sys/sys_top.sdc                  |  41 +-
 sys/sys_top.v                    | 535 ++++++++++++++++----------
 sys/vga_out.sv                   |  44 ++-
 22 files changed, 2564 insertions(+), 938 deletions(-)
 create mode 100644 sys/iir_filter.v
 create mode 100644 sys/mt32pi.sv
 create mode 100644 sys/pll_audio.13.qip
 create mode 100644 sys/pll_audio.qip
 create mode 100644 sys/pll_audio.v
 create mode 100644 sys/pll_audio/pll_audio_0002.qip
 create mode 100644 sys/pll_audio/pll_audio_0002.v
 rename sys/{sd_card.v => sd_card.sv} (81%)

diff --git a/MacPlus.sv b/MacPlus.sv
index 6f98618..0fda29e 100644
--- a/MacPlus.sv
+++ b/MacPlus.sv
@@ -29,7 +29,7 @@ module emu
 	input         RESET,
 
 	//Must be passed to hps_io module
-	inout  [45:0] HPS_BUS,
+	inout  [45:0] HPS_BUS,
 
 	//Base video clock. Usually equals to CLK_SYS.
 	output        CLK_VIDEO,
@@ -39,8 +39,8 @@ module emu
 	output        CE_PIXEL,
 
 	//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
-	output  [7:0] VIDEO_ARX,
-	output  [7:0] VIDEO_ARY,
+	output [11:0] VIDEO_ARX,
+	output [11:0] VIDEO_ARY,
 
 	output  [7:0] VGA_R,
 	output  [7:0] VGA_G,
@@ -48,8 +48,36 @@ module emu
 	output        VGA_HS,
 	output        VGA_VS,
 	output        VGA_DE,    // = ~(VBlank | HBlank)
-	output        VGA_F1,
-	output  [1:0] VGA_SL,
+	output        VGA_F1,
+	output [1:0]  VGA_SL,
+	output        VGA_SCALER, // Force VGA scaler
+
+`ifdef USE_FB
+	// Use framebuffer in DDRAM (USE_FB=1 in qsf)
+	// FB_FORMAT:
+	//    [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
+	//    [3]   : 0=16bits 565 1=16bits 1555
+	//    [4]   : 0=RGB  1=BGR (for 16/24/32 modes)
+	//
+	// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
+	output        FB_EN,
+	output  [4:0] FB_FORMAT,
+	output [11:0] FB_WIDTH,
+	output [11:0] FB_HEIGHT,
+	output [31:0] FB_BASE,
+	output [13:0] FB_STRIDE,
+	input         FB_VBL,
+	input         FB_LL,
+	output        FB_FORCE_BLANK,
+
+	// Palette control for 8bit modes.
+	// Ignored for other video modes.
+	output        FB_PAL_CLK,
+	output  [7:0] FB_PAL_ADDR,
+	output [23:0] FB_PAL_DOUT,
+	input  [23:0] FB_PAL_DIN,
+	output        FB_PAL_WR,
+`endif
 
 	output        LED_USER,  // 1 - ON, 0 - OFF.
 
@@ -58,19 +86,20 @@ module emu
 	// hint: supply 2'b00 to let the system control the LED.
 	output  [1:0] LED_POWER,
 	output  [1:0] LED_DISK,
-
-	// I/O board button press simulation (active high)
-	// b[1]: user button
-	// b[0]: osd button
-	output  [1:0] BUTTONS,
 
+	// I/O board button press simulation (active high)
+	// b[1]: user button
+	// b[0]: osd button
+	output  [1:0] BUTTONS,
+
+	input         CLK_AUDIO, // 24.576 MHz
 	output [15:0] AUDIO_L,
 	output [15:0] AUDIO_R,
 	output        AUDIO_S,   // 1 - signed audio samples, 0 - unsigned
 	output  [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
-
-	//ADC
-	inout   [3:0] ADC_BUS,
+
+	//ADC
+	inout   [3:0] ADC_BUS,
 
 	//SD-SPI
 	output        SD_SCK,
@@ -79,6 +108,7 @@ module emu
 	output        SD_CS,
 	input         SD_CD,
 
+`ifdef USE_DDRAM
 	//High latency DDR3 RAM interface
 	//Use for non-critical time purposes
 	output        DDRAM_CLK,
@@ -91,7 +121,9 @@ module emu
 	output [63:0] DDRAM_DIN,
 	output  [7:0] DDRAM_BE,
 	output        DDRAM_WE,
+`endif
 
+`ifdef USE_SDRAM
 	//SDRAM interface with lower latency
 	output        SDRAM_CLK,
 	output        SDRAM_CKE,
@@ -103,24 +135,38 @@ module emu
 	output        SDRAM_nCS,
 	output        SDRAM_nCAS,
 	output        SDRAM_nRAS,
-	output        SDRAM_nWE,
-
-	input         UART_CTS,
-	output        UART_RTS,
-	input         UART_RXD,
-	output        UART_TXD,
-	output        UART_DTR,
-	input         UART_DSR,
-
-	// Open-drain User port.
-	// 0 - D+/RX
-	// 1 - D-/TX
+	output        SDRAM_nWE,
+`endif
+
+`ifdef DUAL_SDRAM
+	//Secondary SDRAM
+	input         SDRAM2_EN,
+	output        SDRAM2_CLK,
+	output [12:0] SDRAM2_A,
+	output  [1:0] SDRAM2_BA,
+	inout  [15:0] SDRAM2_DQ,
+	output        SDRAM2_nCS,
+	output        SDRAM2_nCAS,
+	output        SDRAM2_nRAS,
+	output        SDRAM2_nWE,
+`endif
+
+	input         UART_CTS,
+	output        UART_RTS,
+	input         UART_RXD,
+	output        UART_TXD,
+	output        UART_DTR,
+	input         UART_DSR,
+
+	// Open-drain User port.
+	// 0 - D+/RX
+	// 1 - D-/TX
 	// 2..6 - USR2..USR6
-	// Set USER_OUT to 1 to read from USER_IN.
+	// Set USER_OUT to 1 to read from USER_IN.
 	input   [6:0] USER_IN,
 	output  [6:0] USER_OUT,
-
-	input         OSD_STATUS
+
+	input         OSD_STATUS
 );
 
 assign ADC_BUS  = 'Z;
@@ -133,9 +179,12 @@ assign LED_USER  = dio_download || (disk_act ^ |diskMotor);
 assign LED_DISK  = 0;
 assign LED_POWER = 0;
 assign BUTTONS   = 0;
+assign VGA_SCALER= 0;
 
-assign VIDEO_ARX = status[8] ? 8'd16 : 8'd4;
-assign VIDEO_ARY = status[8] ? 8'd9  : 8'd3; 
+wire [1:0] ar = status[8:7];
+
+assign VIDEO_ARX = (!ar) ? 12'd4 : (ar - 1'd1);
+assign VIDEO_ARY = (!ar) ? 12'd3 : 12'd0;
 
 `include "build_id.v" 
 localparam CONF_STR = {
@@ -146,7 +195,7 @@ localparam CONF_STR = {
 	"-;",
 	"S0,VHD,Mount HDD;",
 	"-;",
-	"O8,Aspect ratio,4:3,16:9;",
+	"O78,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
 	"O9A,Memory,512KB,1MB,4MB;",
 	"O5,Speed,Normal,Turbo;",
 	"-;",
diff --git a/sys/alsa.sv b/sys/alsa.sv
index 061a287..9034389 100644
--- a/sys/alsa.sv
+++ b/sys/alsa.sv
@@ -20,6 +20,9 @@
 //============================================================================
 
 module alsa
+#(
+	parameter CLK_RATE = 24576000
+)
 (
 	input             reset,
 	input             clk,
@@ -139,17 +142,14 @@ always @(posedge clk) begin
 	end
 end
 
-localparam F48K = 48000;
-localparam F50M = 50000000;
-
 reg ce_sample;
 always @(posedge clk) begin
 	reg [31:0] acc = 0;
 
 	ce_sample <= 0;
-	acc <= acc + F48K + {hurryup,6'd0};
-	if(acc >= F50M) begin
-		acc <= acc - F50M;
+	acc <= acc + 48000 + {hurryup,6'd0};
+	if(acc >= CLK_RATE) begin
+		acc <= acc - CLK_RATE;
 		ce_sample <= 1;
 	end
 end
diff --git a/sys/arcade_video.v b/sys/arcade_video.v
index ba86c9b..a1683f5 100644
--- a/sys/arcade_video.v
+++ b/sys/arcade_video.v
@@ -2,258 +2,6 @@
 //
 //  Copyright (C) 2017-2020 Sorgelig
 //
-//============================================================================
-
-//////////////////////////////////////////////////////////
-// DW:
-//  6 : 2R 2G 2B
-//  8 : 3R 3G 2B
-//  9 : 3R 3G 3B
-// 12 : 4R 4G 4B
-// 24 : 8R 8G 8B
-
-module arcade_video #(parameter WIDTH=320, HEIGHT=240, DW=8, GAMMA=1)
-(
-	input         clk_video,
-	input         ce_pix,
-
-	input[DW-1:0] RGB_in,
-	input         HBlank,
-	input         VBlank,
-	input         HSync,
-	input         VSync,
-
-	output        VGA_CLK,
-	output        VGA_CE,
-	output  [7:0] VGA_R,
-	output  [7:0] VGA_G,
-	output  [7:0] VGA_B,
-	output        VGA_HS,
-	output        VGA_VS,
-	output        VGA_DE,
-
-	output        HDMI_CLK,
-	output        HDMI_CE,
-	output  [7:0] HDMI_R,
-	output  [7:0] HDMI_G,
-	output  [7:0] HDMI_B,
-	output        HDMI_HS,
-	output        HDMI_VS,
-	output        HDMI_DE,
-	output  [1:0] HDMI_SL,
-	
-	input   [2:0] fx,
-	input         forced_scandoubler,
-	input         no_rotate,
-	input         rotate_ccw,
-	inout  [21:0] gamma_bus
-);
-
-wire [7:0] R,G,B;
-wire       CE,HS,VS,HBL,VBL;
-
-wire [DW-1:0] RGB_fix;
-wire VGA_HBL, VGA_VBL;
-arcade_vga #(DW) vga
-(
-	.clk_video(clk_video),
-	.ce_pix(ce_pix),
-
-	.RGB_in(RGB_in),
-	.HBlank(HBlank),
-	.VBlank(VBlank),
-	.HSync(HSync),
-	.VSync(VSync),
-
-	.RGB_out(RGB_fix),
-	.VGA_CLK(VGA_CLK),
-	.VGA_CE(CE),
-	.VGA_R(R),
-	.VGA_G(G),
-	.VGA_B(B),
-	.VGA_HS(HS),
-	.VGA_VS(VS),
-	.VGA_HBL(HBL),
-	.VGA_VBL(VBL)
-);
-
-wire [DW-1:0] RGB_out;
-wire rhs,rvs,rhblank,rvblank;
-
-screen_rotate #(WIDTH,HEIGHT,DW,4) rotator
-(
-	.clk(VGA_CLK),
-	.ce(CE),
-
-	.ccw(rotate_ccw),
-
-	.video_in(RGB_fix),
-	.hblank(HBL),
-	.vblank(VBL),
-
-	.ce_out(CE | (~scandoubler & ~gamma_bus[19])),
-	.video_out(RGB_out),
-	.hsync(rhs),
-	.vsync(rvs),
-	.hblank_out(rhblank),
-	.vblank_out(rvblank)
-);
-
-generate
-	if(DW == 6) begin
-		wire [3:0] Rr = {RGB_out[5:4],RGB_out[5:4]};
-		wire [3:0] Gr = {RGB_out[3:2],RGB_out[3:2]};
-		wire [3:0] Br = {RGB_out[1:0],RGB_out[1:0]};
-	end
-	else if(DW == 8) begin
-		wire [3:0] Rr = {RGB_out[7:5],RGB_out[7]};
-		wire [3:0] Gr = {RGB_out[4:2],RGB_out[4]};
-		wire [3:0] Br = {RGB_out[1:0],RGB_out[1:0]};
-	end
-	else if(DW == 9) begin
-		wire [3:0] Rr = {RGB_out[8:6],RGB_out[8]};
-		wire [3:0] Gr = {RGB_out[5:3],RGB_out[5]};
-		wire [3:0] Br = {RGB_out[2:0],RGB_out[2]};
-	end
-	else if(DW == 12) begin
-		wire [3:0] Rr = RGB_out[11:8];
-		wire [3:0] Gr = RGB_out[7:4];
-		wire [3:0] Br = RGB_out[3:0];
-	end
-	else begin // 24
-		wire [7:0] Rr = RGB_out[23:16];
-		wire [7:0] Gr = RGB_out[15:8];
-		wire [7:0] Br = RGB_out[7:0];
-	end
-endgenerate
-
-assign HDMI_CLK = VGA_CLK;
-assign HDMI_SL  = sl[1:0];
-wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
-wire scandoubler = fx || forced_scandoubler;
-
-video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer
-(
-	.clk_vid(HDMI_CLK),
-	.ce_pix(CE | (~scandoubler & ~gamma_bus[19] & ~no_rotate)),
-	.ce_pix_out(HDMI_CE),
-
-	.scandoubler(scandoubler),
-	.hq2x(fx==1),
-	.gamma_bus(gamma_bus),
-
-	.R(no_rotate ? ((DW!=24) ? R[7:4] : R) : Rr),
-	.G(no_rotate ? ((DW!=24) ? G[7:4] : G) : Gr),
-	.B(no_rotate ? ((DW!=24) ? B[7:4] : B) : Br),
-
-	.HSync (no_rotate ? HS  : rhs),
-	.VSync (no_rotate ? VS  : rvs),
-	.HBlank(no_rotate ? HBL : rhblank),
-	.VBlank(no_rotate ? VBL : rvblank),
-
-	.VGA_R(HDMI_R),
-	.VGA_G(HDMI_G),
-	.VGA_B(HDMI_B),
-	.VGA_VS(HDMI_VS),
-	.VGA_HS(HDMI_HS),
-	.VGA_DE(HDMI_DE)
-);
-
-assign VGA_CE = no_rotate ? HDMI_CE : CE;
-assign VGA_R  = no_rotate ? HDMI_R  : R;
-assign VGA_G  = no_rotate ? HDMI_G  : G;
-assign VGA_B  = no_rotate ? HDMI_B  : B;
-assign VGA_HS = no_rotate ? HDMI_HS : HS;
-assign VGA_VS = no_rotate ? HDMI_VS : VS;
-assign VGA_DE = no_rotate ? HDMI_DE : ~(HBL | VBL);
-
-endmodule
-
-//////////////////////////////////////////////////////////
-
-module arcade_vga #(parameter DW)
-(
-	input          clk_video,
-	input          ce_pix,
-
-	input [DW-1:0] RGB_in,
-	input          HBlank,
-	input          VBlank,
-	input          HSync,
-	input          VSync,
-
-	output[DW-1:0] RGB_out,
-	output         VGA_CLK,
-	output reg     VGA_CE,
-	output  [7:0]  VGA_R,
-	output  [7:0]  VGA_G,
-	output  [7:0]  VGA_B,
-	output reg     VGA_HS,
-	output reg     VGA_VS,
-	output reg     VGA_HBL,
-	output reg     VGA_VBL
-);
-
-assign VGA_CLK = clk_video;
-
-wire hs_fix,vs_fix;
-sync_fix sync_v(VGA_CLK, HSync, hs_fix);
-sync_fix sync_h(VGA_CLK, VSync, vs_fix);
-
-reg [DW-1:0] RGB_fix;
-
-always @(posedge VGA_CLK) begin
-	reg old_ce;
-	old_ce <= ce_pix;
-	VGA_CE <= 0;
-	if(~old_ce & ce_pix) begin
-		VGA_CE <= 1;
-		VGA_HS <= hs_fix;
-		if(~VGA_HS & hs_fix) VGA_VS <= vs_fix;
-
-		RGB_fix <= RGB_in;
-		VGA_HBL <= HBlank;
-		if(VGA_HBL & ~HBlank) VGA_VBL <= VBlank;
-	end
-end
-
-assign RGB_out = RGB_fix;
-
-generate
-	if(DW == 6) begin
-		assign VGA_R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]};
-		assign VGA_G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]};
-		assign VGA_B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
-	end
-	else if(DW == 8) begin
-		assign VGA_R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]};
-		assign VGA_G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]};
-		assign VGA_B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
-	end
-	else if(DW == 9) begin
-		assign VGA_R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]};
-		assign VGA_G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]};
-		assign VGA_B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]};
-	end
-	else if(DW == 12) begin
-		assign VGA_R = {RGB_fix[11:8],RGB_fix[11:8]};
-		assign VGA_G = {RGB_fix[7:4],RGB_fix[7:4]};
-		assign VGA_B = {RGB_fix[3:0],RGB_fix[3:0]};
-	end
-	else begin // 24
-		assign VGA_R = RGB_fix[23:16];
-		assign VGA_G = RGB_fix[15:8];
-		assign VGA_B = RGB_fix[7:0];
-	end
-endgenerate
-
-endmodule
-
-//============================================================================
-//
-//  Screen +90/-90 deg. rotation
-//  Copyright (C) 2017-2019 Sorgelig
-//
 //  This program is free software; you can redistribute it and/or modify it
 //  under the terms of the GNU General Public License as published by the Free
 //  Software Foundation; either version 2 of the License, or (at your option)
@@ -267,139 +15,287 @@ endmodule
 //  You should have received a copy of the GNU General Public License along
 //  with this program; if not, write to the Free Software Foundation, Inc.,
 //  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//
 //============================================================================
 
-//
-// Output timings are incompatible with any TV/VGA mode.
-// The output is supposed to be send to scaler input.
-//
-module screen_rotate #(parameter WIDTH=320, HEIGHT=240, DEPTH=8, MARGIN=4)
+//////////////////////////////////////////////////////////
+// DW:
+//  6 : 2R 2G 2B
+//  8 : 3R 3G 2B
+//  9 : 3R 3G 3B
+// 12 : 4R 4G 4B
+// 24 : 8R 8G 8B
+
+module arcade_video #(parameter WIDTH=320, DW=8, GAMMA=1)
 (
-	input              clk,
-	input              ce,
+	input         clk_video,
+	input         ce_pix,
 
-	input              ccw,
+	input[DW-1:0] RGB_in,
+	input         HBlank,
+	input         VBlank,
+	input         HSync,
+	input         VSync,
 
-	input  [DEPTH-1:0] video_in,
-	input              hblank,
-	input              vblank,
+	output        CLK_VIDEO,
+	output        CE_PIXEL,
+	output  [7:0] VGA_R,
+	output  [7:0] VGA_G,
+	output  [7:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        VGA_DE,
+	output  [1:0] VGA_SL,
 
-	input              ce_out,
-	output [DEPTH-1:0] video_out,
-	output reg         hsync,
-	output reg         vsync,
-	output reg         hblank_out,
-	output reg         vblank_out
+	input   [2:0] fx,
+	input         forced_scandoubler,
+	inout  [21:0] gamma_bus
 );
 
-localparam bufsize = WIDTH*HEIGHT;
-localparam memsize = bufsize*2;
-localparam aw = $clog2(memsize); // resolutions up to ~ 512x256
+assign CLK_VIDEO = clk_video;
 
-reg [aw-1:0] addr_in, addr_out;
-reg we_in;
-reg buff = 0;
+wire hs_fix,vs_fix;
+sync_fix sync_v(CLK_VIDEO, HSync, hs_fix);
+sync_fix sync_h(CLK_VIDEO, VSync, vs_fix);
 
-(* ramstyle="no_rw_check" *) reg [DEPTH-1:0] ram[memsize];
-always @ (posedge clk) if (en_we) ram[addr_in] <= video_in;
-always @ (posedge clk) out <= ram[addr_out];
+reg [DW-1:0] RGB_fix;
 
-reg [DEPTH-1:0] out; 
-reg [DEPTH-1:0] vout;
+reg CE,HS,VS,HBL,VBL;
+always @(posedge CLK_VIDEO) begin
+	reg old_ce;
+	old_ce <= ce_pix;
+	CE <= 0;
+	if(~old_ce & ce_pix) begin
+		CE <= 1;
+		HS <= hs_fix;
+		if(~HS & hs_fix) VS <= vs_fix;
 
-assign video_out = vout;
-
-wire en_we = ce & ~blank & en_x & en_y;
-wire en_x = (xpos<WIDTH);
-wire en_y = (ypos<HEIGHT);
-integer xpos, ypos;
-
-wire blank = hblank | vblank;
-always @(posedge clk) begin
-	reg old_blank, old_vblank;
-	reg [aw-1:0] addr_row;
-
-	if(en_we) begin
-		addr_in <= ccw ? addr_in-HEIGHT[aw-1:0] : addr_in+HEIGHT[aw-1:0];
-		xpos <= xpos + 1;
-	end
-
-	old_blank <= blank;
-	old_vblank <= vblank;
-	if(~old_blank & blank) begin
-		xpos <= 0;
-		ypos <= ypos + 1;
-		addr_in  <= ccw ? addr_row + 1'd1 : addr_row - 1'd1;
-		addr_row <= ccw ? addr_row + 1'd1 : addr_row - 1'd1;
-	end
-
-	if(~old_vblank & vblank) begin
-		if(buff) begin
-			addr_in  <= ccw ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
-			addr_row <= ccw ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
-		end else begin
-			addr_in  <= ccw ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
-			addr_row <= ccw ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
-		end
-		buff <= ~buff;
-		ypos <= 0;
-		xpos <= 0;
+		RGB_fix <= RGB_in;
+		HBL <= HBlank;
+		if(HBL & ~HBlank) VBL <= VBlank;
 	end
 end
 
-always @(posedge clk) begin
-	reg old_buff;
-	reg hs;
-	reg ced;
+wire [7:0] R,G,B;
 
-	integer vbcnt;
-	integer xposo, yposo, xposd, yposd;
-	
-	ced <= 0;
-	if(ce_out) begin
-		ced <= 1;
-
-		xposd <= xposo;
-		yposd <= yposo;
-
-		if(xposo == (HEIGHT + 8))  hsync <= 1;
-		if(xposo == (HEIGHT + 10)) hsync <= 0;
-
-		if((yposo>=MARGIN) && (yposo<WIDTH+MARGIN)) begin
-			if(xposo < HEIGHT) addr_out <= addr_out + 1'd1;
-		end
-
-		xposo <= xposo + 1;
-		if(xposo > (HEIGHT + 16)) begin
-			xposo  <= 0;
-			
-			if(yposo >= (WIDTH+MARGIN+MARGIN)) begin
-				vblank_out <= 1;
-				vbcnt <= vbcnt + 1;
-				if(vbcnt == 10	) vsync <= 1;
-				if(vbcnt == 12) vsync <= 0;
-			end
-			else yposo <= yposo + 1;
-			
-			old_buff <= buff;
-			if(old_buff != buff) begin
-				addr_out <= buff ? {aw{1'b0}} : bufsize[aw-1:0];
-				yposo <= 0;
-				vsync <= 0;
-				vbcnt <= 0;
-				vblank_out <= 0;
-			end
-		end
+generate
+	if(DW == 6) begin
+		assign R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]};
+		assign G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]};
+		assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
 	end
-	
-	if(ced) begin
-		if((yposd<MARGIN) || (yposd>=WIDTH+MARGIN)) begin
-			vout <= 0;
-		end else begin
-			vout <= out;
+	else if(DW == 8) begin
+		assign R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]};
+		assign G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]};
+		assign B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
+	end
+	else if(DW == 9) begin
+		assign R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]};
+		assign G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]};
+		assign B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]};
+	end
+	else if(DW == 12) begin
+		assign R = {RGB_fix[11:8],RGB_fix[11:8]};
+		assign G = {RGB_fix[7:4],RGB_fix[7:4]};
+		assign B = {RGB_fix[3:0],RGB_fix[3:0]};
+	end
+	else begin // 24
+		assign R = RGB_fix[23:16];
+		assign G = RGB_fix[15:8];
+		assign B = RGB_fix[7:0];
+	end
+endgenerate
+
+assign VGA_SL  = sl[1:0];
+wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
+wire scandoubler = fx || forced_scandoubler;
+
+video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer
+(
+	.clk_vid(CLK_VIDEO),
+	.ce_pix(CE),
+	.ce_pix_out(CE_PIXEL),
+
+	.scandoubler(scandoubler),
+	.hq2x(fx==1),
+	.gamma_bus(gamma_bus),
+
+	.R((DW!=24) ? R[7:4] : R),
+	.G((DW!=24) ? G[7:4] : G),
+	.B((DW!=24) ? B[7:4] : B),
+
+	.HSync (HS),
+	.VSync (VS),
+	.HBlank(HBL),
+	.VBlank(VBL),
+
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.VGA_DE(VGA_DE)
+);
+
+endmodule
+
+//============================================================================
+//
+//  Screen +90/-90 deg. rotation
+//  Copyright (C) 2020 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//
+//============================================================================
+
+module screen_rotate
+(
+	input         CLK_VIDEO,
+	input         CE_PIXEL,
+
+	input   [7:0] VGA_R,
+	input   [7:0] VGA_G,
+	input   [7:0] VGA_B,
+	input         VGA_HS,
+	input         VGA_VS,
+	input         VGA_DE,
+
+	input         rotate_ccw,
+	input         no_rotate,
+
+	output        FB_EN,
+	output  [4:0] FB_FORMAT,
+	output [11:0] FB_WIDTH,
+	output [11:0] FB_HEIGHT,
+	output [31:0] FB_BASE,
+	output [13:0] FB_STRIDE,
+	input         FB_VBL,
+	input         FB_LL,
+
+	output        DDRAM_CLK,
+	input         DDRAM_BUSY,
+	output  [7:0] DDRAM_BURSTCNT,
+	output [28:0] DDRAM_ADDR,
+	output [63:0] DDRAM_DIN,
+	output  [7:0] DDRAM_BE,
+	output        DDRAM_WE,
+	output        DDRAM_RD
+);
+
+parameter MEM_BASE    = 7'b0010010; // buffer at 0x24000000, 3x8MB
+
+assign DDRAM_CLK      = CLK_VIDEO;
+assign DDRAM_BURSTCNT = 1;
+assign DDRAM_ADDR     = {MEM_BASE, i_fb, ram_addr[22:3]};
+assign DDRAM_BE       = ram_addr[2] ? 8'hF0 : 8'h0F;
+assign DDRAM_DIN      = {ram_data,ram_data};
+assign DDRAM_WE       = ram_wr;
+assign DDRAM_RD       = 0;
+
+assign FB_EN     = fb_en[2];
+assign FB_FORMAT = 5'b00110;
+assign FB_BASE   = {MEM_BASE,o_fb,23'd0};
+assign FB_WIDTH  = vsz;
+assign FB_HEIGHT = hsz;
+assign FB_STRIDE = stride;
+
+function [1:0] buf_next;
+	input [1:0] a,b;
+	begin
+		buf_next = 1;
+		if ((a==0 && b==1) || (a==1 && b==0)) buf_next = 2;
+		if ((a==1 && b==2) || (a==2 && b==1)) buf_next = 0;
+	end
+endfunction
+
+reg [1:0] i_fb,o_fb;
+always @(posedge CLK_VIDEO) begin
+	reg old_vbl,old_vs;
+	old_vbl <= FB_VBL;
+	old_vs <= VGA_VS;
+
+	if(FB_LL) begin
+		if(~old_vbl & FB_VBL) o_fb<={1'b0,~i_fb[0]};
+		if(~old_vs & VGA_VS)  i_fb<={1'b0,~i_fb[0]};
+	end
+	else begin
+		if(~old_vbl & FB_VBL) o_fb<=buf_next(o_fb,i_fb);
+		if(~old_vs & VGA_VS)  i_fb<=buf_next(i_fb,o_fb);
+	end
+end
+
+initial begin
+	fb_en = 0;
+end
+
+reg  [2:0] fb_en = 0;
+reg [11:0] hsz = 320, vsz = 240;
+reg [11:0] bwidth;
+reg [22:0] bufsize;
+always @(posedge CLK_VIDEO) begin
+	reg [11:0] hcnt = 0, vcnt = 0;
+	reg old_vs, old_de;
+
+	if(CE_PIXEL) begin
+		old_vs <= VGA_VS;
+		old_de <= VGA_DE;
+		
+		hcnt <= hcnt + 1'd1;
+		if(~old_de & VGA_DE) begin
+			hcnt <= 1;
+			vcnt <= vcnt + 1'd1;
+		end
+		if(old_de & ~VGA_DE) hsz <= hcnt;
+		if(~old_vs & VGA_VS) begin
+			vsz <= vcnt;
+			bwidth <= vcnt + 2'd3;
+			vcnt <= 0;
+			fb_en <= {fb_en[1:0], ~no_rotate};
+		end
+		if(old_vs & ~VGA_VS) bufsize <= hsz * stride;
+	end
+end
+
+wire [13:0] stride = {bwidth[11:2], 4'd0};
+
+reg [22:0] ram_addr, next_addr;
+reg [31:0] ram_data;
+reg        ram_wr;
+always @(posedge CLK_VIDEO) begin
+	reg [13:0] hcnt = 0;
+	reg old_vs, old_de;
+
+	ram_wr <= 0;
+	if(CE_PIXEL) begin
+		old_vs <= VGA_VS;
+		old_de <= VGA_DE;
+
+		if(~old_vs & VGA_VS) begin
+			next_addr <= rotate_ccw ? (bufsize - stride) : {vsz-1'd1, 2'b00};
+			hcnt <= rotate_ccw ? 3'd4 : {vsz-2'd2, 2'b00};
+		end
+		if(VGA_DE) begin
+			ram_wr <= 1;
+			ram_data <= {VGA_B,VGA_G,VGA_R};
+			ram_addr <= next_addr;
+			next_addr <= rotate_ccw ? (next_addr - stride) : (next_addr + stride);
+		end
+		if(old_de & ~VGA_DE) begin
+			next_addr <= rotate_ccw ? (bufsize - stride + hcnt) : hcnt;
+			hcnt <= rotate_ccw ? (hcnt + 3'd4) : (hcnt - 3'd4);
 		end
-		if(xposd == 0)       hblank_out <= 0;
-		if(xposd == HEIGHT)  hblank_out <= 1;
 	end
 end
 
diff --git a/sys/ascal.vhd b/sys/ascal.vhd
index 0f89a9e..6d687ac 100644
--- a/sys/ascal.vhd
+++ b/sys/ascal.vhd
@@ -1,14 +1,14 @@
 --------------------------------------------------------------------------------
 -- AVALON SCALER
 --------------------------------------------------------------------------------
--- TEMLIB 10/2018
+-- TEMLIB 2018 - 2020
 --------------------------------------------------------------------------------
 -- This code can be freely distributed and used for any purpose, but, if you
 -- find any bug, or want to suggest an enhancement, you ought to send a mail
 -- to info@temlib.org.
 --------------------------------------------------------------------------------
 
--- Features :
+-- Features
 --  - Arbitrary output video format
 --  - Autodetect input image size or fixed window
 --  - Progressive and interlaced input
@@ -30,7 +30,7 @@
 --   below 1x) them.
 
 --------------------------------------------
--- 5 clock domains :
+-- 5 clock domains
 --  i_xxx    : Input video
 --  o_xxx    : Output video
 --  avl_xxx  : Avalon memory bus
@@ -54,10 +54,10 @@
 --  1    : Pixel format
 --         0 : 16 bits/pixel, RGB : RRRRRGGGGGGBBBBB
 --         1 : 24 bits/pixel, RGB
---         2 : 32 bits/pixels RGB0
+--         2 : 32 bits/pixel, RGB0
 
 --  3:2  : Header size : Offset to start of picture (= N_BURST). 12 bits
---  5:4  : Attributes. TBD
+--  5:4  : Attributes
 --         b0 ; Interlaced
 --         b1 : Field number
 --         b2 : Horizontal downscaled
@@ -83,7 +83,7 @@ USE ieee.numeric_std.ALL;
 -- 100 : Polyphase
 -- 101 : TBD
 -- 110 : TBD
--- 111 : TEST
+-- 111 : TBD
 
 -- MODE[3]
 -- 0 : Direct. Single framebuffer.
@@ -98,7 +98,8 @@ USE ieee.numeric_std.ALL;
 --             Must be a power of two
 -- INTER     : True=Autodetect interlaced video False=Force progressive scan
 -- HEADER    : True=Add image properties header
--- PALETTE   : Enable palette for framebuffer -8bpp mode
+-- PALETTE   : Enable palette for framebuffer 8bpp mode
+-- PALETTE2  : Enable palette for framebuffer 8bpp mode supplied by core
 -- DOWNSCALE : True=Support downscaling False=Downscaling disabled
 -- BYTESWAP  : Little/Big endian byte swap
 -- FRAC      : Fractional bits, subpixel resolution
@@ -120,6 +121,7 @@ ENTITY ascal IS
     DOWNSCALE : boolean := true;
     BYTESWAP  : boolean := true;
     PALETTE   : boolean := true;
+    PALETTE2  : boolean := true;
     FRAC      : natural RANGE 4 TO 6 :=4;
     OHRES     : natural RANGE 1 TO 4096 :=2048;
     IHRES     : natural RANGE 1 TO 2048 :=2048;
@@ -148,6 +150,7 @@ ENTITY ascal IS
     o_hs  : OUT std_logic; -- H sync
     o_vs  : OUT std_logic; -- V sync
     o_de  : OUT std_logic; -- Display Enable
+    o_vbl : OUT std_logic; -- V blank
     o_ce  : IN  std_logic; -- Clock Enable
     o_clk : IN  std_logic; -- Output clock
     
@@ -161,13 +164,22 @@ ENTITY ascal IS
     o_fb_vsize  : IN natural RANGE 0 TO 4095 :=0;
     o_fb_format : IN unsigned(5 DOWNTO 0) :="000100";
     o_fb_base   : IN unsigned(31 DOWNTO 0) :=x"0000_0000";
-
+    o_fb_stride : IN unsigned(13 DOWNTO 0) :=(OTHERS =>'0');
+    
     -- Framebuffer palette in 8bpp mode
-    pal_clk : IN std_logic :='0';
-    pal_dw  : IN  unsigned(47 DOWNTO 0) :=x"000000000000"; -- R1 G1 B1 R0 G0 B0
-    pal_dr  : OUT unsigned(47 DOWNTO 0) :=x"000000000000";
-    pal_a   : IN  unsigned(6 DOWNTO 0)  :="0000000"; -- Colour index/2
-    pal_wr  : IN  std_logic :='0';
+    pal1_clk : IN std_logic :='0';
+    pal1_dw  : IN unsigned(47 DOWNTO 0) :=x"000000000000"; -- R1 G1 B1 R0 G0 B0
+    pal1_dr  : OUT unsigned(47 DOWNTO 0) :=x"000000000000";
+    pal1_a   : IN unsigned(6 DOWNTO 0)  :="0000000"; -- Colour index/2
+    pal1_wr  : IN std_logic :='0';
+
+    pal_n    : IN std_logic :='0';
+
+    pal2_clk : IN std_logic :='0';
+    pal2_dw  : IN unsigned(23 DOWNTO 0) :=x"000000"; -- R G B
+    pal2_dr  : OUT unsigned(23 DOWNTO 0) :=x"000000";
+    pal2_a   : IN unsigned(7 DOWNTO 0)  :="00000000"; -- Colour index
+    pal2_wr  : IN std_logic :='0';
     
     ------------------------------------
     -- Low lag PLL tuning
@@ -175,11 +187,15 @@ ENTITY ascal IS
     
     ------------------------------------
     -- Input video parameters
-    iauto : IN std_logic; -- 1=Autodetect image size 0=Choose window
-    himin : IN natural RANGE 0 TO 4095; -- MIN < MAX, MIN >=0, MAX < DISP
-    himax : IN natural RANGE 0 TO 4095;
-    vimin : IN natural RANGE 0 TO 4095;
-    vimax : IN natural RANGE 0 TO 4095;
+    iauto : IN std_logic :='1'; -- 1=Autodetect image size 0=Choose window
+    himin : IN natural RANGE 0 TO 4095 :=0; -- MIN < MAX, MIN >=0, MAX < DISP
+    himax : IN natural RANGE 0 TO 4095 :=0;
+    vimin : IN natural RANGE 0 TO 4095 :=0;
+    vimax : IN natural RANGE 0 TO 4095 :=0;
+
+    -- Detected input image size
+    i_hdmax : OUT natural RANGE 0 TO 4095;
+    i_vdmax : OUT natural RANGE 0 TO 4095;
     
     -- Output video parameters
     run    : IN std_logic :='1'; -- 1=Enable output image. 0=No image
@@ -187,7 +203,7 @@ ENTITY ascal IS
     mode   : IN unsigned(4 DOWNTO 0);
     -- SYNC  |_________________________/"""""""""\_______|
     -- DE    |""""""""""""""""""\________________________|
-    -- RGB   |    <#IMAGE#>     ^HDISP                   |
+    -- RGB   |    <#IMAGE#>      ^HDISP                  |
     --            ^HMIN   ^HMAX        ^HSSTART  ^HSEND  ^HTOTAL
     htotal  : IN natural RANGE 0 TO 4095;
     hsstart : IN natural RANGE 0 TO 4095;
@@ -284,10 +300,11 @@ ARCHITECTURE rtl OF ascal IS
   SUBTYPE uint13 IS natural RANGE 0 TO 8191;
   
   TYPE arr_uv48 IS ARRAY (natural RANGE <>) OF unsigned(47 DOWNTO 0);
+  TYPE arr_uv24 IS ARRAY (natural RANGE <>) OF unsigned(23 DOWNTO 0);
   TYPE arr_uv36 IS ARRAY (natural RANGE <>) OF unsigned(35 DOWNTO 0);
   TYPE arr_int9 IS ARRAY (natural RANGE <>) OF integer RANGE -256 TO 255;
   TYPE arr_uint12 IS ARRAY (natural RANGE <>) OF uint12;
-
+
   ----------------------------------------------------------
   -- Input image
   SIGNAL i_pvs,i_pfl,i_pde,i_pce : std_logic;
@@ -385,12 +402,15 @@ ARCHITECTURE rtl OF ascal IS
   SIGNAL o_run : std_logic;
   SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0);
   SIGNAL o_format : unsigned(5 DOWNTO 0);
-  SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0);
-  SIGNAL o_fb_pal_dr_x2 : unsigned(47 DOWNTO 0);
-  SIGNAL pal_idx: unsigned(7 DOWNTO 0);
-  SIGNAL pal_idx_lsb: std_logic;
-  SIGNAL pal_mem : arr_uv48(0 TO 127);
-  ATTRIBUTE ramstyle of pal_mem : signal is "no_rw_check";
+  SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0);
+  SIGNAL o_fb_pal_dr2 : unsigned(23 DOWNTO 0);
+  SIGNAL o_fb_pal_dr_x2 : unsigned(47 DOWNTO 0);
+  SIGNAL pal_idx: unsigned(7 DOWNTO 0);
+  SIGNAL pal_idx_lsb: std_logic;
+  SIGNAL pal1_mem : arr_uv48(0 TO 127);
+  SIGNAL pal2_mem : arr_uv24(0 TO 255);
+  ATTRIBUTE ramstyle of pal1_mem : signal is "no_rw_check";
+  ATTRIBUTE ramstyle of pal2_mem : signal is "no_rw_check";
   SIGNAL o_htotal,o_hsstart,o_hsend : uint12;
   SIGNAL o_hmin,o_hmax,o_hdisp : uint12;
   SIGNAL o_hsize,o_vsize : uint12;
@@ -400,14 +420,18 @@ ARCHITECTURE rtl OF ascal IS
   SIGNAL o_iendframe0,o_iendframe02,o_iendframe1,o_iendframe12 : std_logic;
   SIGNAL o_bufup0,o_bufup1,o_inter : std_logic;
   SIGNAL o_ibuf0,o_ibuf1,o_obuf0,o_obuf1 : natural RANGE 0 TO 2;
-  TYPE type_o_state IS (sDISP,sHSYNC,sREAD,sWAITREAD);
-  SIGNAL o_state : type_o_state;
-  SIGNAL o_copy,o_readack,o_readack_sync,o_readack_sync2 : std_logic;
+  TYPE enum_o_state IS (sDISP,sHSYNC,sREAD,sWAITREAD);
+  SIGNAL o_state : enum_o_state;
+  TYPE enum_o_copy IS (sWAIT,sSHIFT,sCOPY);
+  SIGNAL o_copy : enum_o_copy;
+  SIGNAL o_pshift : natural RANGE 0 TO 15;
+  SIGNAL o_readack,o_readack_sync,o_readack_sync2 : std_logic;
   SIGNAL o_readdataack,o_readdataack_sync,o_readdataack_sync2 : std_logic;
   SIGNAL o_copyv : unsigned(0 TO 8);
   SIGNAL o_adrs : unsigned(31 DOWNTO 0); -- Avalon address
-  SIGNAL o_adrs_pre : natural RANGE 0 TO 32*4096-1;
-  SIGNAL o_adrsa,o_rline : std_logic;
+  SIGNAL o_adrs_pre : natural RANGE 0 TO 2**23-1;
+  SIGNAL o_stride : unsigned(13 DOWNTO 0);
+  SIGNAL o_adrsa,o_adrsb,o_rline : std_logic;
   SIGNAL o_ad,o_ad1,o_ad2,o_ad3 : natural RANGE 0 TO 2*BLEN-1;
   SIGNAL o_adturn : std_logic;
   SIGNAL o_dr : unsigned(N_DW-1 DOWNTO 0);
@@ -425,12 +449,12 @@ ARCHITECTURE rtl OF ascal IS
   SIGNAL o_ldw,o_ldr0,o_ldr1,o_ldr2,o_ldr3 : type_pix;
   SIGNAL o_wr : unsigned(3 DOWNTO 0);
   SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3 : uint12;
-  SIGNAL o_ihsize,o_ivsize : uint12;
+  SIGNAL o_ihsize,o_ihsizem,o_ivsize : uint12;
   SIGNAL o_ihsize_temp, o_ihsize_temp2 : natural RANGE 0 TO 32767;
 
   SIGNAL o_vfrac,o_hfrac,o_hfrac1,o_hfrac2,o_hfrac3,o_hfrac4 : unsigned(11 DOWNTO 0);
   SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1;
-  SIGNAL o_hsv,o_vsv,o_dev,o_pev : unsigned(0 TO 5);
+  SIGNAL o_hsv,o_vsv,o_dev,o_pev,o_end : unsigned(0 TO 5);
   SIGNAL o_hsp,o_vss : std_logic;
   SIGNAL o_read,o_read_pre : std_logic;
   SIGNAL o_readlev,o_copylev : natural RANGE 0 TO 2;
@@ -438,11 +462,13 @@ ARCHITECTURE rtl OF ascal IS
   SIGNAL o_fload : natural RANGE 0 TO 3;
   SIGNAL o_acpt,o_acpt1,o_acpt2,o_acpt3,o_acpt4 : natural RANGE 0 TO 15; -- Alternance pixels FIFO
   SIGNAL o_dshi : natural RANGE 0 TO 3;
-  SIGNAL o_first,o_last,o_last1,o_last2,o_last3 : std_logic;
-  SIGNAL o_lastt1,o_lastt2,o_lastt3 : std_logic;
+  SIGNAL o_first,o_last,o_last1,o_last2 : std_logic;
+  SIGNAL o_lastt1,o_lastt2,o_lastt3,o_lastt4 : std_logic;
   SIGNAL o_alt,o_altx : unsigned(3 DOWNTO 0);
   SIGNAL o_hdown,o_vdown : std_logic;
   SIGNAL o_primv,o_lastv,o_bibv : unsigned(0 TO 2);
+  TYPE arr_uint4 IS ARRAY (natural RANGE <>) OF natural RANGE 0 TO 15;
+  SIGNAL o_off : arr_uint4(0 TO 2);
   SIGNAL o_bibu : std_logic :='0';
   SIGNAL o_dcptv : arr_uint12(1 TO 8);
   SIGNAL o_dcpt : uint12;
@@ -596,7 +622,7 @@ ARCHITECTURE rtl OF ascal IS
                (N_DW=64  AND ((acpt MOD 2)=0));
     END CASE;
   END FUNCTION;
-
+  
   FUNCTION shift_opix (shift  : unsigned(0 TO N_DW+15);
                        format : unsigned(5 DOWNTO 0)) RETURN type_pix IS
   BEGIN
@@ -618,6 +644,19 @@ ARCHITECTURE rtl OF ascal IS
     END CASE;
   END FUNCTION;
   
+  FUNCTION pixoffset(adrs   : unsigned(31 DOWNTO 0);
+                     format : unsigned (5 DOWNTO 0)) RETURN natural IS
+  BEGIN
+    CASE format(2 DOWNTO 0) IS
+      WHEN "011" => -- 8bbp
+        RETURN to_integer(adrs(NB_LA-1 DOWNTO 0));
+      WHEN "100" => -- 16bpp 565
+        RETURN to_integer(adrs(NB_LA-1 DOWNTO 1));
+      WHEN OTHERS => -- 32bpp
+        RETURN to_integer(adrs(NB_LA-1 DOWNTO 2));
+    END CASE;
+  END FUNCTION;
+  
   FUNCTION swap(d : unsigned(N_DW-1 DOWNTO 0)) RETURN unsigned IS
     VARIABLE e : unsigned(N_DW-1 DOWNTO 0);
   BEGIN
@@ -1071,9 +1110,16 @@ BEGIN
           i_hmin<=himin; -- <ASYNC>
           i_hmax<=himax; -- <ASYNC>
           i_vmin<=vimin; -- <ASYNC>
-          i_vmax<=vimax; -- <ASYNC>
+          IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN
+            i_vmax<=vimax; -- <ASYNC>
+          END IF;
         END IF;
-
+        
+        IF i_pvs='1' AND i_vs_pre='0' AND (i_inter='0' OR i_pfl='0') THEN
+          i_vdmax<=i_vimax;
+        END IF;
+        i_hdmax<=i_himax;
+        
         IF i_format="00" OR i_format="11" THEN -- 16bpp
           i_hburst<=(i_hrsize*2 + N_BURST - 1) / N_BURST;
         ELSIF i_format="01" THEN -- 24bpp
@@ -1449,6 +1495,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- AVALON interface
   Avaloir:PROCESS(avl_clk,avl_reset_na) IS
+    VARIABLE adr_v : unsigned(31 DOWNTO 0);
   BEGIN
     IF avl_reset_na='0' THEN
       avl_state<=sIDLE;
@@ -1529,7 +1576,6 @@ BEGIN
                 avl_wadrs(N_AW+NB_LA-1 DOWNTO NB_LA) +
                 avl_i_offset1(N_AW+NB_LA-1 DOWNTO NB_LA));
             END IF;
-            
           ELSIF avl_read_sr='1' THEN
             avl_state<=sREAD;
             avl_read_clr<='1';
@@ -1546,14 +1592,12 @@ BEGIN
           
         WHEN sREAD =>
           IF avl_rline='0' THEN
-            avl_address<=std_logic_vector(
-              avl_radrs(N_AW+NB_LA-1 DOWNTO NB_LA) +
-              avl_o_offset0(N_AW+NB_LA-1 DOWNTO NB_LA));
+            adr_v:=avl_radrs + avl_o_offset0;
           ELSE
-            avl_address<=std_logic_vector(
-              avl_radrs(N_AW+NB_LA-1 DOWNTO NB_LA) +
-              avl_o_offset1(N_AW+NB_LA-1 DOWNTO NB_LA));
-          END IF;  
+            adr_v:=avl_radrs + avl_o_offset1;
+          END IF;
+          avl_address<=std_logic_vector(adr_v(N_AW+NB_LA-1 DOWNTO NB_LA));
+          
           avl_read_i<='1';
           IF avl_read_i='1' AND avl_waitrequest='0' THEN
             avl_state<=sIDLE;
@@ -1648,9 +1692,10 @@ BEGIN
     VARIABLE hpix_v : type_pix;
     VARIABLE hcarry_v,vcarry_v : boolean;
     VARIABLE dif_v : natural RANGE 0 TO 8*OHRES-1;
+    VARIABLE off_v : natural RANGE 0 TO 15;
  BEGIN
     IF o_reset_na='0' THEN
-      o_copy<='0';
+      o_copy<=sWAIT;
       o_state<=sDISP;
       o_read_pre<='0';
       o_readlev<=0;
@@ -1712,12 +1757,21 @@ BEGIN
         o_ihsize<=o_fb_hsize;
         o_ivsize<=o_fb_vsize;
         o_format<=o_fb_format;
+        o_hdown<='0';
+        o_vdown<='0';
       END IF;
       
       o_ihsize_temp <= o_ihsize * to_integer(o_format(2 DOWNTO 0) - 2);
       o_ihsize_temp2 <= (o_ihsize_temp + N_BURST - 1);
       o_hburst <= o_ihsize_temp2 / N_BURST;
       
+      IF o_fb_ena='1' AND o_fb_stride /= 0 THEN
+        o_stride<=o_fb_stride;
+      ELSE
+        o_stride<=to_unsigned(o_ihsize_temp2,14);
+        o_stride(NB_BURST-1 DOWNTO 0)<=(OTHERS =>'0');
+      END IF;
+      
       IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN
         o_obuf0<=buf_next(o_obuf0,o_ibuf0);
         o_bufup0<='0';
@@ -1778,13 +1832,15 @@ BEGIN
       o_vpe<=to_std_logic(o_vcpt_pre<o_vmax AND o_vcpt_pre>=o_vmin);
       o_divstart<='0';
       o_adrsa<='0';
-
+      o_adrsb<=o_adrsa;
+      
       o_vacc_ini<=(o_vsize - o_ivsize + 8192) MOD 8192;
       o_hacc_ini<=(o_hsize + o_ihsize + 8192) MOD 8192;
       
+      --Alternate phase
       --o_vacc_ini<=o_ivsize;
       --o_hacc_ini<=(2*o_hsize - o_ihsize + 8192) MOD 8192;
-
+      
       CASE o_state IS
           --------------------------------------------------
         WHEN sDISP =>
@@ -1806,13 +1862,13 @@ BEGIN
             vcarry_v:=true;
           END IF;
           o_divstart<='1';
-          IF o_vcpt_pre2=o_vmin THEN --pe='0' THEN
+          IF o_vcpt_pre2=o_vmin THEN
             o_vacc     <=o_vacc_ini;
             o_vacc_next<=o_vacc_ini + 2*o_ivsize;
             o_vacpt<=x"001";
             vcarry_v:=false;
           END IF;
-
+          
           IF vcarry_v THEN
             o_vacpt<=o_vacpt+1;
           END IF;
@@ -1825,7 +1881,7 @@ BEGIN
           
         WHEN sREAD =>
           -- Read a block
-          IF o_readlev<2 THEN
+          IF o_readlev<2 AND o_adrsb='1' THEN
             lev_inc_v:='1';
             o_read_pre<=NOT o_read_pre;
             o_state <=sWAITREAD;
@@ -1834,6 +1890,10 @@ BEGIN
           prim_v:=to_std_logic(o_hbcpt=0);
           last_v:=to_std_logic(o_hbcpt=o_hburst-1);
           bib_v :=o_bibu;
+          off_v :=pixoffset(o_adrs + o_fb_base(NB_LA-1 DOWNTO 0),o_fb_format);
+          IF o_fb_ena='0' THEN
+            off_v:=0;
+          END IF;
           o_adrsa<='1';
           
         WHEN sWAITREAD =>
@@ -1854,18 +1914,18 @@ BEGIN
       END CASE;
       
       o_read<=o_read_pre AND o_run;
-      
-      o_adrs_pre<=to_integer(o_vacpt) * o_hburst;
       o_rline<=o_vacpt(0); -- Even/Odd line for interlaced video
+      
+      o_adrs_pre<=to_integer(o_vacpt) * to_integer(o_stride);
       IF o_adrsa='1' THEN
         IF o_fload=2 THEN
           o_adrs<=to_unsigned(o_hbcpt * N_BURST,32);
           o_alt<="1111";
         ELSIF o_fload=1 THEN
-          o_adrs<=to_unsigned((o_hburst + o_hbcpt) * N_BURST,32);
+          o_adrs<=to_unsigned(o_hbcpt * N_BURST,32) + o_stride;
           o_alt<="0100";
         ELSE
-          o_adrs<=to_unsigned((o_adrs_pre + o_hbcpt) * N_BURST,32);
+          o_adrs<=to_unsigned(o_adrs_pre + (o_hbcpt * N_BURST),32);
           o_alt<=altx(o_vacpt(1 DOWNTO 0) + 1);
         END IF;
       END IF;
@@ -1873,86 +1933,104 @@ BEGIN
       ------------------------------------------------------
       -- Copy from buffered memory to pixel lines
       o_sh<='0';
-      IF o_copy='0' THEN
-        o_copyv(0)<='0';
-        IF o_copylev>0 AND o_copyv(0)='0' THEN
-          o_copy<='1';
-          o_altx<=o_alt;
-        END IF;
-        o_adturn<='0';
-        
-        IF o_primv(0)='1' THEN
-          -- First memcopy of a horizontal line, carriage return !
-          o_hacc     <=o_hacc_ini;
-          o_hacc_next<=o_hacc_ini + 2*o_ihsize;
-          o_hacpt    <=x"000";
-          o_dcpt<=0;
-          o_dshi<=2;
-          o_acpt<=0;
-          o_first<='1';
-          o_last<='0';
-        END IF;
-        
-        IF o_bibv(0)='0' THEN
-          o_ad<=0;
-        ELSE
-          o_ad<=BLEN;
-        END IF;
-        
-      ELSE
-        -- dshi : Force shift first two or three pixels of each line
-        IF o_dshi=0  THEN
-          dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES);
-          IF dif_v>=4*OHRES THEN
-            o_hacc<=o_hacc_next;
-            o_hacc_next<=o_hacc_next + 2*o_ihsize;
-            hcarry_v:=false;
-          ELSE
-            o_hacc<=dif_v;
-            o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES);
-            hcarry_v:=true;
+      CASE o_copy IS
+        WHEN sWAIT =>
+          o_copyv(0)<='0';
+          IF o_copylev>0 AND o_copyv(0)='0' THEN
+            o_copy<=sCOPY;
+            IF o_off(0)>0 AND o_primv(0)='1' THEN
+              o_copy<=sSHIFT;
+            END IF;
+            o_altx<=o_alt;
           END IF;
-          o_dcpt<=(o_dcpt+1) MOD 4096;
-        ELSE
-          o_dshi<=o_dshi-1;
-          hcarry_v:=false;
-        END IF;
-        IF o_dshi<=1 THEN
-          o_copyv(0)<='1';
-        END IF;
-        IF hcarry_v THEN
+          o_adturn<='0';
+          o_pshift<=o_off(0) -1;
+          IF o_primv(0)='1' THEN
+            -- First memcopy of a horizontal line, carriage return !
+            o_ihsizem<=o_ihsize + o_off(0) - 2;
+            o_hacc     <=o_hacc_ini;
+            o_hacc_next<=o_hacc_ini + 2*o_ihsize;
+            o_hacpt    <=x"000";
+            o_dcpt<=0;
+            o_dshi<=2;
+            o_acpt<=0;
+            o_first<='1';
+            o_last<='0';
+          END IF;
+          
+          IF o_bibv(0)='0' THEN
+            o_ad<=0;
+          ELSE
+            o_ad<=BLEN;
+          END IF;
+          
+        WHEN sSHIFT =>
           o_hacpt<=o_hacpt+1;
-          o_last<=to_std_logic(o_hacpt>=o_ihsize-2);
-        END IF;
-        
-        IF hcarry_v OR o_dshi>0 THEN
           o_sh<='1';
           o_acpt<=(o_acpt+1) MOD 16;
-          
-          -- Shift two more pixels to the right before ending line.
-          o_last1<=o_last;
-          o_last2<=o_last1;
-          
           IF shift_onext(o_acpt,o_format) THEN
             o_ad<=(o_ad+1) MOD (2*BLEN);
           END IF;
-          
-          IF o_adturn='1' AND (shift_onext((o_acpt+1) MOD 16,o_format)) AND
-            (((o_ad MOD BLEN=0) AND o_lastv(0)='0') OR o_last2='1')  THEN
-            o_copy<='0';
-            lev_dec_v:='1';
+          o_pshift<=o_pshift-1;
+          IF o_pshift=0 THEN
+            o_copy<=sCOPY;
           END IF;
           
-          IF o_ad MOD BLEN=4 THEN
-            o_adturn<='1';
+        WHEN sCOPY =>
+          -- dshi : Force shift first two or three pixels of each line
+          IF o_dshi=0 THEN
+            dif_v:=(o_hacc_next - 2*o_hsize + (8*OHRES)) MOD (8*OHRES);
+            IF dif_v>=4*OHRES THEN
+              o_hacc<=o_hacc_next;
+              o_hacc_next<=o_hacc_next + 2*o_ihsize;
+              hcarry_v:=false;
+            ELSE
+              o_hacc<=dif_v;
+              o_hacc_next<=(dif_v + 2*o_ihsize + (4*OHRES)) MOD (4*OHRES);
+              hcarry_v:=true;
+            END IF;
+            o_dcpt<=(o_dcpt+1) MOD 4096;
+          ELSE
+            o_dshi<=o_dshi-1;
+            hcarry_v:=false;
           END IF;
-        END IF;
-      END IF;
+          IF o_dshi<=1 THEN
+            o_copyv(0)<='1';
+          END IF;
+          IF hcarry_v THEN
+            o_hacpt<=o_hacpt+1;
+            o_last <=to_std_logic(o_hacpt>=o_ihsizem);
+          END IF;
+          
+          IF hcarry_v OR o_dshi>0 THEN
+            o_sh<='1';
+            o_acpt<=(o_acpt+1) MOD 16;
+            
+            -- Shift two more pixels to the right before ending line.
+            o_last1<=o_last;
+            o_last2<=o_last1;
+            
+            IF shift_onext(o_acpt,o_format) THEN
+              o_ad<=(o_ad+1) MOD (2*BLEN);
+            END IF;
+            
+            IF o_adturn='1' AND (shift_onext((o_acpt+1) MOD 16,o_format)) AND
+              (((o_ad MOD BLEN=0) AND o_lastv(0)='0') OR o_last2='1')  THEN
+              o_copy<=sWAIT;
+              lev_dec_v:='1';
+            END IF;
+            
+            IF o_ad MOD BLEN=4 THEN
+              o_adturn<='1';
+            END IF;
+          END IF;
+      END CASE;    
       
       o_acpt1<=o_acpt; o_acpt2<=o_acpt1; o_acpt3<=o_acpt2; o_acpt4<=o_acpt3;
       o_ad1<=o_ad; o_ad2<=o_ad1; o_ad3<=o_ad2;
       o_sh1<=o_sh; o_sh2<=o_sh1; o_sh3<=o_sh2; o_sh4<=o_sh3;
-      o_lastt1<=o_last; o_lastt2<=o_lastt1; o_lastt3<=o_lastt2;
+      o_lastt1<=o_last;   o_lastt2<=o_lastt1;
+      o_lastt3<=o_lastt2; o_lastt4<=o_lastt3;
       
       ------------------------------------------------------
       IF o_sh3='1' THEN
@@ -1982,7 +2060,7 @@ BEGIN
           o_hpix2<=hpix_v;
           o_first<='0';
         END IF;
-        IF o_lastt3='1' THEN
+        IF o_lastt4='1' THEN
           -- Right edge. Keep last pixel.
           o_hpix0<=o_hpix0;
         END IF;
@@ -2010,6 +2088,7 @@ BEGIN
         o_primv(0 TO 1)<=o_primv(1 TO 2); -- First buffer of line
         o_lastv(0 TO 1)<=o_lastv(1 TO 2); -- Last buffer of line
         o_bibv (0 TO 1)<=o_bibv (1 TO 2); -- Double buffer select
+        o_off  (0 TO 1)<=o_off  (1 TO 2); -- Start offset
       END IF;
       
       IF lev_inc_v='1' THEN
@@ -2017,15 +2096,18 @@ BEGIN
           o_primv(0)<=prim_v;
           o_lastv(0)<=last_v;
           o_bibv (0)<=bib_v;
+          o_off  (0)<=off_v;
         ELSIF (o_readlev=1 AND lev_dec_v='0') OR
               (o_readlev=2 AND lev_dec_v='1') THEN
           o_primv(1)<=prim_v;
           o_lastv(1)<=last_v;
           o_bibv (1)<=bib_v;
+          o_off  (1)<=off_v;
         END IF;
         o_primv(2)<=prim_v;
         o_lastv(2)<=last_v;
         o_bibv (2)<=bib_v;
+        o_off  (2)<=off_v;
       END IF;
       
       ------------------------------------------------------
@@ -2039,22 +2121,40 @@ BEGIN
   o_v_poly_dr<=o_v_poly(o_v_poly_a) WHEN rising_edge(o_clk);
   
   -- Framebuffer palette
-  GenPal:IF PALETTE GENERATE
-    Tempera:PROCESS(pal_clk) IS
+  GenPal1:IF PALETTE GENERATE
+    Tempera1:PROCESS(pal1_clk) IS
     BEGIN
-      IF rising_edge(pal_clk) THEN
-        IF pal_wr='1' THEN
-          pal_mem(to_integer(pal_a))<=pal_dw;
+      IF rising_edge(pal1_clk) THEN
+        IF pal1_wr='1' THEN
+          pal1_mem(to_integer(pal1_a))<=pal1_dw;
         END IF;
-        pal_dr<=pal_mem(to_integer(pal_a));
+        pal1_dr<=pal1_mem(to_integer(pal1_a));
       END IF;
     END PROCESS;
-
-    pal_idx <= shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7);
-    pal_idx_lsb <= pal_idx(0) WHEN rising_edge(o_clk);
-    o_fb_pal_dr_x2 <= pal_mem(to_integer(pal_idx(7 DOWNTO 1))) WHEN rising_edge(o_clk);
+
+    pal_idx <= shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7);
+    pal_idx_lsb <= pal_idx(0) WHEN rising_edge(o_clk);
+    o_fb_pal_dr_x2 <= pal1_mem(to_integer(pal_idx(7 DOWNTO 1))) WHEN rising_edge(o_clk);
+  END GENERATE GenPal1;
+  
+  GenPal2:IF PALETTE and PALETTE2 GENERATE
+    Tempera2:PROCESS(pal2_clk) IS
+    BEGIN
+      IF rising_edge(pal2_clk) THEN
+        IF pal2_wr='1' THEN
+          pal2_mem(to_integer(pal2_a))<=pal2_dw;
+        END IF;
+        pal2_dr<=pal2_mem(to_integer(pal2_a));
+      END IF;
+    END PROCESS;
+
+    o_fb_pal_dr2 <= pal2_mem(to_integer(pal_idx(7 DOWNTO 0))) WHEN rising_edge(o_clk);
+    o_fb_pal_dr <= o_fb_pal_dr2 when pal_n = '1' else o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0);
+  END GENERATE GenPal2;
+
+  GenPal1not2:IF PALETTE and not PALETTE2 GENERATE
     o_fb_pal_dr <= o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0);
-  END GENERATE GenPal;
+  END GENERATE GenPal1not2;
   
   GenNoPal:IF NOT PALETTE GENERATE
     o_fb_pal_dr<=x"000000";
@@ -2152,7 +2252,7 @@ BEGIN
       o_copyv(1 TO 8)<=o_copyv(0 TO 7);
       
       o_dcptv(1)<=o_dcpt;
-      IF o_dcptv(1)>o_hsize THEN
+      IF o_dcptv(1)>=o_hsize THEN
         o_copyv(2)<='0';
       END IF;
       o_dcptv(2)<=o_dcptv(1) MOD OHRES;
@@ -2283,6 +2383,7 @@ BEGIN
           o_vcpt<=o_vcpt_pre;
         END IF;
         
+        o_end(0)<=to_std_logic(o_vcpt>=o_vdisp);
         o_dev(0)<=to_std_logic(o_hcpt<o_hdisp AND o_vcpt<o_vdisp);
         o_pev(0)<=to_std_logic(o_hcpt>=o_hmin AND o_hcpt<=o_hmax AND
                                o_vcpt>=o_vmin AND o_vcpt<=o_vmax);
@@ -2290,18 +2391,20 @@ BEGIN
         o_vsv(0)<=to_std_logic((o_vcpt=o_vsstart AND o_hcpt>=o_hsstart) OR
                                (o_vcpt>o_vsstart AND o_vcpt<o_vsend) OR
                                (o_vcpt=o_vsend   AND o_hcpt<o_hsstart));
-
+        
         o_vss<=to_std_logic(o_vcpt_pre2>=o_vmin AND o_vcpt_pre2<=o_vmax);
         o_hsv(1 TO 5)<=o_hsv(0 TO 4);
         o_vsv(1 TO 5)<=o_vsv(0 TO 4);
         o_dev(1 TO 5)<=o_dev(0 TO 4);
         o_pev(1 TO 5)<=o_pev(0 TO 4);
+        o_end(1 TO 5)<=o_end(0 TO 4);
         
         IF o_run='0' THEN
           o_hsv(2)<='0';
           o_vsv(2)<='0';
           o_dev(2)<='0';
           o_pev(2)<='0';
+          o_end(2)<='0';
         END IF;
         
       END IF;
@@ -2318,7 +2421,7 @@ BEGIN
       IF o_ce='1' THEN
         -- CYCLE 1 -----------------------------------------
         -- Read mem
-        o_radl<=(o_hcpt-o_hmin+OHRES) MOD OHRES;
+        o_radl<=(o_hcpt - o_hmin + OHRES) MOD OHRES;
         
         -- CYCLE 2 -----------------------------------------
         -- Lines reordering
@@ -2401,6 +2504,7 @@ BEGIN
         o_hs<=o_hsv(5);
         o_vs<=o_vsv(5);
         o_de<=o_dev(5);
+        o_vbl<=o_end(5);
         o_r<=x"00";
         o_g<=x"00";
         o_b<=x"00";
@@ -2455,4 +2559,3 @@ BEGIN
   
   ----------------------------------------------------------------------------  
 END ARCHITECTURE rtl;
-
diff --git a/sys/audio_out.v b/sys/audio_out.v
index 545f3b9..0f748e0 100644
--- a/sys/audio_out.v
+++ b/sys/audio_out.v
@@ -1,7 +1,7 @@
 
 module audio_out
 #(
-	parameter CLK_RATE = 50000000
+	parameter CLK_RATE = 24576000
 )
 (
 	input        reset,
@@ -10,8 +10,24 @@ module audio_out
 	//0 - 48KHz, 1 - 96KHz
 	input        sample_rate,
 
-	input [15:0] left_in,
-	input [15:0] right_in,
+	input  [31:0] flt_rate,
+	input  [39:0] cx,
+	input   [7:0] cx0,
+	input   [7:0] cx1,
+	input   [7:0] cx2,
+	input  [23:0] cy0,
+	input  [23:0] cy1,
+	input  [23:0] cy2,
+
+	input  [4:0] att,
+	input  [1:0] mix,
+
+	input        is_signed,
+	input [15:0] core_l,
+	input [15:0] core_r,
+
+	input [15:0] alsa_l,
+	input [15:0] alsa_r,
 
 	// I2S
 	output       i2s_bclk,
@@ -38,11 +54,11 @@ reg mclk_ce;
 always @(posedge clk) begin
 	reg [31:0] cnt;
 
-	mclk_ce <= 0;
+	mclk_ce = 0;
 	cnt = cnt + real_ce;
 	if(cnt >= CLK_RATE) begin
 		cnt = cnt - CLK_RATE;
-		mclk_ce <= 1;
+		mclk_ce = 1;
 	end
 end
 
@@ -56,19 +72,6 @@ always @(posedge clk) begin
 	end
 end
 
-reg lpf_ce;
-always @(posedge clk) begin
-	integer div;
-	lpf_ce <= 0;
-	if(mclk_ce) begin
-		div <= div + 1;
-		if(div == FILTER_DIV) begin
-			div <= 0;
-			lpf_ce <= 1;
-		end
-	end
-end
-
 i2s i2s
 (
 	.reset(reset),
@@ -111,47 +114,183 @@ sigma_delta_dac #(15) sd_r
 	.DACout(dac_r)
 );
 
-wire [15:0] al, ar;
-lpf_aud lpf_l
-(
-   .CLK(clk),
-   .CE(lpf_ce),
-   .IDATA(left_in),
-   .ODATA(al)
-);
+reg sample_ce;
+always @(posedge clk) begin
+	reg [8:0] div = 0;
+	reg [1:0] add = 0;
 
-lpf_aud lpf_r
-(
-   .CLK(clk),
-   .CE(lpf_ce),
-   .IDATA(right_in),
-   .ODATA(ar)
-);
+	div <= div + add;
+	if(!div) begin
+		div <= 2'd1 << sample_rate;
+		add  <= 2'd1 << sample_rate;
+	end
 
-endmodule
-
-module lpf_aud
-(
-   input         CLK,
-   input         CE,
-   input  [15:0] IDATA,
-   output reg [15:0] ODATA
-);
-
-reg [511:0] acc;
-reg [20:0] sum;
-
-always @(*) begin
-	integer i;
-	sum = 0;
-	for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
+	sample_ce <= !div;
 end
 
-always @(posedge CLK) begin
-	if(CE) begin
-		acc <= {acc[495:0], IDATA};
-		ODATA <= sum[20:5];
+reg flt_ce;
+always @(posedge clk) begin
+	reg [31:0] cnt = 0;
+
+	flt_ce = 0;
+	cnt = cnt + {flt_rate[30:0],1'b0};
+	if(cnt >= CLK_RATE) begin
+		cnt = cnt - CLK_RATE;
+		flt_ce = 1;
 	end
 end
 
+reg [15:0] cl,cr;
+always @(posedge clk) begin
+	reg [15:0] cl1,cl2;
+	reg [15:0] cr1,cr2;
+
+	cl1 <= core_l; cl2 <= cl1;
+	if(cl2 == cl1) cl <= cl2;
+
+	cr1 <= core_r; cr2 <= cr1;
+	if(cr2 == cr1) cr <= cr2;
+end
+
+reg a_en1 = 0, a_en2 = 0;
+always @(posedge clk, posedge reset) begin
+	reg  [1:0] dly1 = 0;
+	reg [14:0] dly2 = 0;
+
+	if(reset) begin
+		dly1 <= 0;
+		dly2 <= 0;
+		a_en1 <= 0;
+		a_en2 <= 0;
+	end
+	else begin
+		if(flt_ce) begin
+			if(~&dly1) dly1 <= dly1 + 1'd1;
+			else a_en1 <= 1;
+		end
+
+		if(sample_ce) begin
+			if(!dly2[13+sample_rate]) dly2 <= dly2 + 1'd1;
+			else a_en2 <= 1;
+		end
+	end
+end
+
+wire [15:0] acl, acr;
+IIR_filter #(.use_params(0)) IIR_filter
+(
+	.clk(clk),
+	.reset(reset),
+
+	.ce(flt_ce & a_en1),
+	.sample_ce(sample_ce),
+
+	.cx(cx),
+	.cx0(cx0),
+	.cx1(cx1),
+	.cx2(cx2),
+	.cy0(cy0),
+	.cy1(cy1),
+	.cy2(cy2),
+
+	.input_l({~is_signed ^ cl[15], cl[14:0]}),
+	.input_r({~is_signed ^ cr[15], cr[14:0]}),
+	.output_l(acl),
+	.output_r(acr)
+);
+
+wire [15:0] adl;
+DC_blocker dcb_l
+(
+	.clk(clk),
+	.ce(sample_ce),
+	.sample_rate(sample_rate),
+	.mute(~a_en2),
+	.din(acl),
+	.dout(adl)
+);
+
+wire [15:0] adr;
+DC_blocker dcb_r
+(
+	.clk(clk),
+	.ce(sample_ce),
+	.sample_rate(sample_rate),
+	.mute(~a_en2),
+	.din(acr),
+	.dout(adr)
+);
+
+wire [15:0] al, audio_l_pre;
+aud_mix_top audmix_l
+(
+	.clk(clk),
+	.ce(sample_ce),
+	.att(att),
+	.mix(mix),
+
+	.core_audio(adl),
+	.pre_in(audio_r_pre),
+	.linux_audio(alsa_l),
+
+	.pre_out(audio_l_pre),
+	.out(al)
+);
+
+wire [15:0] ar, audio_r_pre;
+aud_mix_top audmix_r
+(
+	.clk(clk),
+	.ce(sample_ce),
+	.att(att),
+	.mix(mix),
+
+	.core_audio(adr),
+	.pre_in(audio_l_pre),
+	.linux_audio(alsa_r),
+
+	.pre_out(audio_r_pre),
+	.out(ar)
+);
+
+endmodule
+
+module aud_mix_top
+(
+	input             clk,
+	input             ce,
+
+	input       [4:0] att,
+	input       [1:0] mix,
+
+	input      [15:0] core_audio,
+	input      [15:0] linux_audio,
+	input      [15:0] pre_in,
+
+	output reg [15:0] pre_out = 0,
+	output reg [15:0] out = 0
+);
+
+reg signed [16:0] a1, a2, a3, a4;
+always @(posedge clk) if (ce) begin
+
+	a1 <= {core_audio[15],core_audio};
+	a2 <= a1 + {linux_audio[15],linux_audio};
+
+	pre_out <= a2[16:1];
+
+	case(mix)
+		0: a3 <= a2;
+		1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]);
+		2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]);
+		3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in};
+	endcase
+
+	if(att[4]) a4 <= 0;
+	else a4 <= a3 >>> att[3:0];
+
+	//clamping
+	out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0];
+end
+
 endmodule
diff --git a/sys/hdmi_config.sv b/sys/hdmi_config.sv
index 775a560..4a0a13d 100644
--- a/sys/hdmi_config.sv
+++ b/sys/hdmi_config.sv
@@ -111,32 +111,32 @@ wire [15:0] init_data[82] =
 
 	{8'h17, 8'b01100010},   // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
 
-	{8'h18, ypbpr ? 8'h88 : limited[0] ? 8'h8D : limited[1] ? 8'h8E : 8'h00},  // CSC Scaling Factors and Coefficients for RGB Full->Limited.
-	{8'h19, ypbpr ? 8'h2E : limited[0] ? 8'hBC : 8'hFE},                     // Taken from table in ADV7513 Programming Guide.
-	{8'h1A, ypbpr ? 8'h18 : 8'h00},         // CSC Channel A.
-	{8'h1B, ypbpr ? 8'h93 : 8'h00},
-	{8'h1C, ypbpr ? 8'h1F : 8'h00},
-	{8'h1D, ypbpr ? 8'h3F : 8'h00},
-	{8'h1E, ypbpr ? 8'h08 : 8'h01},
-	{8'h1F, 8'h00},
+	{8'h18, ypbpr ? 8'h86 : limited[0] ? 8'h8D : limited[1] ? 8'h8E : 8'h00},  // CSC Scaling Factors and Coefficients for RGB Full->Limited.
+	{8'h19, ypbpr ? 8'hDF : limited[0] ? 8'hBC : 8'hFE},                     // Taken from table in ADV7513 Programming Guide.
+	{8'h1A, ypbpr ? 8'h1A : 8'h00},         // CSC Channel A.
+	{8'h1B, ypbpr ? 8'h3F : 8'h00},
+	{8'h1C, ypbpr ? 8'h1E : 8'h00},
+	{8'h1D, ypbpr ? 8'hE2 : 8'h00},
+	{8'h1E, ypbpr ? 8'h07 : 8'h01},
+	{8'h1F, ypbpr ? 8'hE7 : 8'h00},
 
-	{8'h20, ypbpr ? 8'h03 : 8'h00},         // CSC Channel B.
-	{8'h21, ypbpr ? 8'h67 : 8'h00},
-	{8'h22, ypbpr ? 8'h0B : limited[0] ? 8'h0D : 8'h0E},
-	{8'h23, ypbpr ? 8'h71 : limited[0] ? 8'hBC : 8'hFE},
+	{8'h20, ypbpr ? 8'h04 : 8'h00},         // CSC Channel B.
+	{8'h21, ypbpr ? 8'h1C : 8'h00},
+	{8'h22, ypbpr ? 8'h08 : limited[0] ? 8'h0D : 8'h0E},
+	{8'h23, ypbpr ? 8'h11 : limited[0] ? 8'hBC : 8'hFE},
 	{8'h24, ypbpr ? 8'h01 : 8'h00},
-	{8'h25, ypbpr ? 8'h28 : 8'h00},
-	{8'h26, ypbpr ? 8'h00 : 8'h01},
+	{8'h25, ypbpr ? 8'h91 : 8'h00},
+	{8'h26, ypbpr ? 8'h01 : 8'h01},
 	{8'h27, 8'h00},
 
-	{8'h28, ypbpr ? 8'h1E : 8'h00},         // CSC Channel C.
-	{8'h29, ypbpr ? 8'h21 : 8'h00},
-	{8'h2A, ypbpr ? 8'h19 : 8'h00},
-	{8'h2B, ypbpr ? 8'hB2 : 8'h00},
-	{8'h2C, ypbpr ? 8'h08 : limited[0] ? 8'h0D : 8'h0E},
-	{8'h2D, ypbpr ? 8'h2D : limited[0] ? 8'hBC : 8'hFE},
-	{8'h2E, ypbpr ? 8'h08 : 8'h01},
-	{8'h2F, 8'h00},
+	{8'h28, ypbpr ? 8'h1D : 8'h00},         // CSC Channel C.
+	{8'h29, ypbpr ? 8'hAE : 8'h00},
+	{8'h2A, ypbpr ? 8'h1B : 8'h00},
+	{8'h2B, ypbpr ? 8'h73 : 8'h00},
+	{8'h2C, ypbpr ? 8'h06 : limited[0] ? 8'h0D : 8'h0E},
+	{8'h2D, ypbpr ? 8'hDF : limited[0] ? 8'hBC : 8'hFE},
+	{8'h2E, ypbpr ? 8'h07 : 8'h01},
+	{8'h2F, ypbpr ? 8'hE7 : 8'h00},
 
 	{8'h3B, 8'b0000_0000},	// Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
 
diff --git a/sys/hps_io.v b/sys/hps_io.v
index 1f37785..9431c95 100644
--- a/sys/hps_io.v
+++ b/sys/hps_io.v
@@ -105,10 +105,13 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
 
 	// ARM -> FPGA download
 	output reg        ioctl_download = 0, // signal indicating an active download
-	output reg  [7:0] ioctl_index,        // menu index used to upload the file
+	output reg [15:0] ioctl_index,        // menu index used to upload the file
 	output reg        ioctl_wr,
 	output reg [26:0] ioctl_addr,         // in WIDE mode address will be incremented by 2
 	output reg [DW:0] ioctl_dout,
+	output reg        ioctl_upload = 0,   // signal indicating an active upload
+	input      [DW:0] ioctl_din,
+	output reg        ioctl_rd,
 	output reg [31:0] ioctl_file_ext,
 	input             ioctl_wait,
 
@@ -123,7 +126,8 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
 	output reg [32:0] TIMESTAMP,
 
 	// UART flags
-	input      [15:0] uart_mode,
+	output reg  [7:0] uart_mode,
+	output reg [31:0] uart_speed,
 
 	// ps2 keyboard emulation
 	output            ps2_kbd_clk_out,
@@ -163,9 +167,9 @@ localparam DW = (WIDE) ? 15 : 7;
 localparam AW = (WIDE) ?  7 : 8;
 localparam VD = VDNUM-1;
 
-wire        io_strobe= HPS_BUS[33];
+wire        io_strobe= HPS_BUS[33];
 wire        io_enable= HPS_BUS[34];
-wire        fp_enable= HPS_BUS[35];
+wire        fp_enable= HPS_BUS[35];
 wire        io_wide  = (WIDE) ? 1'b1 : 1'b0;
 wire [15:0] io_din   = HPS_BUS[31:16];
 reg  [15:0] io_dout;
@@ -173,7 +177,7 @@ reg  [15:0] io_dout;
 assign HPS_BUS[37]   = ioctl_wait;
 assign HPS_BUS[36]   = clk_sys;
 assign HPS_BUS[32]   = io_wide;
-assign HPS_BUS[15:0] = EXT_BUS[32] ? EXT_BUS[15:0] : io_dout;
+assign HPS_BUS[15:0] = EXT_BUS[32] ? EXT_BUS[15:0] : fp_enable ? fp_dout : io_dout;
 
 reg [15:0] cfg;
 assign buttons = cfg[1:0];
@@ -234,7 +238,7 @@ wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[1
 
 reg [MAX_W:0] byte_cnt;
 
-always@(posedge clk_sys) begin
+always@(posedge clk_sys) begin : uio_block
 	reg [15:0] cmd;
 	reg  [2:0] b_wr;
 	reg  [3:0] stick_idx;
@@ -245,6 +249,8 @@ always@(posedge clk_sys) begin
 	reg        old_status_set = 0;
 	reg        old_info = 0;
 	reg  [7:0] info_n = 0;
+	reg [15:0] tmp1;
+	reg  [7:0] tmp2;
 
 	old_status_set <= status_set;
 	if(~old_status_set & status_set) begin
@@ -279,6 +285,7 @@ always@(posedge clk_sys) begin
 		sd_ack_conf <= 0;
 		io_dout <= 0;
 		ps2skip <= 0;
+		img_mounted <= 0;
 	end
 	else if(io_strobe) begin
 
@@ -297,10 +304,10 @@ always@(posedge clk_sys) begin
 				'h2F: io_dout <= 1;
 				'h32: io_dout <= gamma_bus[21];
 				'h36: begin io_dout <= info_n; info_n <= 0; end
+				'h39: io_dout <= 1;
 			endcase
 
 			sd_buff_addr <= 0;
-			img_mounted <= 0;
 			if(io_din == 5) ps2_key_raw <= 0;
 		end else begin
 
@@ -449,9 +456,6 @@ always@(posedge clk_sys) begin
 				//RTC
 				'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
 
-				//UART flags
-				'h28: io_dout <= uart_mode;
-
 				//status set
 				'h29: if(!byte_cnt[MAX_W:3]) begin
 							case(byte_cnt[2:0])
@@ -475,6 +479,15 @@ always@(posedge clk_sys) begin
 							{gamma_wr, gamma_value} <= {1'b1,io_din[7:0]};
 							if (byte_cnt[1:0] == 3) byte_cnt <= 1;
 						end
+
+				// UART
+				'h3b: if(!byte_cnt[MAX_W:2]) begin
+							case(byte_cnt[1:0])
+								1: tmp2 <= io_din[7:0];
+								2: tmp1 <= io_din;
+								3: {uart_speed, uart_mode} <= {io_din, tmp1, tmp2};
+							endcase
+						end
 			endcase
 		end
 	end
@@ -550,18 +563,20 @@ endgenerate
 
 ///////////////////////////////   DOWNLOADING   ///////////////////////////////
 
-localparam UIO_FILE_TX      = 8'h53;
-localparam UIO_FILE_TX_DAT  = 8'h54;
-localparam UIO_FILE_INDEX   = 8'h55;
-localparam UIO_FILE_INFO    = 8'h56;
+localparam FIO_FILE_TX      = 8'h53;
+localparam FIO_FILE_TX_DAT  = 8'h54;
+localparam FIO_FILE_INDEX   = 8'h55;
+localparam FIO_FILE_INFO    = 8'h56;
 
-always@(posedge clk_sys) begin
+reg [15:0] fp_dout;
+always@(posedge clk_sys) begin : fio_block
 	reg [15:0] cmd;
 	reg  [2:0] cnt;
 	reg        has_cmd;
 	reg [26:0] addr;
 	reg        wr;
 	
+	ioctl_rd <= 0;
 	ioctl_wr <= wr;
 	wr <= 0;
 
@@ -576,7 +591,7 @@ always@(posedge clk_sys) begin
 			end else begin
 
 				case(cmd)
-					UIO_FILE_INFO:
+					FIO_FILE_INFO:
 						if(~cnt[1]) begin
 							case(cnt)
 								0: ioctl_file_ext[31:16] <= io_din;
@@ -585,29 +600,54 @@ always@(posedge clk_sys) begin
 							cnt <= cnt + 1'd1;
 						end
 
-					UIO_FILE_INDEX:
+					FIO_FILE_INDEX:
 						begin
-							ioctl_index <= io_din[7:0];
+							ioctl_index <= io_din[15:0];
 						end
 
-					UIO_FILE_TX:
+					FIO_FILE_TX:
 						begin
-							if(io_din[7:0]) begin
-								addr <= 0;
-								ioctl_download <= 1;
-							end else begin
-								ioctl_addr <= addr;
-								ioctl_download <= 0;
-							end
+							cnt <= cnt + 1'd1;
+							case(cnt) 
+								0:	if(io_din[7:0] == 8'hAA) begin
+										ioctl_addr <= 0;
+										ioctl_upload <= 1;
+										ioctl_rd <= 1;
+									end
+									else if(io_din[7:0]) begin
+										addr <= 0;
+										ioctl_download <= 1;
+									end
+									else begin
+										if(ioctl_download) ioctl_addr <= addr;
+										ioctl_download <= 0;
+										ioctl_upload <= 0;
+									end
+
+								1: begin
+										ioctl_addr[15:0] <= io_din;
+										addr[15:0] <= io_din;
+									end
+
+								2: begin
+										ioctl_addr[26:16] <= io_din[10:0];
+										addr[26:16] <= io_din[10:0];
+									end
+							endcase
 						end
 
-					UIO_FILE_TX_DAT:
-						begin
+					FIO_FILE_TX_DAT:
+						if(ioctl_download) begin
 							ioctl_addr <= addr;
 							ioctl_dout <= io_din[DW:0];
 							wr   <= 1;
 							addr <= addr + (WIDE ? 2'd2 : 2'd1);
 						end
+						else begin
+							ioctl_addr <= ioctl_addr + (WIDE ? 2'd2 : 2'd1);
+							fp_dout <= ioctl_din;
+							ioctl_rd <= 1;
+						end
 				endcase
 			end
 		end
@@ -664,7 +704,7 @@ always@(posedge clk_sys) begin
 
 	tx_empty <= ((wptr == rptr) && (tx_state == 0));
 
-	if(we) begin
+	if(we && !has_data) begin
 		fifo[wptr] <= wdata;
 		wptr <= wptr + 1'd1;
 	end
@@ -704,6 +744,8 @@ always@(posedge clk_sys) begin
 						ps2_dat_out <= 1;
 						has_data <= 1;
 						rx_state <= 0;
+						rptr     <= 0;
+						wptr     <= 0;
 					end
 			endcase
 		end else begin
diff --git a/sys/iir_filter.v b/sys/iir_filter.v
new file mode 100644
index 0000000..b8bcf4f
--- /dev/null
+++ b/sys/iir_filter.v
@@ -0,0 +1,213 @@
+
+//  3-tap IIR filter for 2 channels. 
+//  Copyright (C) 2020 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+
+//
+//  Can be converted to 2-tap (coeff_x2 = 0, coeff_y2 = 0) or 1-tap (coeff_x1,2 = 0, coeff_y1,2 = 0)
+//
+module IIR_filter
+#(
+	parameter use_params = 1,                     // set to 1 to use following parameters, 0 for input port variables.
+	parameter stereo   =  1,                      // 0 for mono (input_l)
+
+	parameter coeff_x  =  0.00000774701983513660, // Base gain value for X. Float. Range: 0.0 ... 0.999(9)
+	parameter coeff_x0 =  3,                      // Gain scale factor for X0. Integer. Range -7 ... +7
+	parameter coeff_x1 =  3,                      // Gain scale factor for X1. Integer. Range -7 ... +7
+	parameter coeff_x2 =  1,                      // Gain scale factor for X2. Integer. Range -7 ... +7
+	parameter coeff_y0 = -2.96438150626551080000, // Coefficient for Y0. Float. Range -3.999(9) ... 3.999(9)
+	parameter coeff_y1 =  2.92939452735121100000, // Coefficient for Y1. Float. Range -3.999(9) ... 3.999(9)
+	parameter coeff_y2 = -0.96500747158831091000  // Coefficient for Y2. Float. Range -3.999(9) ... 3.999(9)
+)
+(
+	input         clk,
+	input         reset,
+
+	input         ce,        // must be double of calculated rate for stereo!
+	input         sample_ce, // desired output sample rate
+
+	input  [39:0] cx,
+	input   [7:0] cx0,
+	input   [7:0] cx1,
+	input   [7:0] cx2,
+	input  [23:0] cy0,
+	input  [23:0] cy1,
+	input  [23:0] cy2,
+
+	input  [15:0] input_l,  input_r,  // signed samples
+	output [15:0] output_l, output_r  // signed samples
+);
+
+localparam  [39:0] pcoeff_x  = coeff_x  * 40'h8000000000;
+localparam  [31:0] pcoeff_y0 = coeff_y0 * 24'h200000;
+localparam  [31:0] pcoeff_y1 = coeff_y1 * 24'h200000;
+localparam  [31:0] pcoeff_y2 = coeff_y2 * 24'h200000;
+
+wire [39:0] vcoeff    = use_params ? pcoeff_x        : cx;
+wire [23:0] vcoeff_y0 = use_params ? pcoeff_y0[23:0] : cy0;
+wire [23:0] vcoeff_y1 = use_params ? pcoeff_y1[23:0] : cy1;
+wire [23:0] vcoeff_y2 = use_params ? pcoeff_y2[23:0] : cy2;
+
+wire [59:0] inp_mul = $signed(inp) * $signed(vcoeff);
+
+wire [39:0] x = inp_mul[59:20];
+wire [39:0] y = x + tap0;
+
+wire [39:0] tap0;
+iir_filter_tap iir_tap_0
+(
+	.clk(clk),
+	.reset(reset),
+	.ce(ce),
+	.ch(ch),
+	.cx(use_params ? coeff_x0[7:0] : cx0),
+	.cy(vcoeff_y0),
+	.x(x),
+	.y(y),
+	.z(tap1),
+	.tap(tap0)
+);
+
+wire [39:0] tap1;
+iir_filter_tap iir_tap_1
+(
+	.clk(clk),
+	.reset(reset),
+	.ce(ce),
+	.ch(ch),
+	.cx(use_params ? coeff_x1[7:0] : cx1),
+	.cy(vcoeff_y1),
+	.x(x),
+	.y(y),
+	.z(tap2),
+	.tap(tap1)
+);
+
+wire [39:0] tap2;
+iir_filter_tap iir_tap_2
+(
+	.clk(clk),
+	.reset(reset),
+	.ce(ce),
+	.ch(ch),
+	.cx(use_params ? coeff_x2[7:0] : cx2),
+	.cy(vcoeff_y2),
+	.x(x),
+	.y(y),
+	.z(0),
+	.tap(tap2)
+);
+
+wire [15:0] y_clamp = (~y[39] & |y[38:35]) ? 16'h7FFF : (y[39] & ~&y[38:35]) ? 16'h8000 : y[35:20];
+
+reg        ch = 0;
+reg [15:0] out_l, out_r, out_m;
+reg [15:0] inp, inp_m;
+always @(posedge clk) if (ce) begin
+	if(!stereo) begin
+		ch    <= 0;
+		inp   <= input_l;
+		out_l <= y_clamp;
+		out_r <= y_clamp;
+	end
+	else begin
+		ch <= ~ch;
+		if(ch) begin
+			out_m <= y_clamp;
+			inp   <= inp_m;
+		end
+		else begin
+			out_l <= out_m;
+			out_r <= y_clamp;
+			inp   <= input_l;
+			inp_m <= input_r;
+		end
+	end
+end
+
+reg [31:0] out;
+always @(posedge clk) if (sample_ce) out <= {out_l, out_r};
+
+assign {output_l, output_r} = out;
+
+endmodule
+
+module iir_filter_tap
+(
+	input         clk,
+	input         reset,
+
+	input         ce,
+	input         ch,
+
+	input   [7:0] cx,
+	input  [23:0] cy,
+
+	input  [39:0] x,
+	input  [39:0] y,
+	input  [39:0] z,
+	output [39:0] tap
+);
+
+wire signed [60:0] y_mul = $signed(y[36:0]) * $signed(cy);
+
+function [39:0] x_mul;
+	input [39:0] x;
+begin
+	x_mul = 0;
+	if(cx[0]) x_mul =  x_mul + {{4{x[39]}}, x[39:4]};
+	if(cx[1]) x_mul =  x_mul + {{3{x[39]}}, x[39:3]};
+	if(cx[2]) x_mul =  x_mul + {{2{x[39]}}, x[39:2]};
+	if(cx[7]) x_mul = ~x_mul; //cheap NEG
+end
+endfunction
+
+(* ramstyle = "logic" *) reg [39:0] intreg[2];
+always @(posedge clk, posedge reset) begin
+	if(reset) {intreg[0],intreg[1]} <= 80'd0;
+	else if(ce) intreg[ch] <= x_mul(x) - y_mul[60:21] + z;
+end
+
+assign tap = intreg[ch];
+
+endmodule
+
+// simplified IIR 1-tap.
+module DC_blocker
+(
+	input         clk,
+	input         ce, // 48/96 KHz
+	input         mute,
+
+	input         sample_rate,
+	input  [15:0] din,
+	output [15:0] dout
+);
+
+wire [39:0] x  = {din[15], din, 23'd0};
+wire [39:0] x0 = x - (sample_rate ? {{11{x[39]}}, x[39:11]} : {{10{x[39]}}, x[39:10]});
+wire [39:0] y1 = y - (sample_rate ? {{10{y[39]}}, y[39:10]} : {{09{y[39]}}, y[39:09]});
+wire [39:0] y0 = x0 - x1 + y1;
+
+reg  [39:0] x1, y;
+always @(posedge clk) if(ce) begin
+	x1 <= x0;
+	y  <= ^y0[39:38] ? {{2{y0[39]}},{38{y0[38]}}} : y0;
+end
+
+assign dout = mute ? 16'd0 : y[38:23];
+
+endmodule
diff --git a/sys/mt32pi.sv b/sys/mt32pi.sv
new file mode 100644
index 0000000..6704807
--- /dev/null
+++ b/sys/mt32pi.sv
@@ -0,0 +1,283 @@
+//
+// Communication module to MT32-pi (external MIDI emulator on RPi)
+// (C) 2020 Sorgelig, Kitrinx
+//
+// https://github.com/dwhinham/mt32-pi
+//
+
+module mt32pi
+(
+	input             CLK_AUDIO,
+
+	input             CLK_VIDEO,
+	input             CE_PIXEL,
+	input             VGA_VS,
+	input             VGA_DE,
+
+	input       [6:0] USER_IN,
+	output      [6:0] USER_OUT,
+
+	input             reset,
+	input             midi_tx,
+	output            midi_rx,
+
+	output reg [15:0] mt32_i2s_r,
+	output reg [15:0] mt32_i2s_l,
+
+	output reg        mt32_available,
+
+	input             mt32_mode_req,
+	input       [1:0] mt32_rom_req,
+	input       [7:0] mt32_sf_req,
+
+	output reg  [7:0] mt32_mode,
+	output reg  [7:0] mt32_rom,
+	output reg  [7:0] mt32_sf,
+	output reg        mt32_newmode,
+
+	output reg        mt32_lcd_en,
+	output reg        mt32_lcd_pix,
+	output reg        mt32_lcd_update
+);
+
+//
+// Pin | USB Name | Signal
+// ----+----------+--------------
+// 0   | D+       | I/O I2C_SDA / RX (midi in)
+// 1   | D-       | O   TX (midi out)
+// 2   | TX-      | I   I2S_WS (1 == right)
+// 3   | GND_d    | I   I2C_SCL
+// 4   | RX+      | I   I2S_BCLK
+// 5   | RX-      | I   I2S_DAT
+// 6   | TX+      | -   none
+//
+
+assign USER_OUT[0]   = sda_out;
+assign USER_OUT[1]   = midi_tx;
+assign USER_OUT[6:2] = '1;
+
+
+//
+// crossed/straight cable selection
+//
+
+generate
+	genvar i;
+	for(i = 0; i<2; i++) begin : clk_rate
+		wire clk_in = i ? USER_IN[6] : USER_IN[4];
+		reg [4:0] cnt;
+		always @(posedge CLK_AUDIO) begin : clkr
+			reg       clk_sr, clk, old_clk;
+			reg [4:0] cnt_tmp;
+
+			clk_sr <= clk_in;
+			if (clk_sr == clk_in) clk <= clk_sr;
+
+			if(~&cnt_tmp) cnt_tmp <= cnt_tmp + 1'd1;
+			else cnt <= '1;
+
+			old_clk <= clk;
+			if(~old_clk & clk) begin
+				cnt <= cnt_tmp;
+				cnt_tmp <= 0;
+			end
+		end
+	end
+	
+	reg crossed;
+	always @(posedge CLK_AUDIO) crossed <= (clk_rate[0].cnt <= clk_rate[1].cnt);
+endgenerate
+
+wire   i2s_ws   = crossed ? USER_IN[2] : USER_IN[5];
+wire   i2s_data = crossed ? USER_IN[5] : USER_IN[2];
+wire   i2s_bclk = crossed ? USER_IN[4] : USER_IN[6];
+assign midi_rx  = ~mt32_available ? USER_IN[0] : crossed ? USER_IN[6] : USER_IN[4];
+
+
+//
+// i2s receiver
+//
+
+always @(posedge CLK_AUDIO) begin : i2s_proc
+	reg [15:0] i2s_buf = 0;
+	reg  [4:0] i2s_cnt = 0;
+	reg        clk_sr;
+	reg        i2s_clk = 0;
+	reg        old_clk, old_ws;
+	reg        i2s_next = 0;
+
+	// Debounce clock
+	clk_sr <= i2s_bclk;
+	if (clk_sr == i2s_bclk) i2s_clk <= clk_sr;
+
+	// Latch data and ws on rising edge
+	old_clk <= i2s_clk;
+	if (i2s_clk && ~old_clk) begin
+
+		if (~i2s_cnt[4]) begin
+			i2s_cnt <= i2s_cnt + 1'd1;
+			i2s_buf[~i2s_cnt[3:0]] <= i2s_data;
+		end
+
+		// Word Select will change 1 clock before the new word starts
+		old_ws <= i2s_ws;
+		if (old_ws != i2s_ws) i2s_next <= 1;
+	end
+
+	if (i2s_next) begin
+		i2s_next <= 0;
+		i2s_cnt <= 0;
+		i2s_buf <= 0;
+
+		if (i2s_ws) mt32_i2s_l <= i2s_buf;
+		else        mt32_i2s_r <= i2s_buf;
+	end
+	
+	if (reset) begin
+		i2s_buf    <= 0;
+		mt32_i2s_l <= 0;
+		mt32_i2s_r <= 0;
+	end
+end
+
+
+//
+// i2c slave
+//
+
+reg        sda_out;
+reg  [7:0] lcd_data[1024];
+reg        lcd_sz;
+
+reg        reset_r  = 0;
+wire [7:0] mode_req = reset_r ? 8'hA0 : mt32_mode_req ? 8'hA2 : 8'hA1;
+wire [7:0] rom_req  = {6'd0, mt32_rom_req};
+
+always @(posedge CLK_AUDIO) begin : i2c_slave
+	reg        sda_sr, scl_sr;
+	reg        old_sda, old_scl;
+	reg        sda, scl;
+	reg  [7:0] tmp;
+	reg  [3:0] cnt = 0;
+	reg [10:0] bcnt = 0;
+	reg        ack;
+	reg        i2c_rw;
+	reg        disp, dispdata;
+	reg  [2:0] div;
+	reg        old_reset;
+	
+	old_reset <= reset;
+	if(old_reset & ~reset) sda_out <= 1;
+
+	div <= div + 1'd1;
+	if(!div) begin
+		sda_sr <= USER_IN[0];
+		if(sda_sr == USER_IN[0]) sda <= sda_sr;
+		old_sda <= sda;
+
+		scl_sr <= USER_IN[3];
+		if(scl_sr == USER_IN[3]) scl <= scl_sr;
+		old_scl <= scl;
+
+		//start
+		if(old_scl & scl & old_sda & ~sda) begin
+			cnt <= 9;
+			bcnt <= 0;
+			ack <= 0;
+			i2c_rw <= 0;
+			disp <= 0;
+			dispdata <= 0;
+		end
+
+		//stop
+		if(old_scl & scl & ~old_sda & sda) begin
+			cnt <= 0;
+			if(dispdata) begin
+				lcd_sz <= ~bcnt[9];
+				mt32_lcd_update <= ~mt32_lcd_update;
+			end
+		end
+
+		//data latch
+		if(~old_scl && scl && cnt) begin
+			tmp <= {tmp[6:0], sda};
+			cnt <= cnt - 1'd1;
+		end
+
+		if(!cnt) sda_out <= 1;
+
+		//data set
+		if(old_scl && ~scl) begin
+			sda_out <= 1;
+			if(cnt == 1) begin
+				if(!bcnt) begin
+					if(tmp[7:1] == 'h45 || tmp[7:1] == 'h3c) begin
+						disp <= (tmp[7:1] == 'h3c);
+						sda_out <= 0;
+						mt32_available <= 1;
+						ack <= 1;
+						i2c_rw <= tmp[0];
+						bcnt <= bcnt + 1'd1;
+						cnt <= 10;
+					end
+					else begin
+						// wrong address, stop
+						cnt <= 0;
+					end
+				end
+				else if(ack) begin
+					if(~i2c_rw) begin
+						if(disp) begin
+							if(bcnt == 1) dispdata <= (tmp[7:6] == 2'b01);
+							else if(dispdata) lcd_data[bcnt[9:0] - 2'd2] <= tmp;
+						end
+						else begin
+							if(bcnt == 1) mt32_mode <= tmp;
+							if(bcnt == 2) mt32_rom  <= tmp;
+							if(bcnt == 3) mt32_sf   <= tmp;
+							if(bcnt == 3) mt32_newmode <= ~mt32_newmode;
+						end
+					end
+					if(~&bcnt) bcnt <= bcnt + 1'd1;
+					sda_out <= 0;
+					cnt <= 10;
+				end
+			end
+			else if(i2c_rw && ack && cnt && ~disp) begin
+				if(bcnt == 1) sda_out <= mode_req[cnt[2:0] - 2'd2];
+				if(bcnt == 2) sda_out <= rom_req[cnt[2:0] - 2'd2];
+				if(bcnt == 3) sda_out <= mt32_sf_req[cnt[2:0] - 2'd2];
+				if(bcnt == 3) reset_r <= 0;
+			end
+		end
+	end
+
+	if(reset) begin
+		reset_r <= 1;
+		mt32_available <= 0;
+	end
+end
+
+always @(posedge CLK_VIDEO) begin
+	reg old_de, old_vs;
+	reg [7:0] hcnt;
+	reg [6:0] vcnt;
+	reg [7:0] sh;
+
+	if(CE_PIXEL) begin
+		old_de <= VGA_DE;
+		old_vs <= VGA_VS;
+
+		if(~&hcnt) hcnt <= hcnt + 1'd1;
+		sh <= (sh << 1) | (~old_de & VGA_DE);
+		if(sh[7]) hcnt <= 0;
+
+		if(old_de & ~VGA_DE & ~&vcnt) vcnt <= vcnt + 1'd1;
+		if(~old_vs & VGA_VS) vcnt <= 0;
+
+		mt32_lcd_en  <= mt32_available & ~hcnt[7] && (lcd_sz ? !vcnt[6] : !vcnt[6:5]);
+		mt32_lcd_pix <= lcd_data[{vcnt[5:3],hcnt[6:0]}][vcnt[2:0]];
+	end
+end
+
+endmodule
diff --git a/sys/pll_audio.13.qip b/sys/pll_audio.13.qip
new file mode 100644
index 0000000..e987931
--- /dev/null
+++ b/sys/pll_audio.13.qip
@@ -0,0 +1,17 @@
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "13.1"
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"]
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+
+set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"]
+set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"]
+
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
+
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "13.1"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
diff --git a/sys/pll_audio.qip b/sys/pll_audio.qip
new file mode 100644
index 0000000..abb013b
--- /dev/null
+++ b/sys/pll_audio.qip
@@ -0,0 +1,337 @@
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_VERSION "17.0"
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_audio" -name MISC_FILE [file join $::quartus(qip_path) "pll_audio.cmp"]
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlv"
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA=="
+set_global_assignment -entity "pll_audio" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_NAME "cGxsX2F1ZGlvXzAwMDI="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_VERSION "MTcuMA=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjQuNTc2::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MTUyODMyMTE2Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTc=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjQuNTc2MDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw5LDgsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDE3Ljc5MiBNSHosMTUyODMyMTE2Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio.v"]
+set_global_assignment -library "pll_audio" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.v"]
+set_global_assignment -library "pll_audio" -name QIP_FILE [file join $::quartus(qip_path) "pll_audio/pll_audio_0002.qip"]
+
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_VERSION "17.0"
+set_global_assignment -entity "pll_audio_0002" -library "pll_audio" -name IP_TOOL_ENV "mwpim"
diff --git a/sys/pll_audio.v b/sys/pll_audio.v
new file mode 100644
index 0000000..185a94c
--- /dev/null
+++ b/sys/pll_audio.v
@@ -0,0 +1,252 @@
+// megafunction wizard: %Altera PLL v17.0%
+// GENERATION: XML
+// pll_audio.v
+
+// Generated using ACDS version 17.0 602
+
+`timescale 1 ps / 1 ps
+module pll_audio (
+		input  wire  refclk,   //  refclk.clk
+		input  wire  rst,      //   reset.reset
+		output wire  outclk_0  // outclk0.clk
+	);
+
+	pll_audio_0002 pll_audio_inst (
+		.refclk   (refclk),   //  refclk.clk
+		.rst      (rst),      //   reset.reset
+		.outclk_0 (outclk_0), // outclk0.clk
+		.locked   ()          // (terminated)
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2020 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_pll" version="17.0" >
+// Retrieval info: 	<generic name="debug_print_output" value="false" />
+// Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
+// Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
+// Retrieval info: 	<generic name="gui_device_speed_grade" value="1" />
+// Retrieval info: 	<generic name="gui_pll_mode" value="Fractional-N PLL" />
+// Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
+// Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
+// Retrieval info: 	<generic name="gui_operation_mode" value="direct" />
+// Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
+// Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
+// Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
+// Retrieval info: 	<generic name="gui_use_locked" value="false" />
+// Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
+// Retrieval info: 	<generic name="gui_number_of_clocks" value="1" />
+// Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
+// Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
+// Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="24.576" />
+// Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg1" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency3" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency4" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency5" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency6" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
+// Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
+// Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
+// Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+// Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
+// Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
+// Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
+// Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
+// Retrieval info: 	<generic name="gui_pll_auto_reset" value="On" />
+// Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
+// Retrieval info: 	<generic name="gui_en_reconf" value="false" />
+// Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
+// Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
+// Retrieval info: 	<generic name="gui_phout_division" value="1" />
+// Retrieval info: 	<generic name="gui_mif_generate" value="false" />
+// Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
+// Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
+// Retrieval info: 	<generic name="gui_dps_num" value="1" />
+// Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
+// Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
+// Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
+// Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+// Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
+// Retrieval info: 	<generic name="gui_active_clk" value="false" />
+// Retrieval info: 	<generic name="gui_clk_bad" value="false" />
+// Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
+// Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
+// Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
+// Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+// Retrieval info: </instance>
+// IPFS_FILES : pll_audio.vo
+// RELATED_FILES: pll_audio.v, pll_audio_0002.v
diff --git a/sys/pll_audio/pll_audio_0002.qip b/sys/pll_audio/pll_audio_0002.qip
new file mode 100644
index 0000000..dadd4b8
--- /dev/null
+++ b/sys/pll_audio/pll_audio_0002.qip
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_audio_0002*|altera_pll:altera_pll_i*|*"
diff --git a/sys/pll_audio/pll_audio_0002.v b/sys/pll_audio/pll_audio_0002.v
new file mode 100644
index 0000000..7898914
--- /dev/null
+++ b/sys/pll_audio/pll_audio_0002.v
@@ -0,0 +1,87 @@
+`timescale 1ns/10ps
+module  pll_audio_0002(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("true"),
+		.reference_clock_frequency("50.0 MHz"),
+		.operation_mode("direct"),
+		.number_of_clocks(1),
+		.output_clock_frequency0("24.576000 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("0 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("0 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
diff --git a/sys/pll_q13.qip b/sys/pll_q13.qip
index 7018c53..13a7ed4 100644
--- a/sys/pll_q13.qip
+++ b/sys/pll_q13.qip
@@ -1,5 +1,6 @@
 set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll.13.qip ]
 set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_hdmi.13.qip ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_audio.13.qip ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll_cfg.v ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ]
diff --git a/sys/pll_q17.qip b/sys/pll_q17.qip
index 5bc92e0..85cc84b 100644
--- a/sys/pll_q17.qip
+++ b/sys/pll_q17.qip
@@ -1,3 +1,4 @@
 set_global_assignment -name QIP_FILE           rtl/pll.qip
 set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_hdmi.qip ]
+set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_audio.qip ]
 set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_cfg.qip ]
diff --git a/sys/sd_card.v b/sys/sd_card.sv
similarity index 81%
rename from sys/sd_card.v
rename to sys/sd_card.sv
index 3761a7e..a2aad7e 100644
--- a/sys/sd_card.v
+++ b/sys/sd_card.sv
@@ -25,7 +25,7 @@
 // Made module syncrhronous. Total code refactoring. (Sorgelig)
 // clk_spi must be at least 4 x sck for proper work.
 
-module sd_card
+module sd_card #(parameter WIDE = 0)
 (
 	input         clk_sys,
 	input         reset,
@@ -38,9 +38,9 @@ module sd_card
 	input         sd_ack,
 	input         sd_ack_conf,
 
-	input   [8:0] sd_buff_addr,
-	input   [7:0] sd_buff_dout,
-	output  [7:0] sd_buff_din,
+	input  [AW:0] sd_buff_addr,
+	input  [DW:0] sd_buff_dout,
+	output [DW:0] sd_buff_din,
 	input         sd_buff_wr,
 
 	// SPI interface
@@ -52,6 +52,9 @@ module sd_card
 	output reg    miso
 );
 
+localparam AW = WIDE ?  7 : 8;
+localparam DW = WIDE ? 15 : 7;
+
 assign sd_lba = sdhc ? lba : {9'd0, lba[31:9]};
 
 wire[31:0] OCR = { 1'b1, sdhc, 30'd0 };  // bit30 = 1 -> high capaciry card (sdhc) // bit31 = 0 -> card power up finished
@@ -75,7 +78,7 @@ localparam WR_STATE_RECV_CRC1  = 4;
 localparam WR_STATE_SEND_DRESP = 5;
 localparam WR_STATE_BUSY       = 6;
 
-sdbuf buffer
+sdbuf #(WIDE) buffer
 (
 	.clock_a(clk_sys),
 	.address_a(sd_buff_addr),
@@ -90,7 +93,7 @@ sdbuf buffer
 	.q_b(buffer_dout)
 );
 
-sdbuf conf
+sdbuf #(WIDE) conf
 (
 	.clock_a(clk_sys),
 	.address_a(sd_buff_addr),
@@ -344,7 +347,14 @@ always @(posedge clk_spi) begin
 					'h4a: reply <= 0;    // ok
 
 					// CMD12: STOP_TRANSMISSION 
-					'h4c: reply <= 0;    // ok
+					'h4c: reply <= 0;    // ok
+					
+					// CMD13: SEND_STATUS 
+					'h4d: begin
+					        reply <= 'h00;    // ok 
+							  reply0 <='h00;
+							  reply_len <= 1;
+					      end
 
 					// CMD16: SET_BLOCKLEN
 					'h50: begin
@@ -358,6 +368,8 @@ always @(posedge clk_spi) begin
 
 					// CMD18: READ_MULTIPLE
 					'h52: reply <= 0;    // ok
+					// ACMD23:  SET_WR_BLK_ERASE_COUNT
+					'h57: reply <= 0;     //ok
 
 					// CMD24: WRITE_BLOCK
 					'h58,
@@ -467,72 +479,59 @@ end
 
 endmodule
 
-module sdbuf
+module sdbuf #(parameter WIDE)
 (
-	input	       clock_a,
-	input	       clock_b,
-	input	 [8:0] address_a,
-	input	 [8:0] address_b,
-	input	 [7:0] data_a,
-	input	 [7:0] data_b,
-	input	       wren_a,
-	input	       wren_b,
-	output [7:0] q_a,
-	output [7:0] q_b
+	input             clock_a,
+	input      [AW:0] address_a,
+	input      [DW:0] data_a, 
+	input             wren_a,
+	output reg [DW:0] q_a,
+
+	input             clock_b,
+	input       [8:0] address_b,
+	input       [7:0] data_b, 
+	input             wren_b,
+	output reg  [7:0] q_b
 );
 
-altsyncram	altsyncram_component
-(
-	.address_a (address_a),
-	.address_b (address_b),
-	.clock0 (clock_a),
-	.clock1 (clock_b),
-	.data_a (data_a),
-	.data_b (data_b),
-	.wren_a (wren_a),
-	.wren_b (wren_b),
-	.q_a (q_a),
-	.q_b (q_b),
-	.aclr0 (1'b0),
-	.aclr1 (1'b0),
-	.addressstall_a (1'b0),
-	.addressstall_b (1'b0),
-	.byteena_a (1'b1),
-	.byteena_b (1'b1),
-	.clocken0 (1'b1),
-	.clocken1 (1'b1),
-	.clocken2 (1'b1),
-	.clocken3 (1'b1),
-	.eccstatus (),
-	.rden_a (1'b1),
-	.rden_b (1'b1)
-);
-defparam
-	altsyncram_component.address_reg_b = "CLOCK1",
-	altsyncram_component.clock_enable_input_a = "BYPASS",
-	altsyncram_component.clock_enable_input_b = "BYPASS",
-	altsyncram_component.clock_enable_output_a = "BYPASS",
-	altsyncram_component.clock_enable_output_b = "BYPASS",
-	altsyncram_component.indata_reg_b = "CLOCK1",
-	altsyncram_component.intended_device_family = "Cyclone V",
-	altsyncram_component.lpm_type = "altsyncram",
-	altsyncram_component.numwords_a = 512,
-	altsyncram_component.numwords_b = 512,
-	altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
-	altsyncram_component.outdata_aclr_a = "NONE",
-	altsyncram_component.outdata_aclr_b = "NONE",
-	altsyncram_component.outdata_reg_a = "UNREGISTERED",
-	altsyncram_component.outdata_reg_b = "UNREGISTERED",
-	altsyncram_component.power_up_uninitialized = "FALSE",
-	altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
-	altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
-	altsyncram_component.widthad_a = 9,
-	altsyncram_component.widthad_b = 9,
-	altsyncram_component.width_a = 8,
-	altsyncram_component.width_b = 8,
-	altsyncram_component.width_byteena_a = 1,
-	altsyncram_component.width_byteena_b = 1,
-	altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
+localparam AW = WIDE ?  7 : 8;
+localparam DW = WIDE ? 15 : 7;
+
+always@(posedge clock_a) begin
+	if(wren_a) begin
+		ram[address_a] <= data_a;
+		q_a <= data_a;
+	end
+	else begin
+		q_a <= ram[address_a];
+	end
+end
+
+generate
+	if(WIDE) begin
+		reg [1:0][7:0] ram[1<<8];
+		always@(posedge clock_b) begin
+			if(wren_b) begin
+				ram[address_b[8:1]][address_b[0]] <= data_b;
+				q_b <= data_b;
+			end
+			else begin
+				q_b <= ram[address_b[8:1]][address_b[0]];
+			end
+		end
+	end
+	else begin
+		reg [7:0] ram[1<<9];
+		always@(posedge clock_b) begin
+			if(wren_b) begin
+				ram[address_b] <= data_b;
+				q_b <= data_b;
+			end
+			else begin
+				q_b <= ram[address_b];
+			end
+		end
+	end
+endgenerate
 
 endmodule
-
diff --git a/sys/spdif.v b/sys/spdif.v
index d50c2da..db5027c 100644
--- a/sys/spdif.v
+++ b/sys/spdif.v
@@ -67,6 +67,8 @@ reg         spdif_out_q;
 
 reg [5:0]   parity_count_q;
 
+reg         channel_status_bit;
+
 //-----------------------------------------------------------------
 // Subframe Counter
 //-----------------------------------------------------------------
@@ -142,7 +144,7 @@ assign subframe_w[28] = 1'b0; // Valid
 assign subframe_w[29] = 1'b0;
 
 // Timeslots 30 = Channel status bit
-assign subframe_w[30] = 1'b0;
+assign subframe_w[30] = channel_status_bit ; //was constant 1'b0 enabling copy-bit;
 
 // Timeslots 31 = Even Parity bit (31:4)
 assign subframe_w[31] = 1'b0;
@@ -150,9 +152,9 @@ assign subframe_w[31] = 1'b0;
 //-----------------------------------------------------------------
 // Preamble
 //-----------------------------------------------------------------
-localparam PREAMBLE_Z = 8'b00010111;
-localparam PREAMBLE_Y = 8'b00100111;
-localparam PREAMBLE_X = 8'b01000111;
+localparam PREAMBLE_Z = 8'b00010111; // "B" channel A data at start of block
+localparam PREAMBLE_Y = 8'b00100111; // "W" channel B data
+localparam PREAMBLE_X = 8'b01000111; // "M" channel A data not at start of block
 
 reg [7:0] preamble_r;
 
@@ -168,6 +170,15 @@ begin
     // Left Channel (but not start of block)?
     else
         preamble_r = PREAMBLE_X; // X(M)
+
+    if (subframe_count_q[8:1] == 8'd2) // frame 2 => subframes 4 and 5 => 0 = copy inhibited, 1 = copy permitted
+        channel_status_bit = 1'b1;
+    else if (subframe_count_q[8:1] == 8'd15) // frame 15 => 0 = no indication, 1 = original media
+        channel_status_bit = 1'b1;
+    else if (subframe_count_q[8:1] == 8'd25) // frame 24 to 27 => sample frequency, 0100 = 48kHz, 0000 = 44kHz (l2r)
+        channel_status_bit = 1'b1;
+    else
+        channel_status_bit = 1'b0; // everything else defaults to 0        
 end
 
 always @ (posedge rst_i or posedge clk_i )
diff --git a/sys/sys.qip b/sys/sys.qip
index 3a594df..ac810d5 100644
--- a/sys/sys.qip
+++ b/sys/sys.qip
@@ -17,11 +17,13 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) a
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) i2s.v ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) spdif.v ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) audio_out.v ]
+set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) iir_filter.v ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ltc2308.sv ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sigma_delta_dac.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mt32pi.sv ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]
 set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
-set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) sd_card.v ]
+set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sd_card.sv ]
 set_global_assignment -name VERILOG_FILE       [file join $::quartus(qip_path) hps_io.v ]
diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc
index 67619ac..46c761d 100644
--- a/sys/sys_top.sdc
+++ b/sys/sys_top.sdc
@@ -12,6 +12,8 @@ derive_clock_uncertainty
 set_clock_groups -exclusive \
    -group [get_clocks { *|pll|pll_inst|altera_pll_i|*[*].*|divclk}] \
    -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
+   -group [get_clocks { pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}] \
+   -group [get_clocks { spi_sck}] \
    -group [get_clocks { *|h2f_user0_clk}] \
    -group [get_clocks { FPGA_CLK1_50 }] \
    -group [get_clocks { FPGA_CLK2_50 }] \
@@ -19,33 +21,42 @@ set_clock_groups -exclusive \
 
 set_false_path -from [get_ports {KEY*}]
 set_false_path -from [get_ports {BTN_*}]
-set_false_path -to [get_ports {LED_*}]
-set_false_path -to [get_ports {VGA_*}]
-set_false_path -to [get_ports {AUDIO_SPDIF}]
-set_false_path -to [get_ports {AUDIO_L}]
-set_false_path -to [get_ports {AUDIO_R}]
-set_false_path -to {cfg[*]}
+set_false_path -to   [get_ports {LED_*}]
+set_false_path -to   [get_ports {VGA_*}]
+set_false_path -to   [get_ports {AUDIO_SPDIF}]
+set_false_path -to   [get_ports {AUDIO_L}]
+set_false_path -to   [get_ports {AUDIO_R}]
+set_false_path -to   {cfg[*]}
 set_false_path -from {cfg[*]}
 set_false_path -from {VSET[*]}
-set_false_path -to {wcalc[*] hcalc[*]}
-set_false_path -to {width[*] height[*]}
+set_false_path -to   {wcalc[*] hcalc[*]}
+set_false_path -to   {width[*] height[*]}
 
 set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
 set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
-set_false_path -to {*_osd|v_cnt*}
-set_false_path -to {*_osd|v_osd_start*}
-set_false_path -to {*_osd|v_info_start*}
-set_false_path -to {*_osd|h_osd_start*}
+
+set_false_path -to   {*_osd|v_cnt*}
+set_false_path -to   {*_osd|v_osd_start*}
+set_false_path -to   {*_osd|v_info_start*}
+set_false_path -to   {*_osd|h_osd_start*}
 set_false_path -from {*_osd|v_osd_start*}
 set_false_path -from {*_osd|v_info_start*}
 set_false_path -from {*_osd|h_osd_start*}
 set_false_path -from {*_osd|rot*}
 set_false_path -from {*_osd|dsp_width*}
-set_false_path -to {*_osd|half}
+set_false_path -to   {*_osd|half}
 
 set_false_path -to   {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
 set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
-set_false_path -to   {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] FB_HMIN[*] FB_HMAX[*] FB_VMIN[*] FB_VMAX[*]}
-set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] FB_HMIN[*] FB_HMAX[*] FB_VMIN[*] FB_VMAX[*]}
+set_false_path -to   {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}
+set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] LFB_HMIN[*] LFB_HMAX[*] LFB_VMIN[*] LFB_VMAX[*]}
 set_false_path -to   {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
 set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
+set_false_path -from {aflt_* acx* acy* areset* arc*}
+set_false_path -from {vs_line*}
+
+set_false_path -from {ascal|o_ihsize*}
+set_false_path -from {ascal|o_ivsize*}
+set_false_path -from {ascal|o_format*}
+set_false_path -from {ascal|o_hdown}
+set_false_path -from {ascal|o_vdown}
diff --git a/sys/sys_top.v b/sys/sys_top.v
index c8ef6f7..5e31b0d 100644
--- a/sys/sys_top.v
+++ b/sys/sys_top.v
@@ -24,6 +24,13 @@
 	`define USE_SDRAM
 `endif
 
+`ifndef USE_DDRAM
+	`ifdef USE_FB
+		`define USE_DDRAM
+	`endif
+`endif
+
+
 module sys_top
 (
 	/////////// CLOCK //////////
@@ -236,7 +243,10 @@ wire        io_ss0 = gp_outr[18];
 wire        io_ss1 = gp_outr[19];
 wire        io_ss2 = gp_outr[20];
 
+`ifndef DEBUG_NOHDMI
 wire io_osd_hdmi = io_ss1 & ~io_ss0;
+`endif
+
 wire io_fpga     = ~io_ss1 & io_ss0;
 wire io_uio      = ~io_ss1 & io_ss2;
 
@@ -276,11 +286,16 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp
 
 reg [15:0] cfg;
 
-reg        cfg_got      = 0;
 reg        cfg_set      = 0;
-wire       vga_fb       = cfg[12];
+wire       vga_fb       = cfg[12] | vga_force_scaler;
 wire [1:0] hdmi_limited = {cfg[11],cfg[8]};
+
+`ifdef DEBUG_NOHDMI
+wire       direct_video = 1;
+`else
 wire       direct_video = cfg[10];
+`endif
+
 wire       dvi_mode     = cfg[7];
 wire       audio_96k    = cfg[6];
 wire       csync_en     = cfg[3];
@@ -288,7 +303,7 @@ wire       ypbpr_en     = cfg[5];
 wire       io_osd_vga   = io_ss1 & ~io_ss2;
 `ifndef DUAL_SDRAM
 	wire    sog          = cfg[9];
-	wire    vga_scaler   = cfg[2];
+	wire    vga_scaler   = cfg[2] | vga_force_scaler;
 `endif
 
 reg        cfg_custom_t = 0;
@@ -301,7 +316,7 @@ reg  [6:0] coef_addr;
 reg  [8:0] coef_data;
 reg        coef_wr = 0;
 
-wire [7:0] ARX, ARY;
+wire[11:0] ARX, ARY;
 reg [11:0] VSET = 0, HSET = 0;
 reg        FREESCALE = 0;
 reg  [2:0] scaler_flt;
@@ -312,12 +327,28 @@ reg        vs_wait = 0;
 reg [11:0] vs_line = 0;
 
 reg        scaler_out = 0;
+
+reg [31:0] aflt_rate = 7056000;
+reg [39:0] acx  = 4258969;
+reg  [7:0] acx0 = 3;
+reg  [7:0] acx1 = 3;
+reg  [7:0] acx2 = 1;
+reg [23:0] acy0 = -24'd6216759;
+reg [23:0] acy1 =  24'd6143386;
+reg [23:0] acy2 = -24'd2023767;
+reg        areset = 0;
+reg [11:0] arc1x = 0;
+reg [11:0] arc1y = 0;
+reg [11:0] arc2x = 0;
+reg [11:0] arc2y = 0;
+
 always@(posedge clk_sys) begin
 	reg  [7:0] cmd;
 	reg        has_cmd;
 	reg        old_strobe;
 	reg  [7:0] cnt = 0;
 	reg        vs_d0,vs_d1,vs_d2;
+	reg  [4:0] acx_att;
 
 	old_strobe <= io_strobe;
 	coef_wr <= 0;
@@ -325,6 +356,9 @@ always@(posedge clk_sys) begin
 	if(~io_uio) begin
 		has_cmd <= 0;
 		cmd <= 0;
+		areset <= 0;
+		acx_att <= 0;
+		acx <= acx >> acx_att;
 	end
 	else
 	if(~old_strobe & io_strobe) begin
@@ -333,6 +367,17 @@ always@(posedge clk_sys) begin
 			cmd <= io_din[7:0];
 			cnt <= 0;
 			if(io_din[7:0] == 'h30) vs_wait <= 1;
+			if(io_din[7:0] == 'h39) begin
+				aflt_rate <= 7056000;
+				acx  <= 4258969;
+				acx0 <= 3;
+				acx1 <= 3;
+				acx2 <= 1;
+				acy0 <= -24'd6216759;
+				acy1 <=  24'd6143386;
+				acy2 <= -24'd2023767;
+				areset <= 1;
+			end
 		end
 		else begin
 			if(cmd == 1) begin
@@ -354,6 +399,7 @@ always@(posedge clk_sys) begin
 						6: if(VS     != io_din[11:0]) VS     <= io_din[11:0];
 						7: if(VBP    != io_din[11:0]) VBP    <= io_din[11:0];
 					endcase
+`ifndef DEBUG_NOHDMI
 					if(cnt == 1) begin
 						cfg_custom_p1 <= 0;
 						cfg_custom_p2 <= 0;
@@ -369,20 +415,21 @@ always@(posedge clk_sys) begin
 						cnt[2:0] <= 3'b100;
 					end
 					if(cnt == 8) {lowlat,cfg_dis} <= io_din[15:14];
+`endif
 				end
 			end
 			if(cmd == 'h2F) begin
 				cnt <= cnt + 1'd1;
 				case(cnt[3:0])
-					0: {FB_EN,FB_FLT,FB_FMT} <= {io_din[15], io_din[14], io_din[5:0]};
-					1: FB_BASE[15:0]  <= io_din[15:0];
-					2: FB_BASE[31:16] <= io_din[15:0];
-					3: FB_WIDTH       <= io_din[11:0];
-					4: FB_HEIGHT      <= io_din[11:0];
-					5: FB_HMIN        <= io_din[11:0];
-					6: FB_HMAX        <= io_din[11:0];
-					7: FB_VMIN        <= io_din[11:0];
-					8: FB_VMAX        <= io_din[11:0];
+					0: {LFB_EN,LFB_FLT,LFB_FMT} <= {io_din[15], io_din[14], io_din[5:0]};
+					1: LFB_BASE[15:0]  <= io_din[15:0];
+					2: LFB_BASE[31:16] <= io_din[15:0];
+					3: LFB_WIDTH       <= io_din[11:0];
+					4: LFB_HEIGHT      <= io_din[11:0];
+					5: LFB_HMIN        <= io_din[11:0];
+					6: LFB_HMAX        <= io_din[11:0];
+					7: LFB_VMIN        <= io_din[11:0];
+					8: LFB_VMAX        <= io_din[11:0];
 				endcase
 			end
 			if(cmd == 'h25) {led_overtake, led_state} <= io_din;
@@ -392,6 +439,35 @@ always@(posedge clk_sys) begin
 			if(cmd == 'h2B) scaler_flt <= io_din[2:0];
 			if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]};
 			if(cmd == 'h38) vs_line <= io_din[11:0];
+			if(cmd == 'h39) begin
+				cnt <= cnt + 1'd1;
+				case(cnt[3:0])
+					 0: acx_att          <= io_din[4:0];
+					 1: aflt_rate[15:0]  <= io_din;
+					 2: aflt_rate[31:16] <= io_din;
+					 3: acx[15:0]        <= io_din;
+					 4: acx[31:16]       <= io_din;
+					 5: acx[39:32]       <= io_din[7:0];
+					 6: acx0             <= io_din[7:0];
+					 7: acx1             <= io_din[7:0];
+					 8: acx2             <= io_din[7:0];
+					 9: acy0[15:0]       <= io_din;
+					10: acy0[23:16]      <= io_din[7:0];
+					11: acy1[15:0]       <= io_din;
+					12: acy1[23:16]      <= io_din[7:0];
+					13: acy2[15:0]       <= io_din;
+					14: acy2[23:16]      <= io_din[7:0];
+				endcase
+			end
+			if(cmd == 'h3A) begin
+				cnt <= cnt + 1'd1;
+				case(cnt[3:0])
+					 0: arc1x <= io_din[11:0];
+					 1: arc1y <= io_din[11:0];
+					 2: arc2x <= io_din[11:0];
+					 3: arc2y <= io_din[11:0];
+				endcase
+			end
 		end
 	end
 
@@ -402,16 +478,6 @@ always@(posedge clk_sys) begin
 	if(~vs_d2 & vs_d1) vs_wait <= 0;
 end
 
-always @(posedge clk_sys) begin
-	reg vsd, vsd2;
-	if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set;
-	else begin
-		vsd  <= HDMI_TX_VS;
-		vsd2 <= vsd;
-		if(~vsd2 & vsd) cfg_got <= cfg_set;
-	end
-end
-
 cyclonev_hps_interface_peripheral_uart uart
 (
 	.ri(0)
@@ -465,14 +531,11 @@ always @(posedge FPGA_CLK2_50) begin
 	resetd2 <= resetd;
 end
 
-wire clk_100m;
-wire clk_hdmi  = hdmi_clk_out;
-wire clk_audio = FPGA_CLK3_50;
-wire clk_pal   = FPGA_CLK3_50;
-
 ////////////////////  SYSTEM MEMORY & SCALER  /////////////////////////
 
 wire reset;
+wire clk_100m;
+
 sysmem_lite sysmem
 (
 	//Reset/Clock
@@ -562,6 +625,8 @@ ddr_svc ddr_svc
 	.ch1_ready(pal_wr)
 );
 
+wire clk_pal = clk_audio;
+
 
 wire  [27:0] vbuf_address;
 wire   [7:0] vbuf_burstcount;
@@ -574,11 +639,17 @@ wire  [15:0] vbuf_byteenable;
 wire         vbuf_write;
 
 wire  [23:0] hdmi_data;
-wire         hdmi_vs, hdmi_hs, hdmi_de;
+wire         hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl;
+
+`ifndef DEBUG_NOHDMI
+wire clk_hdmi  = hdmi_clk_out;
 
 ascal 
 #(
 	.RAMBASE(32'h20000000),
+`ifndef USE_FB	
+	.PALETTE2("false"),
+`endif
 	.N_DW(128),
 	.N_AW(28)
 )
@@ -611,6 +682,7 @@ ascal
 	.o_hs     (hdmi_hs),
 	.o_vs     (hdmi_vs),
 	.o_de     (hdmi_de),
+	.o_vbl    (hdmi_vbl),
 	.o_lltune (lltune),
 	.htotal   (WIDTH + HFP + HBP + HS),
 	.hsstart  (WIDTH + HFP),
@@ -625,22 +697,32 @@ ascal
 	.vmin     (vmin),
 	.vmax     (vmax),
 
-	.mode     ({~lowlat,FB_EN ? FB_FLT : |scaler_flt,2'b00}),
+	.mode     ({~lowlat,LFB_EN ? LFB_FLT : |scaler_flt,2'b00}),
 	.poly_clk (clk_sys),
 	.poly_a   (coef_addr),
 	.poly_dw  (coef_data),
 	.poly_wr  (coef_wr),
 
-	.pal_clk  (clk_pal),
-	.pal_dw   (pal_d),
-	.pal_a    (pal_a),
-	.pal_wr   (pal_wr),
+	.pal1_clk (clk_pal),
+	.pal1_dw  (pal_d),
+	.pal1_a   (pal_a),
+	.pal1_wr  (pal_wr),
+
+`ifdef USE_FB	
+	.pal2_clk (fb_pal_clk),
+	.pal2_dw  (fb_pal_d),
+	.pal2_dr  (fb_pal_q),
+	.pal2_a   (fb_pal_a),
+	.pal2_wr  (fb_pal_wr),
+	.pal_n    (fb_en),
+`endif
 
 	.o_fb_ena         (FB_EN),
 	.o_fb_hsize       (FB_WIDTH),
 	.o_fb_vsize       (FB_HEIGHT),
 	.o_fb_format      (FB_FMT),
 	.o_fb_base        (FB_BASE),
+	.o_fb_stride      (FB_STRIDE),
 
 	.avl_clk          (clk_100m),
 	.avl_waitrequest  (vbuf_waitrequest),
@@ -653,17 +735,48 @@ ascal
 	.avl_read         (vbuf_read),
 	.avl_byteenable   (vbuf_byteenable)
 );
+`endif
+
+reg        LFB_EN     = 0;
+reg        LFB_FLT    = 0;
+reg  [5:0] LFB_FMT    = 0;
+reg [11:0] LFB_WIDTH  = 0;
+reg [11:0] LFB_HEIGHT = 0;
+reg [11:0] LFB_HMIN   = 0;
+reg [11:0] LFB_HMAX   = 0;
+reg [11:0] LFB_VMIN   = 0;
+reg [11:0] LFB_VMAX   = 0;
+reg [31:0] LFB_BASE   = 0;
 
 reg        FB_EN     = 0;
-reg        FB_FLT    = 0;
 reg  [5:0] FB_FMT    = 0;
 reg [11:0] FB_WIDTH  = 0;
 reg [11:0] FB_HEIGHT = 0;
-reg [11:0] FB_HMIN   = 0;
-reg [11:0] FB_HMAX   = 0;
-reg [11:0] FB_VMIN   = 0;
-reg [11:0] FB_VMAX   = 0;
 reg [31:0] FB_BASE   = 0;
+reg [13:0] FB_STRIDE = 0;
+
+always @(posedge clk_sys) begin
+	FB_EN <= LFB_EN | fb_en;
+	if(LFB_EN) begin
+		FB_FMT    <= LFB_FMT;
+		FB_WIDTH  <= LFB_WIDTH;
+		FB_HEIGHT <= LFB_HEIGHT;
+		FB_BASE   <= LFB_BASE;
+		FB_STRIDE <= 0;
+	end
+	else begin
+		FB_FMT    <= fb_fmt;
+		FB_WIDTH  <= fb_width;
+		FB_HEIGHT <= fb_height;
+		FB_BASE   <= fb_base;
+		FB_STRIDE <= fb_stride;
+	end
+end
+
+`ifdef USE_FB
+reg fb_vbl;
+always @(posedge clk_vid) fb_vbl <= hdmi_vbl;
+`endif
 
 reg [11:0] hmin;
 reg [11:0] hmax;
@@ -678,31 +791,54 @@ always @(posedge clk_vid) begin
 	reg [11:0] videoh;
 	reg [11:0] height;
 	reg [11:0] width;
+	reg [11:0] arx;
+	reg [11:0] ary;
 
 	height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT;
 	width  <= (HSET && (HSET < WIDTH))  ? HSET : WIDTH;
+	
+	if(!ARY) begin
+		if(ARX == 1) begin
+			arx <= arc1x;
+			ary <= arc1y;
+		end
+		else if(ARX == 2) begin
+			arx <= arc2x;
+			ary <= arc2y;
+		end
+		else begin
+			arx <= 0;
+			ary <= 0;
+		end
+	end
+	else begin
+		arx <= ARX;
+		ary <= ARY;
+	end
 
 	state <= state + 1'd1;
 	case(state)
-		0: if(FB_EN) begin
-				hmin <= FB_HMIN;
-				vmin <= FB_VMIN;
-				hmax <= FB_HMAX;
-				vmax <= FB_VMAX;
+		0: if(LFB_EN) begin
+				hmin <= LFB_HMIN;
+				vmin <= LFB_VMIN;
+				hmax <= LFB_HMAX;
+				vmax <= LFB_VMAX;
 				state<= 0;
 			end
-			else if(ARX && ARY && !FREESCALE) begin
-				wcalc <= (height*ARX)/ARY;
-				hcalc <= (width*ARY)/ARX;
-			end
-			else begin
+			else if(FREESCALE || !arx || !ary) begin
 				wcalc <= width;
 				hcalc <= height;
 			end
+			else begin
+				wcalc <= (height*arx)/ary;
+				hcalc <= (width*ary)/arx;
+			end
+
 		6: begin
 				videow <= (wcalc > width)  ? width  : wcalc[11:0];
 				videoh <= (hcalc > height) ? height : hcalc[11:0];
 			end
+
 		7: begin
 				hmin <= ((WIDTH  - videow)>>1);
 				hmax <= ((WIDTH  - videow)>>1) + videow - 1'd1;
@@ -712,8 +848,8 @@ always @(posedge clk_vid) begin
 	endcase
 end
 
+`ifndef DEBUG_NOHDMI
 wire [15:0] lltune;
-
 pll_hdmi_adj pll_hdmi_adj
 (
 	.clk(FPGA_CLK1_50),
@@ -731,6 +867,9 @@ pll_hdmi_adj pll_hdmi_adj
 	.o_address(cfg_address),
 	.o_writedata(cfg_data)
 );
+`else
+	assign led_locked = 0;
+`endif
 
 wire [63:0] pal_data;
 wire [47:0] pal_d = {pal_data[55:32], pal_data[23:0]};
@@ -740,17 +879,19 @@ wire        pal_wr;
 reg  [28:0] pal_addr;
 reg         pal_req = 0;
 always @(posedge clk_pal) begin
-	reg old_vs;
+	reg old_vs1, old_vs2;
 
-	pal_addr <= FB_BASE[31:3] - 29'd512;
+	pal_addr <= LFB_BASE[31:3] - 29'd512;
 
-	old_vs <= hdmi_vs;
-	if(~old_vs & hdmi_vs & ~FB_FMT[2] & FB_FMT[1] & FB_FMT[0] & FB_EN) pal_req <= ~pal_req;
+	old_vs1 <= hdmi_vs;
+	old_vs2 <= old_vs1;
+	
+	if(~old_vs2 & old_vs1 & ~FB_FMT[2] & FB_FMT[1] & FB_FMT[0] & FB_EN) pal_req <= ~pal_req;
 end
 
 
 /////////////////////////  HDMI output  /////////////////////////////////
-
+`ifndef DEBUG_NOHDMI
 wire hdmi_clk_out;
 pll_hdmi pll_hdmi
 (
@@ -760,6 +901,7 @@ pll_hdmi pll_hdmi
 	.reconfig_from_pll(reconfig_from_pll),
 	.outclk_0(hdmi_clk_out)
 );
+`endif
 
 //1920x1080@60 PCLK=148.5MHz CEA
 reg  [11:0] WIDTH  = 1920;
@@ -781,6 +923,7 @@ reg         adj_write;
 reg   [5:0] adj_address;
 reg  [31:0] adj_data;
 
+`ifndef DEBUG_NOHDMI
 pll_cfg pll_cfg
 (
 	.mgmt_clk(FPGA_CLK1_50),
@@ -795,8 +938,18 @@ pll_cfg pll_cfg
 	.reconfig_from_pll(reconfig_from_pll)
 );
 
-reg cfg_ready = 0;
+reg cfg_got = 0;
+always @(posedge clk_sys) begin
+	reg vsd, vsd2;
+	if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set;
+	else begin
+		vsd  <= HDMI_TX_VS;
+		vsd2 <= vsd;
+		if(~vsd2 & vsd) cfg_got <= cfg_set;
+	end
+end
 
+reg cfg_ready = 0;
 always @(posedge FPGA_CLK1_50) begin
 	reg gotd = 0, gotd2 = 0;
 	reg custd = 0, custd2 = 0;
@@ -825,6 +978,12 @@ always @(posedge FPGA_CLK1_50) begin
 	if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1;
 end
 
+`else
+
+wire cfg_ready = 1;
+
+`endif
+
 wire hdmi_config_done;
 hdmi_config hdmi_config
 (
@@ -841,14 +1000,27 @@ hdmi_config hdmi_config
 	.ypbpr(ypbpr_en & direct_video)
 );
 
+`ifndef DEBUG_NOHDMI
 wire [23:0] hdmi_data_sl;
 wire        hdmi_de_sl, hdmi_vs_sl, hdmi_hs_sl;
+
+`ifdef USE_FB
+reg dis_output;
+always @(posedge clk_hdmi) begin
+	reg dis;
+	dis <= fb_force_blank;
+	dis_output <= dis;
+end
+`else
+wire dis_output = 0;
+`endif
+
 scanlines #(1) HDMI_scanlines
 (
 	.clk(clk_hdmi),
 
 	.scanlines(scanlines),
-	.din(hdmi_data),
+	.din(dis_output ? 24'd0 : hdmi_data),
 	.hs_in(hdmi_hs),
 	.vs_in(hdmi_vs),
 	.de_in(hdmi_de),
@@ -861,6 +1033,7 @@ scanlines #(1) HDMI_scanlines
 
 wire [23:0] hdmi_data_osd;
 wire        hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd;
+
 osd hdmi_osd
 (
 	.clk_sys(clk_sys),
@@ -884,6 +1057,7 @@ osd hdmi_osd
 	.osd_status(osd_status)
 `endif
 );
+`endif
 
 wire hdmi_cs_osd;
 csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd);
@@ -930,12 +1104,16 @@ always @(posedge clk_vid) begin
 end
 
 wire hdmi_tx_clk;
+`ifndef DEBUG_NOHDMI
 cyclonev_clkselect hdmi_clk_sw
 ( 
 	.clkselect({1'b1, ~vga_fb & direct_video}),
 	.inclk({clk_vid, hdmi_clk_out, 2'b00}),
 	.outclk(hdmi_tx_clk)
 );
+`else
+assign hdmi_tx_clk = clk_vid;
+`endif
 
 altddio_out
 #(
@@ -1032,21 +1210,29 @@ wire vga_cs_osd;
 csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
 
 `ifndef DUAL_SDRAM
-	wire [23:0] vga_o;
-	vga_out vga_out
-	(
-		.ypbpr_full(0),
-		.ypbpr_en(ypbpr_en),
-		.dout(vga_o),
-		.din((vga_fb | vga_scaler) ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd)
-	);
-
 	wire vs1 = (vga_fb | vga_scaler) ? hdmi_vs_osd : vga_vs_osd;
 	wire hs1 = (vga_fb | vga_scaler) ? hdmi_hs_osd : vga_hs_osd;
 	wire cs1 = (vga_fb | vga_scaler) ? hdmi_cs_osd : vga_cs_osd;
 
-	assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ      : csync_en ? 1'b1 : ~vs1;
-	assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ      : csync_en ? ~cs1 : ~hs1;
+	wire [23:0] vga_o;
+	wire vga_hs, vga_vs, vga_cs;
+	vga_out vga_out
+	(
+		.clk(clk_vid),
+		.ypbpr_full(0),
+		.ypbpr_en(ypbpr_en),
+		.hsync(hs1),
+		.vsync(vs1),
+		.csync(cs1),
+		.dout(vga_o),
+		.din((vga_fb | vga_scaler) ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd),
+		.hsync_o(vga_hs),
+		.vsync_o(vga_vs),
+		.csync_o(vga_cs)
+	);
+
+	assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ      : csync_en ? 1'b1    : ~vga_vs;
+	assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ      : csync_en ? ~vga_cs : ~vga_hs;
 	assign VGA_R  = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[23:18];
 	assign VGA_G  = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[15:10];
 	assign VGA_B  = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[7:2];
@@ -1082,65 +1268,60 @@ end
 assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ;
 
 `ifndef DUAL_SDRAM
-	wire anl,anr;
+	wire analog_l, analog_r;
 
 	assign AUDIO_SPDIF = SW[3] ? 1'bZ : SW[0] ? HDMI_LRCLK : spdif;
-	assign AUDIO_R     = SW[3] ? 1'bZ : SW[0] ? HDMI_I2S   : anr;
-	assign AUDIO_L     = SW[3] ? 1'bZ : SW[0] ? HDMI_SCLK  : anl;
+	assign AUDIO_R     = SW[3] ? 1'bZ : SW[0] ? HDMI_I2S   : analog_r;
+	assign AUDIO_L     = SW[3] ? 1'bZ : SW[0] ? HDMI_SCLK  : analog_l;
 `endif
 
-assign HDMI_MCLK = 0;
+assign HDMI_MCLK = clk_audio;
+wire clk_audio;
 
-wire [15:0] audio_l, audio_l_pre;
-aud_mix_top audmix_l
+pll_audio pll_audio
 (
-	.clk(clk_audio),
-	.att(vol_att),
-	.mix(audio_mix),
-	.is_signed(audio_s),
-
-	.core_audio(audio_ls),
-	.pre_in(audio_r_pre),
-	.linux_audio(alsa_l),
-
-	.pre_out(audio_l_pre),
-	.out(audio_l)
-);
-
-wire [15:0] audio_r, audio_r_pre;
-aud_mix_top audmix_r
-(
-	.clk(clk_audio),
-	.att(vol_att),
-	.mix(audio_mix),
-	.is_signed(audio_s),
-
-	.core_audio(audio_rs),
-	.pre_in(audio_l_pre),
-	.linux_audio(alsa_r),
-
-	.pre_out(audio_r_pre),
-	.out(audio_r)
+	.refclk(FPGA_CLK3_50),
+	.rst(0),
+	.outclk_0(clk_audio)
 );
 
 wire spdif;
 audio_out audio_out
 (
-	.reset(reset),
+	.reset(reset | areset),
 	.clk(clk_audio),
+
+	.att(vol_att),
+	.mix(audio_mix),
 	.sample_rate(audio_96k),
-	.left_in(audio_l),
-	.right_in(audio_r),
+
+	.flt_rate(aflt_rate),
+	.cx(acx),
+	.cx0(acx0),
+	.cx1(acx1),
+	.cx2(acx2),
+	.cy0(acy0),
+	.cy1(acy1),
+	.cy2(acy2),
+
+	.is_signed(audio_s),
+	.core_l(audio_l),
+	.core_r(audio_r),
+
+	.alsa_l(alsa_l),
+	.alsa_r(alsa_r),
+
 	.i2s_bclk(HDMI_SCLK),
 	.i2s_lrclk(HDMI_LRCLK),
 	.i2s_data(HDMI_I2S),
 `ifndef DUAL_SDRAM
-	.dac_l(anl),
-	.dac_r(anr),
+	.dac_l(analog_l),
+	.dac_r(analog_r),
 `endif
 	.spdif(spdif)
 );
 
+
 wire [28:0] alsa_address;
 wire [63:0] alsa_readdata;
 wire        alsa_ready;
@@ -1168,7 +1349,6 @@ alsa alsa
 	.pcm_r(alsa_r)
 );
 
-
 ////////////////  User I/O (USB 3.0 connector) /////////////////////////
 
 assign USER_IO[0] =                       !user_out[0]  ? 1'b0 : 1'bZ;
@@ -1191,7 +1371,7 @@ assign user_in[6] =         USER_IO[6];
 ///////////////////  User module connection ////////////////////////////
 
 wire        clk_sys;
-wire [15:0] audio_ls, audio_rs;
+wire [15:0] audio_l, audio_r;
 wire        audio_s;
 wire  [1:0] audio_mix;
 wire  [1:0] scanlines;
@@ -1199,6 +1379,7 @@ wire  [7:0] r_out, g_out, b_out, hr_out, hg_out, hb_out;
 wire        vs_fix, hs_fix, de_emu, vs_emu, hs_emu, f1;
 wire        hvs_fix, hhs_fix, hde_emu;
 wire        clk_vid, ce_pix, clk_ihdmi, ce_hpix;
+wire        vga_force_scaler;
 
 `ifdef USE_DDRAM
 	wire        ram_clk;
@@ -1227,24 +1408,20 @@ wire  [6:0] user_out, user_in;
 assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = {39'bZ};
 `endif
 
-`ifdef ARCADE_SYS
-	wire hvs_emu, hhs_emu;
-	sync_fix hdmi_sync_v(clk_ihdmi, hvs_emu, hvs_fix);
-	sync_fix hdmi_sync_h(clk_ihdmi, hhs_emu, hhs_fix);
+assign clk_ihdmi= clk_vid;
+assign ce_hpix  = ce_pix;
+assign hr_out   = r_out;
+assign hg_out   = g_out;
+assign hb_out   = b_out;
+assign hhs_fix  = hs_fix;
+assign hvs_fix  = vs_fix;
+assign hde_emu  = de_emu;
 
+`ifdef ARCADE_SYS
 	assign audio_mix = 0;
 	assign {ADC_SCK, ADC_SDI, ADC_CONVST} = 0;
 	assign btn = 0;
 `else
-	assign clk_ihdmi= clk_vid;
-	assign ce_hpix  = ce_pix;
-	assign hr_out   = r_out;
-	assign hg_out   = g_out;
-	assign hb_out   = b_out;
-	assign hhs_fix  = hs_fix;
-	assign hvs_fix  = vs_fix;
-	assign hde_emu  = de_emu;
-
 	wire uart_dtr;
 	wire uart_dsr;
 	wire uart_cts;
@@ -1254,6 +1431,28 @@ assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQM
 	wire osd_status;
 `endif
 
+wire        fb_en;
+wire  [4:0] fb_fmt;
+wire [11:0] fb_width;
+wire [11:0] fb_height;
+wire [31:0] fb_base;
+wire [13:0] fb_stride;
+
+`ifdef USE_FB
+	wire        fb_pal_clk;
+	wire  [7:0] fb_pal_a;
+	wire [23:0] fb_pal_d;
+	wire [23:0] fb_pal_q;
+	wire        fb_pal_wr;
+	wire        fb_force_blank;
+`else
+	assign fb_en = 0;
+	assign fb_fmt = 0;
+	assign fb_width = 0;
+	assign fb_height = 0;
+	assign fb_base = 0;
+	assign fb_stride = 0;
+`endif
 
 emu emu
 (
@@ -1268,40 +1467,46 @@ emu emu
 	.VGA_VS(vs_emu),
 	.VGA_DE(de_emu),
 	.VGA_F1(f1),
+	.VGA_SCALER(vga_force_scaler),
 
-`ifdef ARCADE_SYS
-	.VGA_CLK(clk_vid),
-	.VGA_CE(ce_pix),
-	.HDMI_CLK(clk_ihdmi),
-	.HDMI_CE(ce_hpix),
-	.HDMI_R(hr_out),
-	.HDMI_G(hg_out),
-	.HDMI_B(hb_out),
-	.HDMI_HS(hhs_emu),
-	.HDMI_VS(hvs_emu),
-	.HDMI_DE(hde_emu),
-	.HDMI_SL(scanlines),
-	.HDMI_ARX(ARX),
-	.HDMI_ARY(ARY),
-`else
 	.CLK_VIDEO(clk_vid),
 	.CE_PIXEL(ce_pix),
 	.VGA_SL(scanlines),
 	.VIDEO_ARX(ARX),
 	.VIDEO_ARY(ARY),
 
-	.AUDIO_MIX(audio_mix),
-	.ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}),
+`ifdef USE_FB
+	.FB_EN(fb_en),
+	.FB_FORMAT(fb_fmt),
+	.FB_WIDTH(fb_width),
+	.FB_HEIGHT(fb_height),
+	.FB_BASE(fb_base),
+	.FB_STRIDE(fb_stride),
+	.FB_VBL(fb_vbl),
+	.FB_LL(lowlat),
+	.FB_FORCE_BLANK(fb_force_blank),
+
+	.FB_PAL_CLK (fb_pal_clk),
+	.FB_PAL_ADDR(fb_pal_a),
+	.FB_PAL_DOUT(fb_pal_d),
+	.FB_PAL_DIN (fb_pal_q),
+	.FB_PAL_WR  (fb_pal_wr),
 `endif
 
 	.LED_USER(led_user),
 	.LED_POWER(led_power),
 	.LED_DISK(led_disk),
 
-	.AUDIO_L(audio_ls),
-	.AUDIO_R(audio_rs),
+	.CLK_AUDIO(clk_audio),
+	.AUDIO_L(audio_l),
+	.AUDIO_R(audio_r),
 	.AUDIO_S(audio_s),
 
+`ifndef ARCADE_SYS
+	.AUDIO_MIX(audio_mix),
+	.ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}),
+`endif
+
 `ifdef USE_DDRAM
 	.DDRAM_CLK(ram_clk),
 	.DDRAM_ADDR(ram_address),
@@ -1401,56 +1606,6 @@ endmodule
 
 /////////////////////////////////////////////////////////////////////
 
-module aud_mix_top
-(
-	input             clk,
-
-	input       [4:0] att,
-	input       [1:0] mix,
-	input             is_signed,
-
-	input      [15:0] core_audio,
-	input      [15:0] linux_audio,
-	input      [15:0] pre_in,
-
-	output reg [15:0] pre_out,
-	output reg [15:0] out
-);
-
-reg [15:0] ca;
-always @(posedge clk) begin
-	reg [15:0] d1,d2,d3;
-
-	d1 <= core_audio; d2<=d1; d3<=d2;
-	if(d2 == d3) ca <= d2;
-end
-
-always @(posedge clk) begin
-	reg signed [16:0] a1, a2, a3, a4;
-
-	a1 <= is_signed ? {ca[15],ca} : {2'b00,ca[15:1]};
-	a2 <= a1 + {linux_audio[15],linux_audio};
-
-	pre_out <= a2[16:1];
-
-	case(mix)
-		0: a3 <= a2;
-		1: a3 <= $signed(a2) - $signed(a2[16:3]) + $signed(pre_in[15:2]);
-		2: a3 <= $signed(a2) - $signed(a2[16:2]) + $signed(pre_in[15:1]);
-		3: a3 <= {a2[16],a2[16:1]} + {pre_in[15],pre_in};
-	endcase
-
-	if(att[4]) a4 <= 0;
-	else a4 <= a3 >>> att[3:0];
-
-	//clamping
-	out <= ^a4[16:15] ? {a4[16],{15{a4[15]}}} : a4[15:0];
-end
-
-endmodule
-
-/////////////////////////////////////////////////////////////////////
-
 // CSync generation
 // Shifts HSync left by 1 HSync period during VSync
 
diff --git a/sys/vga_out.sv b/sys/vga_out.sv
index e316000..b66bef7 100644
--- a/sys/vga_out.sv
+++ b/sys/vga_out.sv
@@ -1,11 +1,20 @@
 
 module vga_out
 (
+	input         clk,
 	input         ypbpr_full,
 	input         ypbpr_en,
 
+	input         hsync,
+	input         vsync,
+	input         csync,
+
 	input  [23:0] din,
-	output [23:0] dout
+	output [23:0] dout,
+
+	output reg    hsync_o,
+	output reg    vsync_o,
+	output reg    csync_o
 );
 
 wire [5:0] yuv_full[225] = '{
@@ -49,17 +58,32 @@ wire [5:0] blue  = din[7:2];
 // Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
 // Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
 
-wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
-wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
-wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+reg [18:0] y_2, pb_2, pr_2;
 
-wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
-wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
-wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+wire [7:0] y  = ( y_2[17:8] < 16) ? 8'd16 : ( y_2[17:8] > 235) ? 8'd235 :  y_2[15:8];
+wire [7:0] pb = (pb_2[17:8] < 16) ? 8'd16 : (pb_2[17:8] > 240) ? 8'd240 : pb_2[15:8];
+wire [7:0] pr = (pr_2[17:8] < 16) ? 8'd16 : (pr_2[17:8] > 240) ? 8'd240 : pr_2[15:8];
 
-assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16];
-assign dout[15:8]  = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]), 2'b00} : din[15:8];
-assign dout[7:0]   = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0];
+reg [7:0] y_3, pb_3, pr_3;
+reg [23:0] din2, din3;
+reg hsync2, vsync2, csync2;
+always @(posedge clk) begin
+	y_2  <= 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+	pb_2 <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+	pr_2 <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
 
+	y_3  <= {(ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]), 2'b00};
+	pb_3 <= {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00};
+	pr_3 <= {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00};
+
+	hsync_o <= hsync2; hsync2 <= hsync;
+	vsync_o <= vsync2; vsync2 <= vsync;
+	csync_o <= csync2; csync2 <= csync;
+
+	din2 <= din;
+	din3 <= din2;
+end
+
+assign dout = ypbpr_en ? {pr_3, y_3, pb_3} : din3;
 
 endmodule