From b54236b9cc22c97829d876053b50cdb3f543fdfb Mon Sep 17 00:00:00 2001 From: sorgelig Date: Sun, 21 Mar 2021 01:29:09 +0800 Subject: [PATCH] 16bit for disk I/O. Fix: audio must be signed. --- MacPlus.sv | 22 +++++++++------------- rtl/dataController_top.v | 6 +++--- rtl/ncr5380.v | 10 +++++----- rtl/scsi.v | 29 +++++++++++++++++++---------- 4 files changed, 36 insertions(+), 31 deletions(-) diff --git a/MacPlus.sv b/MacPlus.sv index 44cdb8a..83b833b 100644 --- a/MacPlus.sv +++ b/MacPlus.sv @@ -272,9 +272,9 @@ wire [31:0] sd_lba; wire [1:0] sd_rd; wire [1:0] sd_wr; wire sd_ack; -wire [8:0] sd_buff_addr; -wire [7:0] sd_buff_dout; -wire [7:0] sd_buff_din; +wire [7:0] sd_buff_addr; +wire [15:0] sd_buff_dout; +wire [15:0] sd_buff_din; wire sd_buff_wr; wire [1:0] img_mounted; wire [31:0] img_size; @@ -287,11 +287,11 @@ wire [24:0] ps2_mouse; wire capslock; wire [24:0] ioctl_addr; -wire [7:0] ioctl_data; +wire [15:0] ioctl_data; wire [32:0] TIMESTAMP; -hps_io #(.STRLEN($size(CONF_STR)>>3), .VDNUM(2)) hps_io +hps_io #(.STRLEN($size(CONF_STR)>>3), .VDNUM(2), .WIDE(1)) hps_io ( .clk_sys(clk_sys), .HPS_BUS(HPS_BUS), @@ -346,7 +346,7 @@ assign VGA_SL = 0; wire [10:0] audio; assign AUDIO_L = {audio[10:0], 5'b00000}; assign AUDIO_R = {audio[10:0], 5'b00000}; -assign AUDIO_S = 0; +assign AUDIO_S = 1; assign AUDIO_MIX = 0; @@ -731,16 +731,12 @@ reg [15:0] dio_data; reg dio_write; always @(posedge clk_sys) begin - reg [7:0] temp; reg old_cyc = 0; if(ioctl_write) begin - if(~ioctl_addr[0]) temp <= ioctl_data; - else begin - dio_data <= {temp, ioctl_data}; - dio_a <= {dio_index[1:0], dio_addr[18:0]}; - ioctl_wait <= 1; - end + dio_data <= {ioctl_data[7:0], ioctl_data[15:8]}; + dio_a <= {dio_index[1:0], dio_addr[18:0]}; + ioctl_wait <= 1; end old_cyc <= dioBusControl; diff --git a/rtl/dataController_top.v b/rtl/dataController_top.v index 476b490..44cb307 100644 --- a/rtl/dataController_top.v +++ b/rtl/dataController_top.v @@ -83,9 +83,9 @@ module dataController_top( output [1:0] io_rd, output [1:0] io_wr, input io_ack, - input [8:0] sd_buff_addr, - input [7:0] sd_buff_dout, - output [7:0] sd_buff_din, + input [7:0] sd_buff_addr, + input [15:0] sd_buff_dout, + output [15:0] sd_buff_din, input sd_buff_wr ); diff --git a/rtl/ncr5380.v b/rtl/ncr5380.v index 3a4d8b2..a8cc357 100644 --- a/rtl/ncr5380.v +++ b/rtl/ncr5380.v @@ -71,9 +71,9 @@ module ncr5380 output [1:0] io_wr, input io_ack, - input [8:0] sd_buff_addr, - input [7:0] sd_buff_dout, - output [7:0] sd_buff_din, + input [7:0] sd_buff_addr, + input [15:0] sd_buff_dout, + output [15:0] sd_buff_din, input sd_buff_wr ); @@ -287,7 +287,7 @@ module ncr5380 wire [7:0] scsi2_dout; wire [31:0] io_lba_2; - wire [7:0] sd_buff_din_2; + wire [15:0] sd_buff_din_2; // connect a target scsi #(.ID(2)) scsi2 @@ -329,7 +329,7 @@ module ncr5380 wire [7:0] scsi6_dout; wire [31:0] io_lba_6; - wire [7:0] sd_buff_din_6; + wire [15:0] sd_buff_din_6; scsi #(.ID(6)) scsi6 ( diff --git a/rtl/scsi.v b/rtl/scsi.v index 1267ba1..4f07aac 100644 --- a/rtl/scsi.v +++ b/rtl/scsi.v @@ -32,10 +32,10 @@ module scsi output reg io_wr, input io_ack, - input [8:0] sd_buff_addr, - input [7:0] sd_buff_dout, - output reg [7:0] sd_buff_din, - input sd_buff_wr + input [7:0] sd_buff_addr, + input [15:0] sd_buff_dout, + output reg [15:0] sd_buff_din, + input sd_buff_wr ); @@ -52,13 +52,19 @@ reg [2:0] phase; // ---------------- buffer read engine ----------------------- // the buffer itself. Can hold one sector -reg [7:0] buffer_out [512]; -always @(posedge clk) sd_buff_din <= buffer_out[sd_buff_addr]; +reg [7:0] buffer_out0 [256]; +always @(posedge clk) sd_buff_din[7:0] <= buffer_out0[sd_buff_addr]; + +reg [7:0] buffer_out1 [256]; +always @(posedge clk) sd_buff_din[15:8] <= buffer_out1[sd_buff_addr]; // ---------------- buffer write engine ---------------------- // the buffer itself. Can hold one sector -reg [7:0] buffer_in [512]; -always @(posedge clk) if(sd_buff_wr) buffer_in[sd_buff_addr] <= sd_buff_dout; +reg [7:0] buffer_in0 [256]; +always @(posedge clk) if(sd_buff_wr) buffer_in0[sd_buff_addr] <= sd_buff_dout[7:0]; + +reg [7:0] buffer_in1 [256]; +always @(posedge clk) if(sd_buff_wr) buffer_in1[sd_buff_addr] <= sd_buff_dout[15:8]; // ----------------------------------------------------------- @@ -136,7 +142,7 @@ wire [7:0] mode_sense_dout = // clock data out of buffer to allow for embedded ram reg [7:0] buffer_dout; -always @(posedge clk) buffer_dout <= buffer_in[data_cnt]; +always @(posedge clk) buffer_dout <= data_cnt[0] ? buffer_in1[data_cnt[8:1]] : buffer_in0[data_cnt[8:1]]; // buffer to store incoming commands reg [3:0] cmd_cnt; @@ -185,7 +191,10 @@ end always @(posedge clk) begin if(stb_ack) begin if(phase == `PHASE_CMD_IN) cmd[cmd_cnt] <= din; - if(phase == `PHASE_DATA_IN) buffer_out[data_cnt] <= din; + if(phase == `PHASE_DATA_IN) begin + if(data_cnt[0]) buffer_out1[data_cnt[8:1]] <= din; + else buffer_out0[data_cnt[8:1]] <= din; + end end end