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https://github.com/MiSTer-devel/MacPlus_MiSTer.git
synced 2024-05-28 22:41:28 +00:00
Update sys. Re-organizing the sources.
This commit is contained in:
parent
1b5314cc30
commit
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5
MacPlus.sdc
Normal file
5
MacPlus.sdc
Normal file
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@ -0,0 +1,5 @@
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derive_pll_clocks
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derive_clock_uncertainty
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set_multicycle_path -from {emu|m68k|*} -setup 2
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set_multicycle_path -from {emu|m68k|*} -hold 1
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31
files.qip
31
files.qip
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@ -1,16 +1,17 @@
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set_global_assignment -name QIP_FILE src/tg68k/TG68K.qip
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set_global_assignment -name QIP_FILE rtl/tg68k/TG68K.qip
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set_global_assignment -name SYSTEMVERILOG_FILE src/sdram.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
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set_global_assignment -name VERILOG_FILE src/scsi.v
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set_global_assignment -name VERILOG_FILE rtl/scsi.v
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set_global_assignment -name VERILOG_FILE src/ncr5380.v
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set_global_assignment -name VERILOG_FILE rtl/ncr5380.v
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set_global_assignment -name VERILOG_FILE src/floppy_track_encoder.v
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set_global_assignment -name VERILOG_FILE rtl/floppy_track_encoder.v
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set_global_assignment -name VERILOG_FILE src/floppy.v
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set_global_assignment -name VERILOG_FILE rtl/floppy.v
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set_global_assignment -name SYSTEMVERILOG_FILE src/ps2_kbd.sv
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/ps2_kbd.sv
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set_global_assignment -name VERILOG_FILE src/ps2_mouse.v
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set_global_assignment -name VERILOG_FILE rtl/ps2_mouse.v
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set_global_assignment -name VERILOG_FILE src/scc.v
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set_global_assignment -name VERILOG_FILE rtl/scc.v
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set_global_assignment -name VERILOG_FILE src/iwm.v
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set_global_assignment -name VERILOG_FILE rtl/iwm.v
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set_global_assignment -name VERILOG_FILE src/via.v
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set_global_assignment -name VERILOG_FILE rtl/via.v
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set_global_assignment -name VERILOG_FILE src/addrDecoder.v
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set_global_assignment -name VERILOG_FILE rtl/addrDecoder.v
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set_global_assignment -name VERILOG_FILE src/addrController_top.v
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set_global_assignment -name VERILOG_FILE rtl/addrController_top.v
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set_global_assignment -name VERILOG_FILE src/dataController_top.v
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set_global_assignment -name VERILOG_FILE rtl/dataController_top.v
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set_global_assignment -name VERILOG_FILE src/video.v
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set_global_assignment -name VERILOG_FILE rtl/video.v
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set_global_assignment -name SDC_FILE MacPlus.sdc
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set_global_assignment -name SYSTEMVERILOG_FILE MacPlus.sv
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set_global_assignment -name SYSTEMVERILOG_FILE MacPlus.sv
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388
sys/hps_io.v
388
sys/hps_io.v
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@ -2,7 +2,7 @@
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// hps_io.v
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// hps_io.v
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//
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//
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
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// Copyright (c) 2017-2019 Alexey Melnikov
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// Copyright (c) 2017-2020 Alexey Melnikov
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// it under the terms of the GNU General Public License as published
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@ -18,14 +18,11 @@
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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///////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////
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// altera message_off 10665
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//
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//
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// Use buffer to access SD card. It's time-critical part.
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// Use buffer to access SD card. It's time-critical part.
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//
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//
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// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
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// clk_ps2 = CLK_SYS/(PS2DIV*2)
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//
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// WIDE=1 for 16 bit file I/O
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// WIDE=1 for 16 bit file I/O
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// VDNUM 1-4
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// VDNUM 1-4
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module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
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module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
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@ -36,12 +33,15 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
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// parameter STRLEN and the actual length of conf_str have to match
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// parameter STRLEN and the actual length of conf_str have to match
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input [(8*STRLEN)-1:0] conf_str,
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input [(8*STRLEN)-1:0] conf_str,
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// buttons up to 32
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output reg [31:0] joystick_0,
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output reg [31:0] joystick_0,
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output reg [31:0] joystick_1,
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output reg [31:0] joystick_1,
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output reg [31:0] joystick_2,
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output reg [31:0] joystick_2,
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output reg [31:0] joystick_3,
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output reg [31:0] joystick_3,
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output reg [31:0] joystick_4,
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output reg [31:0] joystick_4,
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output reg [31:0] joystick_5,
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output reg [31:0] joystick_5,
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// analog -127..+127, Y: [15:8], X: [7:0]
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output reg [15:0] joystick_analog_0,
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output reg [15:0] joystick_analog_0,
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output reg [15:0] joystick_analog_1,
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output reg [15:0] joystick_analog_1,
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output reg [15:0] joystick_analog_2,
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output reg [15:0] joystick_analog_2,
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@ -49,6 +49,22 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
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output reg [15:0] joystick_analog_4,
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output reg [15:0] joystick_analog_4,
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output reg [15:0] joystick_analog_5,
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output reg [15:0] joystick_analog_5,
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// paddle 0..255
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output reg [7:0] paddle_0,
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output reg [7:0] paddle_1,
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output reg [7:0] paddle_2,
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output reg [7:0] paddle_3,
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output reg [7:0] paddle_4,
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output reg [7:0] paddle_5,
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// spinner [7:0] -128..+127, [8] - toggle with every update
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output reg [8:0] spinner_0,
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output reg [8:0] spinner_1,
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output reg [8:0] spinner_2,
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output reg [8:0] spinner_3,
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output reg [8:0] spinner_4,
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output reg [8:0] spinner_5,
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output [1:0] buttons,
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output [1:0] buttons,
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output forced_scandoubler,
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output forced_scandoubler,
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output direct_video,
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output direct_video,
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@ -109,10 +125,6 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
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// UART flags
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// UART flags
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input [15:0] uart_mode,
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input [15:0] uart_mode,
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// CD interface
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input [48:0] cd_in,
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output reg [48:0] cd_out,
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// ps2 keyboard emulation
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// ps2 keyboard emulation
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output ps2_kbd_clk_out,
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output ps2_kbd_clk_out,
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output ps2_kbd_data_out,
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output ps2_kbd_data_out,
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@ -136,24 +148,32 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
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output reg [24:0] ps2_mouse = 0,
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output reg [24:0] ps2_mouse = 0,
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output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements
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output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements
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inout [21:0] gamma_bus
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inout [21:0] gamma_bus,
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// for core-specific extensions
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inout [35:0] EXT_BUS
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);
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);
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assign EXT_BUS[31:16] = HPS_BUS[31:16];
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assign EXT_BUS[35:33] = HPS_BUS[35:33];
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localparam MAX_W = $clog2((512 > (STRLEN+1)) ? 512 : (STRLEN+1))-1;
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localparam DW = (WIDE) ? 15 : 7;
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localparam DW = (WIDE) ? 15 : 7;
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localparam AW = (WIDE) ? 7 : 8;
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localparam AW = (WIDE) ? 7 : 8;
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localparam VD = VDNUM-1;
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localparam VD = VDNUM-1;
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wire io_wait = ioctl_wait;
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wire io_enable= |HPS_BUS[35:34];
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wire io_strobe= HPS_BUS[33];
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wire io_strobe= HPS_BUS[33];
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wire io_enable= HPS_BUS[34];
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wire fp_enable= HPS_BUS[35];
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wire io_wide = (WIDE) ? 1'b1 : 1'b0;
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wire io_wide = (WIDE) ? 1'b1 : 1'b0;
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wire [15:0] io_din = HPS_BUS[31:16];
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wire [15:0] io_din = HPS_BUS[31:16];
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reg [15:0] io_dout;
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reg [15:0] io_dout;
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assign HPS_BUS[37] = io_wait;
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assign HPS_BUS[37] = ioctl_wait;
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assign HPS_BUS[36] = clk_sys;
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assign HPS_BUS[36] = clk_sys;
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assign HPS_BUS[32] = io_wide;
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assign HPS_BUS[32] = io_wide;
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assign HPS_BUS[15:0] = io_dout;
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assign HPS_BUS[15:0] = EXT_BUS[32] ? EXT_BUS[15:0] : io_dout;
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reg [15:0] cfg;
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reg [15:0] cfg;
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assign buttons = cfg[1:0];
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assign buttons = cfg[1:0];
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@ -212,18 +232,17 @@ reg [31:0] ps2_key_raw = 0;
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wire pressed = (ps2_key_raw[15:8] != 8'hf0);
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wire pressed = (ps2_key_raw[15:8] != 8'hf0);
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wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
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wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
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reg [9:0] byte_cnt;
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reg [MAX_W:0] byte_cnt;
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always@(posedge clk_sys) begin
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always@(posedge clk_sys) begin
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reg [15:0] cmd;
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reg [15:0] cmd;
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reg [2:0] b_wr;
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reg [2:0] b_wr;
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reg [2:0] stick_idx;
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reg [3:0] stick_idx;
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reg [3:0] pdsp_idx;
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reg ps2skip = 0;
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reg ps2skip = 0;
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reg [3:0] stflg = 0;
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reg [3:0] stflg = 0;
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reg [63:0] status_req;
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reg [63:0] status_req;
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reg old_status_set = 0;
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reg old_status_set = 0;
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reg [7:0] cd_req = 0;
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reg old_cd = 0;
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reg old_info = 0;
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reg old_info = 0;
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reg [7:0] info_n = 0;
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reg [7:0] info_n = 0;
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@ -236,9 +255,6 @@ always@(posedge clk_sys) begin
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old_info <= info_req;
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old_info <= info_req;
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if(~old_info & info_req) info_n <= info;
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if(~old_info & info_req) info_n <= info;
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old_cd <= cd_in[48];
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if(old_cd ^ cd_in[48]) cd_req <= cd_req + 1'd1;
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sd_buff_wr <= b_wr[0];
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sd_buff_wr <= b_wr[0];
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if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
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if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
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b_wr <= (b_wr<<1);
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b_wr <= (b_wr<<1);
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@ -257,63 +273,61 @@ always@(posedge clk_sys) begin
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end
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end
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if(cmd == 'h22) RTC[64] <= ~RTC[64];
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if(cmd == 'h22) RTC[64] <= ~RTC[64];
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if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
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if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
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if(cmd == 'h35) cd_out[48] <= ~cd_out[48];
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cmd <= 0;
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cmd <= 0;
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byte_cnt <= 0;
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byte_cnt <= 0;
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sd_ack <= 0;
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sd_ack <= 0;
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sd_ack_conf <= 0;
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sd_ack_conf <= 0;
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io_dout <= 0;
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io_dout <= 0;
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ps2skip <= 0;
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ps2skip <= 0;
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end else begin
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end
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if(io_strobe) begin
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else if(io_strobe) begin
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io_dout <= 0;
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io_dout <= 0;
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if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
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if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
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if(byte_cnt == 0) begin
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if(byte_cnt == 0) begin
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cmd <= io_din;
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cmd <= io_din;
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case(io_din)
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case(io_din)
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'h19: sd_ack_conf <= 1;
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'h19: sd_ack_conf <= 1;
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'h17,
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'h17,
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'h18: sd_ack <= 1;
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'h18: sd_ack <= 1;
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'h29: io_dout <= {4'hA, stflg};
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'h29: io_dout <= {4'hA, stflg};
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'h2B: io_dout <= 1;
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'h2B: io_dout <= 1;
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'h2F: io_dout <= 1;
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'h2F: io_dout <= 1;
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'h32: io_dout <= gamma_bus[21];
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'h32: io_dout <= gamma_bus[21];
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'h34: io_dout <= cd_req;
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'h36: begin io_dout <= info_n; info_n <= 0; end
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'h36: begin io_dout <= info_n; info_n <= 0; end
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endcase
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endcase
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sd_buff_addr <= 0;
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sd_buff_addr <= 0;
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img_mounted <= 0;
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img_mounted <= 0;
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if(io_din == 5) ps2_key_raw <= 0;
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if(io_din == 5) ps2_key_raw <= 0;
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end else begin
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end else begin
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case(cmd)
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case(cmd)
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// buttons and switches
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// buttons and switches
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'h01: cfg <= io_din;
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'h01: cfg <= io_din;
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'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din;
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'h02: if(byte_cnt==1) joystick_0[15:0] <= io_din; else joystick_0[31:16] <= io_din;
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'h03: if(byte_cnt==1) joystick_1[15:0] <= io_din; else joystick_1[31:16] <= io_din;
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'h03: if(byte_cnt==1) joystick_1[15:0] <= io_din; else joystick_1[31:16] <= io_din;
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'h10: if(byte_cnt==1) joystick_2[15:0] <= io_din; else joystick_2[31:16] <= io_din;
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'h10: if(byte_cnt==1) joystick_2[15:0] <= io_din; else joystick_2[31:16] <= io_din;
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'h11: if(byte_cnt==1) joystick_3[15:0] <= io_din; else joystick_3[31:16] <= io_din;
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'h11: if(byte_cnt==1) joystick_3[15:0] <= io_din; else joystick_3[31:16] <= io_din;
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'h12: if(byte_cnt==1) joystick_4[15:0] <= io_din; else joystick_4[31:16] <= io_din;
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'h12: if(byte_cnt==1) joystick_4[15:0] <= io_din; else joystick_4[31:16] <= io_din;
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'h13: if(byte_cnt==1) joystick_5[15:0] <= io_din; else joystick_5[31:16] <= io_din;
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'h13: if(byte_cnt==1) joystick_5[15:0] <= io_din; else joystick_5[31:16] <= io_din;
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// store incoming ps2 mouse bytes
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// store incoming ps2 mouse bytes
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'h04: begin
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'h04: begin
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if(PS2DIV) begin
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if(PS2DIV) begin
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mouse_data <= io_din[7:0];
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mouse_data <= io_din[7:0];
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mouse_we <= 1;
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mouse_we <= 1;
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end
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end
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if(&io_din[15:8]) ps2skip <= 1;
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if(&io_din[15:8]) ps2skip <= 1;
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if(~&io_din[15:8] & ~ps2skip) begin
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if(~&io_din[15:8] && ~ps2skip && !byte_cnt[MAX_W:2]) begin
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case(byte_cnt)
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case(byte_cnt[1:0])
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1: ps2_mouse[7:0] <= io_din[7:0];
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1: ps2_mouse[7:0] <= io_din[7:0];
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2: ps2_mouse[15:8] <= io_din[7:0];
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2: ps2_mouse[15:8] <= io_din[7:0];
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3: ps2_mouse[23:16] <= io_din[7:0];
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3: ps2_mouse[23:16] <= io_din[7:0];
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endcase
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endcase
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case(byte_cnt)
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case(byte_cnt[1:0])
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1: ps2_mouse_ext[7:0] <= {io_din[14], io_din[14:8]};
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1: ps2_mouse_ext[7:0] <= {io_din[14], io_din[14:8]};
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2: ps2_mouse_ext[11:8] <= io_din[11:8];
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2: ps2_mouse_ext[11:8] <= io_din[11:8];
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3: ps2_mouse_ext[15:12]<= io_din[11:8];
|
3: ps2_mouse_ext[15:12]<= io_din[11:8];
|
||||||
|
@ -321,8 +335,8 @@ always@(posedge clk_sys) begin
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
// store incoming ps2 keyboard bytes
|
// store incoming ps2 keyboard bytes
|
||||||
'h05: begin
|
'h05: begin
|
||||||
if(&io_din[15:8]) ps2skip <= 1;
|
if(&io_din[15:8]) ps2skip <= 1;
|
||||||
if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
|
if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
|
||||||
if(PS2DIV) begin
|
if(PS2DIV) begin
|
||||||
|
@ -331,130 +345,137 @@ always@(posedge clk_sys) begin
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
// reading config string, returning a byte from string
|
// reading config string, returning a byte from string
|
||||||
'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
|
'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
|
||||||
|
|
||||||
// reading sd card status
|
// reading sd card status
|
||||||
'h16: case(byte_cnt)
|
'h16: if(!byte_cnt[MAX_W:3]) begin
|
||||||
|
case(byte_cnt[2:0])
|
||||||
1: io_dout <= sd_cmd;
|
1: io_dout <= sd_cmd;
|
||||||
2: io_dout <= sd_lba[15:0];
|
2: io_dout <= sd_lba[15:0];
|
||||||
3: io_dout <= sd_lba[31:16];
|
3: io_dout <= sd_lba[31:16];
|
||||||
4: io_dout <= sd_req_type;
|
4: io_dout <= sd_req_type;
|
||||||
endcase
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
// send SD config IO -> FPGA
|
// send SD config IO -> FPGA
|
||||||
// flag that download begins
|
// flag that download begins
|
||||||
// sd card knows data is config if sd_dout_strobe is asserted
|
// sd card knows data is config if sd_dout_strobe is asserted
|
||||||
// with sd_ack still being inactive (low)
|
// with sd_ack still being inactive (low)
|
||||||
'h19,
|
'h19,
|
||||||
// send sector IO -> FPGA
|
// send sector IO -> FPGA
|
||||||
// flag that download begins
|
// flag that download begins
|
||||||
'h17: begin
|
'h17: begin
|
||||||
sd_buff_dout <= io_din[DW:0];
|
sd_buff_dout <= io_din[DW:0];
|
||||||
b_wr <= 1;
|
b_wr <= 1;
|
||||||
end
|
end
|
||||||
|
|
||||||
// reading sd card write data
|
// reading sd card write data
|
||||||
'h18: begin
|
'h18: begin
|
||||||
if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
|
if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||||
io_dout <= sd_buff_din;
|
io_dout <= sd_buff_din;
|
||||||
end
|
end
|
||||||
|
|
||||||
// joystick analog
|
// joystick analog
|
||||||
'h1a: case(byte_cnt)
|
'h1a: if(!byte_cnt[MAX_W:2]) begin
|
||||||
1: stick_idx <= io_din[2:0]; // first byte is joystick index
|
case(byte_cnt[1:0])
|
||||||
|
1: {pdsp_idx,stick_idx} <= io_din[7:0]; // first byte is joystick index
|
||||||
2: case(stick_idx)
|
2: case(stick_idx)
|
||||||
0: joystick_analog_0 <= io_din;
|
0: joystick_analog_0 <= io_din;
|
||||||
1: joystick_analog_1 <= io_din;
|
1: joystick_analog_1 <= io_din;
|
||||||
2: joystick_analog_2 <= io_din;
|
2: joystick_analog_2 <= io_din;
|
||||||
3: joystick_analog_3 <= io_din;
|
3: joystick_analog_3 <= io_din;
|
||||||
4: joystick_analog_4 <= io_din;
|
4: joystick_analog_4 <= io_din;
|
||||||
5: joystick_analog_5 <= io_din;
|
5: joystick_analog_5 <= io_din;
|
||||||
|
15: case(pdsp_idx)
|
||||||
|
0: paddle_0 <= io_din[7:0];
|
||||||
|
1: paddle_1 <= io_din[7:0];
|
||||||
|
2: paddle_2 <= io_din[7:0];
|
||||||
|
3: paddle_3 <= io_din[7:0];
|
||||||
|
4: paddle_4 <= io_din[7:0];
|
||||||
|
5: paddle_5 <= io_din[7:0];
|
||||||
|
8: spinner_0 <= {~spinner_0[8],io_din[7:0]};
|
||||||
|
9: spinner_1 <= {~spinner_1[8],io_din[7:0]};
|
||||||
|
10: spinner_2 <= {~spinner_2[8],io_din[7:0]};
|
||||||
|
11: spinner_3 <= {~spinner_3[8],io_din[7:0]};
|
||||||
|
12: spinner_4 <= {~spinner_4[8],io_din[7:0]};
|
||||||
|
13: spinner_5 <= {~spinner_5[8],io_din[7:0]};
|
||||||
|
endcase
|
||||||
endcase
|
endcase
|
||||||
endcase
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
// notify image selection
|
// notify image selection
|
||||||
'h1c: begin
|
'h1c: begin
|
||||||
img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
|
img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1;
|
||||||
img_readonly <= io_din[7];
|
img_readonly <= io_din[7];
|
||||||
end
|
end
|
||||||
|
|
||||||
// send image info
|
// send image info
|
||||||
'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
|
'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
|
||||||
|
|
||||||
// status, 64bit version
|
// status, 64bit version
|
||||||
'h1e: case(byte_cnt)
|
'h1e: if(!byte_cnt[MAX_W:3]) begin
|
||||||
|
case(byte_cnt[2:0])
|
||||||
1: status[15:00] <= io_din;
|
1: status[15:00] <= io_din;
|
||||||
2: status[31:16] <= io_din;
|
2: status[31:16] <= io_din;
|
||||||
3: status[47:32] <= io_din;
|
3: status[47:32] <= io_din;
|
||||||
4: status[63:48] <= io_din;
|
4: status[63:48] <= io_din;
|
||||||
endcase
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
// reading keyboard LED status
|
// reading keyboard LED status
|
||||||
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
|
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
|
||||||
|
|
||||||
// reading ps2 keyboard/mouse control
|
// reading ps2 keyboard/mouse control
|
||||||
'h21: if(PS2DIV) begin
|
'h21: if(PS2DIV) begin
|
||||||
if(byte_cnt == 1) begin
|
if(byte_cnt == 1) begin
|
||||||
io_dout <= kbd_data_host;
|
io_dout <= kbd_data_host;
|
||||||
kbd_rd <= 1;
|
kbd_rd <= 1;
|
||||||
end
|
|
||||||
else
|
|
||||||
if(byte_cnt == 2) begin
|
|
||||||
io_dout <= mouse_data_host;
|
|
||||||
mouse_rd <= 1;
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
else
|
||||||
|
if(byte_cnt == 2) begin
|
||||||
|
io_dout <= mouse_data_host;
|
||||||
|
mouse_rd <= 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
//RTC
|
//RTC
|
||||||
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
|
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
|
||||||
|
|
||||||
//Video res.
|
//Video res.
|
||||||
'h23: if(!byte_cnt[9:4]) io_dout <= vc_dout;
|
'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
|
||||||
|
|
||||||
//RTC
|
//RTC
|
||||||
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
|
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
|
||||||
|
|
||||||
//UART flags
|
//UART flags
|
||||||
'h28: io_dout <= uart_mode;
|
'h28: io_dout <= uart_mode;
|
||||||
|
|
||||||
//status set
|
//status set
|
||||||
'h29: case(byte_cnt)
|
'h29: if(!byte_cnt[MAX_W:3]) begin
|
||||||
|
case(byte_cnt[2:0])
|
||||||
1: io_dout <= status_req[15:00];
|
1: io_dout <= status_req[15:00];
|
||||||
2: io_dout <= status_req[31:16];
|
2: io_dout <= status_req[31:16];
|
||||||
3: io_dout <= status_req[47:32];
|
3: io_dout <= status_req[47:32];
|
||||||
4: io_dout <= status_req[63:48];
|
4: io_dout <= status_req[63:48];
|
||||||
endcase
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
//menu mask
|
//menu mask
|
||||||
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
|
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
|
||||||
|
|
||||||
//sdram size set
|
//sdram size set
|
||||||
'h31: if(byte_cnt == 1) sdram_sz <= io_din;
|
'h31: if(byte_cnt == 1) sdram_sz <= io_din;
|
||||||
|
|
||||||
// Gamma
|
// Gamma
|
||||||
'h32: gamma_en <= io_din[0];
|
'h32: gamma_en <= io_din[0];
|
||||||
'h33: begin
|
'h33: begin
|
||||||
gamma_wr_addr <= {(byte_cnt[1:0]-1'b1),io_din[15:8]};
|
gamma_wr_addr <= {(byte_cnt[1:0]-1'b1),io_din[15:8]};
|
||||||
{gamma_wr, gamma_value} <= {1'b1,io_din[7:0]};
|
{gamma_wr, gamma_value} <= {1'b1,io_din[7:0]};
|
||||||
if (byte_cnt[1:0] == 3) byte_cnt <= 1;
|
if (byte_cnt[1:0] == 3) byte_cnt <= 1;
|
||||||
end
|
end
|
||||||
|
endcase
|
||||||
//CD get
|
|
||||||
'h34: case(byte_cnt)
|
|
||||||
1: io_dout <= cd_in[15:0];
|
|
||||||
2: io_dout <= cd_in[31:16];
|
|
||||||
3: io_dout <= cd_in[47:32];
|
|
||||||
endcase
|
|
||||||
|
|
||||||
//CD set
|
|
||||||
'h35: case(byte_cnt)
|
|
||||||
1: cd_out[15:0] <= io_din;
|
|
||||||
2: cd_out[31:16] <= io_din;
|
|
||||||
3: cd_out[47:32] <= io_din;
|
|
||||||
endcase
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
@ -544,7 +565,7 @@ always@(posedge clk_sys) begin
|
||||||
ioctl_wr <= wr;
|
ioctl_wr <= wr;
|
||||||
wr <= 0;
|
wr <= 0;
|
||||||
|
|
||||||
if(~io_enable) has_cmd <= 0;
|
if(~fp_enable) has_cmd <= 0;
|
||||||
else begin
|
else begin
|
||||||
if(io_strobe) begin
|
if(io_strobe) begin
|
||||||
|
|
||||||
|
@ -873,92 +894,3 @@ always @(posedge clk_100) begin
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
|
||||||
//
|
|
||||||
// Phase shift helper module for better 64MB/128MB modules support.
|
|
||||||
//
|
|
||||||
// Copyright (c) 2019 Alexey Melnikov
|
|
||||||
//
|
|
||||||
|
|
||||||
module phase_shift #(parameter M32MB=0, M64MB=0, M128MB=0)
|
|
||||||
(
|
|
||||||
input reset,
|
|
||||||
|
|
||||||
input clk,
|
|
||||||
input pll_locked,
|
|
||||||
|
|
||||||
output reg phase_en,
|
|
||||||
output reg updn,
|
|
||||||
input phase_done,
|
|
||||||
|
|
||||||
input [15:0] sdram_sz,
|
|
||||||
output reg ready
|
|
||||||
);
|
|
||||||
|
|
||||||
localparam ph32 = ($signed(M32MB ) >= 0) ? M32MB : (0 - M32MB);
|
|
||||||
localparam ph64 = ($signed(M64MB ) >= 0) ? M64MB : (0 - M64MB);
|
|
||||||
localparam ph128 = ($signed(M128MB) >= 0) ? M128MB : (0 - M128MB);
|
|
||||||
|
|
||||||
localparam up32 = ($signed(M32MB ) >= 0) ? 1'b1 : 1'b0;
|
|
||||||
localparam up64 = ($signed(M64MB ) >= 0) ? 1'b1 : 1'b0;
|
|
||||||
localparam up128 = ($signed(M128MB) >= 0) ? 1'b1 : 1'b0;
|
|
||||||
|
|
||||||
always @(posedge clk, posedge reset) begin
|
|
||||||
reg [2:0] state = 0;
|
|
||||||
reg [7:0] cnt;
|
|
||||||
reg [8:0] ph;
|
|
||||||
|
|
||||||
if(reset) begin
|
|
||||||
state <= 0;
|
|
||||||
ready <= 0;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
case(state)
|
|
||||||
0: begin
|
|
||||||
ready <= 0;
|
|
||||||
if(pll_locked) state <= state + 1'd1;
|
|
||||||
end
|
|
||||||
1: if(sdram_sz[15]) begin
|
|
||||||
cnt <= 0;
|
|
||||||
if(sdram_sz[14]) ph <= sdram_sz[8:0];
|
|
||||||
else begin
|
|
||||||
case(sdram_sz[1:0])
|
|
||||||
0: ph <= 0;
|
|
||||||
1: ph <= {up32[0],ph32[7:0]};
|
|
||||||
2: ph <= {up64[0],ph64[7:0]};
|
|
||||||
3: ph <= {up128[0],ph128[7:0]};
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
state <= state + 1'd1;
|
|
||||||
end
|
|
||||||
2: if(ph[7:0]) begin
|
|
||||||
ph[7:0] <= ph[7:0] - 1'd1;
|
|
||||||
updn <= ph[8];
|
|
||||||
state <= state + 1'd1;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
state <= 6;
|
|
||||||
end
|
|
||||||
3: begin
|
|
||||||
phase_en <= 1;
|
|
||||||
state <= state + 1'd1;
|
|
||||||
end
|
|
||||||
4: if(~phase_done) begin
|
|
||||||
phase_en <= 0;
|
|
||||||
state <= state + 1'd1;
|
|
||||||
end
|
|
||||||
5: if(phase_done) begin
|
|
||||||
cnt <= cnt + 1'd1;
|
|
||||||
if(cnt == ph[7:0]) state <= state + 1'd1;
|
|
||||||
else state <= 3;
|
|
||||||
end
|
|
||||||
6: begin
|
|
||||||
ready <= 1;
|
|
||||||
if(!sdram_sz[15]) state <= 0;
|
|
||||||
end
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
64
sys/osd.v
64
sys/osd.v
|
@ -38,7 +38,7 @@ reg osd_enable;
|
||||||
reg info = 0;
|
reg info = 0;
|
||||||
reg [8:0] infoh;
|
reg [8:0] infoh;
|
||||||
reg [8:0] infow;
|
reg [8:0] infow;
|
||||||
reg [11:0] infox;
|
reg [21:0] infox;
|
||||||
reg [21:0] infoy;
|
reg [21:0] infoy;
|
||||||
reg [21:0] osd_h;
|
reg [21:0] osd_h;
|
||||||
reg [21:0] osd_t;
|
reg [21:0] osd_t;
|
||||||
|
@ -123,31 +123,39 @@ end
|
||||||
reg [2:0] osd_de;
|
reg [2:0] osd_de;
|
||||||
reg osd_pixel;
|
reg osd_pixel;
|
||||||
reg [21:0] v_cnt;
|
reg [21:0] v_cnt;
|
||||||
|
reg v_cnt_h, v_cnt_1, v_cnt_2, v_cnt_3, v_cnt_4;
|
||||||
reg v_cnt_half, v_cnt_single, v_cnt_double, v_cnt_triple;
|
reg [21:0] v_osd_start_h, v_osd_start_1, v_osd_start_2, v_osd_start_3, v_osd_start_4, v_osd_start_5;
|
||||||
|
reg [21:0] v_info_start_h, v_info_start_1, v_info_start_2, v_info_start_3, v_info_start_4, v_info_start_5;
|
||||||
reg [21:0] v_osd_start_h, v_osd_start_s, v_osd_start_d, v_osd_start_t, v_osd_start_q;
|
|
||||||
|
|
||||||
wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR);
|
wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR);
|
||||||
|
|
||||||
// pipeline the comparisons a bit
|
// pipeline the comparisons a bit
|
||||||
always @(posedge clk_video) if(ce_pix) begin
|
always @(posedge clk_video) if(ce_pix) begin
|
||||||
v_cnt_half <= v_cnt < osd_t;
|
v_cnt_h <= v_cnt < osd_t;
|
||||||
v_cnt_single <= v_cnt < 320;
|
v_cnt_1 <= v_cnt < 320;
|
||||||
v_cnt_double <= v_cnt < 640;
|
v_cnt_2 <= v_cnt < 640;
|
||||||
v_cnt_triple <= v_cnt < 960;
|
v_cnt_3 <= v_cnt < 960;
|
||||||
|
v_cnt_4 <= v_cnt < 1280;
|
||||||
|
|
||||||
v_osd_start_h <= ((v_cnt-(osd_h_hdr>>1))>>1);
|
v_osd_start_h <= (v_cnt-(osd_h_hdr>>1))>>1;
|
||||||
v_osd_start_s <= ((v_cnt-osd_h_hdr)>>1);
|
v_osd_start_1 <= (v_cnt-osd_h_hdr)>>1;
|
||||||
v_osd_start_d <= ((v_cnt-(osd_h_hdr<<1))>>1);
|
v_osd_start_2 <= (v_cnt-(osd_h_hdr<<1))>>1;
|
||||||
v_osd_start_t <= ((v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1);
|
v_osd_start_3 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1;
|
||||||
v_osd_start_q <= ((v_cnt-(osd_h_hdr<<2))>>1);
|
v_osd_start_4 <= (v_cnt-(osd_h_hdr<<2))>>1;
|
||||||
|
v_osd_start_5 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<2)))>>1;
|
||||||
|
|
||||||
|
v_info_start_h <= rot[0] ? infox : infoy;
|
||||||
|
v_info_start_1 <= rot[0] ? infox : infoy;
|
||||||
|
v_info_start_2 <= rot[0] ? (infox<<1) : (infoy<<1);
|
||||||
|
v_info_start_3 <= rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1));
|
||||||
|
v_info_start_4 <= rot[0] ? (infox << 2) : (infoy << 2);
|
||||||
|
v_info_start_5 <= rot[0] ? (infox + (infox << 2)) : (infoy + (infoy << 2));
|
||||||
end
|
end
|
||||||
|
|
||||||
always @(posedge clk_video) begin
|
always @(posedge clk_video) begin
|
||||||
reg deD;
|
reg deD;
|
||||||
reg [1:0] osd_div;
|
reg [2:0] osd_div;
|
||||||
reg [1:0] multiscan;
|
reg [2:0] multiscan;
|
||||||
reg [7:0] osd_byte;
|
reg [7:0] osd_byte;
|
||||||
reg [23:0] h_cnt;
|
reg [23:0] h_cnt;
|
||||||
reg [21:0] dsp_width;
|
reg [21:0] dsp_width;
|
||||||
|
@ -199,26 +207,30 @@ always @(posedge clk_video) begin
|
||||||
if(~osd_enable) osd_en <= 0;
|
if(~osd_enable) osd_en <= 0;
|
||||||
|
|
||||||
half <= 0;
|
half <= 0;
|
||||||
if(v_cnt_half) begin
|
if(v_cnt_h) begin
|
||||||
multiscan <= 0;
|
multiscan <= 0;
|
||||||
v_osd_start <= info ? (rot[0] ? infox : infoy) : v_osd_start_h;
|
v_osd_start <= info ? v_info_start_h : v_osd_start_h;
|
||||||
half <= 1;
|
half <= 1;
|
||||||
end
|
end
|
||||||
else if(v_cnt_single | (rot[0] & v_cnt_double)) begin
|
else if(v_cnt_1 | (rot[0] & v_cnt_2)) begin
|
||||||
multiscan <= 0;
|
multiscan <= 0;
|
||||||
v_osd_start <= info ? (rot[0] ? infox : infoy) : v_osd_start_s;
|
v_osd_start <= info ? v_info_start_1 : v_osd_start_1;
|
||||||
end
|
end
|
||||||
else if(rot[0] ? v_cnt_triple : v_cnt_double) begin
|
else if(rot[0] ? v_cnt_3 : v_cnt_2) begin
|
||||||
multiscan <= 1;
|
multiscan <= 1;
|
||||||
v_osd_start <= info ? (rot[0] ? (infox<<1) : (infoy<<1)) : v_osd_start_d;
|
v_osd_start <= info ? v_info_start_2 : v_osd_start_2;
|
||||||
end
|
end
|
||||||
else if(v_cnt_triple | rot[0]) begin
|
else if(rot[0] ? v_cnt_4 : v_cnt_3) begin
|
||||||
multiscan <= 2;
|
multiscan <= 2;
|
||||||
v_osd_start <= info ? (rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1))) : v_osd_start_t;
|
v_osd_start <= info ? v_info_start_3 : v_osd_start_3;
|
||||||
|
end
|
||||||
|
else if(rot[0] | v_cnt_4) begin
|
||||||
|
multiscan <= 3;
|
||||||
|
v_osd_start <= info ? v_info_start_4 : v_osd_start_4;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
multiscan <= 3;
|
multiscan <= 4;
|
||||||
v_osd_start <= info ? (rot[0] ? (infox<<2) : (infoy<<2)) : v_osd_start_q;
|
v_osd_start <= info ? v_info_start_5 : v_osd_start_5;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
|
@ -4,9 +4,13 @@ set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
|
||||||
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
|
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
|
||||||
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||||
|
|
||||||
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v
|
||||||
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
|
set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v
|
||||||
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"]
|
|
||||||
|
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||||
|
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||||
|
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||||
|
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
||||||
|
|
||||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
|
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
|
||||||
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1"
|
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1"
|
||||||
|
|
|
@ -1,4 +0,0 @@
|
||||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
|
||||||
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
|
||||||
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
|
||||||
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"
|
|
|
@ -6,7 +6,11 @@ set_global_assignment -name SYNTHESIS_ONLY_QIP ON
|
||||||
|
|
||||||
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
|
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
|
||||||
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
|
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
|
||||||
set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"]
|
|
||||||
|
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
||||||
|
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
||||||
|
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
||||||
|
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
||||||
|
|
||||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
|
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
|
||||||
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
|
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"
|
||||||
|
|
|
@ -1,4 +0,0 @@
|
||||||
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
|
||||||
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
|
||||||
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
|
||||||
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
|
|
|
@ -1,3 +1,3 @@
|
||||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
|
set_global_assignment -name QIP_FILE rtl/pll.qip
|
||||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
|
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
|
||||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]
|
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]
|
||||||
|
|
|
@ -28,13 +28,16 @@ set_false_path -to {cfg[*]}
|
||||||
set_false_path -from {cfg[*]}
|
set_false_path -from {cfg[*]}
|
||||||
set_false_path -from {VSET[*]}
|
set_false_path -from {VSET[*]}
|
||||||
set_false_path -to {wcalc[*] hcalc[*]}
|
set_false_path -to {wcalc[*] hcalc[*]}
|
||||||
|
set_false_path -to {width[*] height[*]}
|
||||||
|
|
||||||
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
|
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
|
||||||
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 2
|
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
|
||||||
set_false_path -to {*_osd|v_cnt*}
|
set_false_path -to {*_osd|v_cnt*}
|
||||||
set_false_path -to {*_osd|v_osd_start*}
|
set_false_path -to {*_osd|v_osd_start*}
|
||||||
|
set_false_path -to {*_osd|v_info_start*}
|
||||||
set_false_path -to {*_osd|h_osd_start*}
|
set_false_path -to {*_osd|h_osd_start*}
|
||||||
set_false_path -from {*_osd|v_osd_start*}
|
set_false_path -from {*_osd|v_osd_start*}
|
||||||
|
set_false_path -from {*_osd|v_info_start*}
|
||||||
set_false_path -from {*_osd|h_osd_start*}
|
set_false_path -from {*_osd|h_osd_start*}
|
||||||
set_false_path -from {*_osd|rot*}
|
set_false_path -from {*_osd|rot*}
|
||||||
set_false_path -from {*_osd|dsp_width*}
|
set_false_path -from {*_osd|dsp_width*}
|
||||||
|
|
|
@ -235,7 +235,6 @@ wire io_clk = gp_outr[17];
|
||||||
wire io_ss0 = gp_outr[18];
|
wire io_ss0 = gp_outr[18];
|
||||||
wire io_ss1 = gp_outr[19];
|
wire io_ss1 = gp_outr[19];
|
||||||
wire io_ss2 = gp_outr[20];
|
wire io_ss2 = gp_outr[20];
|
||||||
//wire io_sdd = gp_outr[21]; // used only in ST core
|
|
||||||
|
|
||||||
wire io_osd_hdmi = io_ss1 & ~io_ss0;
|
wire io_osd_hdmi = io_ss1 & ~io_ss0;
|
||||||
wire io_fpga = ~io_ss1 & io_ss0;
|
wire io_fpga = ~io_ss1 & io_ss0;
|
||||||
|
@ -303,13 +302,16 @@ reg [8:0] coef_data;
|
||||||
reg coef_wr = 0;
|
reg coef_wr = 0;
|
||||||
|
|
||||||
wire [7:0] ARX, ARY;
|
wire [7:0] ARX, ARY;
|
||||||
reg [11:0] VSET = 0;
|
reg [11:0] VSET = 0, HSET = 0;
|
||||||
|
reg FREESCALE = 0;
|
||||||
reg [2:0] scaler_flt;
|
reg [2:0] scaler_flt;
|
||||||
reg lowlat = 0;
|
reg lowlat = 0;
|
||||||
reg cfg_dis = 0;
|
reg cfg_dis = 0;
|
||||||
|
|
||||||
reg vs_wait = 0;
|
reg vs_wait = 0;
|
||||||
|
reg [11:0] vs_line = 0;
|
||||||
|
|
||||||
|
reg scaler_out = 0;
|
||||||
always@(posedge clk_sys) begin
|
always@(posedge clk_sys) begin
|
||||||
reg [7:0] cmd;
|
reg [7:0] cmd;
|
||||||
reg has_cmd;
|
reg has_cmd;
|
||||||
|
@ -336,6 +338,7 @@ always@(posedge clk_sys) begin
|
||||||
if(cmd == 1) begin
|
if(cmd == 1) begin
|
||||||
cfg <= io_din;
|
cfg <= io_din;
|
||||||
cfg_set <= 1;
|
cfg_set <= 1;
|
||||||
|
scaler_out <= 1;
|
||||||
end
|
end
|
||||||
if(cmd == 'h20) begin
|
if(cmd == 'h20) begin
|
||||||
cfg_set <= 0;
|
cfg_set <= 0;
|
||||||
|
@ -384,9 +387,11 @@ always@(posedge clk_sys) begin
|
||||||
end
|
end
|
||||||
if(cmd == 'h25) {led_overtake, led_state} <= io_din;
|
if(cmd == 'h25) {led_overtake, led_state} <= io_din;
|
||||||
if(cmd == 'h26) vol_att <= io_din[4:0];
|
if(cmd == 'h26) vol_att <= io_din[4:0];
|
||||||
if(cmd == 'h27) VSET <= io_din[11:0];
|
if(cmd == 'h27) VSET <= io_din[11:0];
|
||||||
if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
|
if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
|
||||||
if(cmd == 'h2B) scaler_flt <= io_din[2:0];
|
if(cmd == 'h2B) scaler_flt <= io_din[2:0];
|
||||||
|
if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]};
|
||||||
|
if(cmd == 'h38) vs_line <= io_din[11:0];
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
@ -434,7 +439,7 @@ cyclonev_hps_interface_peripheral_spi_master spi
|
||||||
.ss_in_n(1)
|
.ss_in_n(1)
|
||||||
);
|
);
|
||||||
|
|
||||||
wire [63:0] f2h_irq = {HDMI_TX_VS};
|
wire [63:0] f2h_irq = {video_sync,HDMI_TX_VS};
|
||||||
cyclonev_hps_interface_interrupts interrupts
|
cyclonev_hps_interface_interrupts interrupts
|
||||||
(
|
(
|
||||||
.irq(f2h_irq)
|
.irq(f2h_irq)
|
||||||
|
@ -599,7 +604,7 @@ ascal
|
||||||
.vimax (0),
|
.vimax (0),
|
||||||
|
|
||||||
.o_clk (clk_hdmi),
|
.o_clk (clk_hdmi),
|
||||||
.o_ce (1),
|
.o_ce (scaler_out),
|
||||||
.o_r (hdmi_data[23:16]),
|
.o_r (hdmi_data[23:16]),
|
||||||
.o_g (hdmi_data[15:8]),
|
.o_g (hdmi_data[15:8]),
|
||||||
.o_b (hdmi_data[7:0]),
|
.o_b (hdmi_data[7:0]),
|
||||||
|
@ -671,6 +676,11 @@ always @(posedge clk_vid) begin
|
||||||
reg [2:0] state;
|
reg [2:0] state;
|
||||||
reg [11:0] videow;
|
reg [11:0] videow;
|
||||||
reg [11:0] videoh;
|
reg [11:0] videoh;
|
||||||
|
reg [11:0] height;
|
||||||
|
reg [11:0] width;
|
||||||
|
|
||||||
|
height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT;
|
||||||
|
width <= (HSET && (HSET < WIDTH)) ? HSET : WIDTH;
|
||||||
|
|
||||||
state <= state + 1'd1;
|
state <= state + 1'd1;
|
||||||
case(state)
|
case(state)
|
||||||
|
@ -681,22 +691,17 @@ always @(posedge clk_vid) begin
|
||||||
vmax <= FB_VMAX;
|
vmax <= FB_VMAX;
|
||||||
state<= 0;
|
state<= 0;
|
||||||
end
|
end
|
||||||
else if(ARX && ARY) begin
|
else if(ARX && ARY && !FREESCALE) begin
|
||||||
wcalc <= VSET ? (VSET*ARX)/ARY : (HEIGHT*ARX)/ARY;
|
wcalc <= (height*ARX)/ARY;
|
||||||
hcalc <= (WIDTH*ARY)/ARX;
|
hcalc <= (width*ARY)/ARX;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
hmin <= 0;
|
wcalc <= width;
|
||||||
hmax <= WIDTH - 1'd1;
|
hcalc <= height;
|
||||||
vmin <= 0;
|
|
||||||
vmax <= HEIGHT - 1'd1;
|
|
||||||
wcalc<= WIDTH;
|
|
||||||
hcalc<= HEIGHT;
|
|
||||||
state<= 0;
|
|
||||||
end
|
end
|
||||||
6: begin
|
6: begin
|
||||||
videow <= (!VSET && (wcalc > WIDTH)) ? WIDTH : wcalc[11:0];
|
videow <= (wcalc > width) ? width : wcalc[11:0];
|
||||||
videoh <= VSET ? VSET : (hcalc > HEIGHT) ? HEIGHT : hcalc[11:0];
|
videoh <= (hcalc > height) ? height : hcalc[11:0];
|
||||||
end
|
end
|
||||||
7: begin
|
7: begin
|
||||||
hmin <= ((WIDTH - videow)>>1);
|
hmin <= ((WIDTH - videow)>>1);
|
||||||
|
@ -1047,6 +1052,31 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
|
||||||
assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[7:2];
|
assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[7:2];
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
|
reg video_sync = 0;
|
||||||
|
always @(posedge clk_vid) begin
|
||||||
|
reg [11:0] line_cnt = 0;
|
||||||
|
reg [11:0] sync_line = 0;
|
||||||
|
reg [1:0] hs_cnt = 0;
|
||||||
|
reg old_hs;
|
||||||
|
|
||||||
|
old_hs <= hs_fix;
|
||||||
|
if(~old_hs & hs_fix) begin
|
||||||
|
|
||||||
|
video_sync <= (sync_line == line_cnt);
|
||||||
|
|
||||||
|
line_cnt <= line_cnt + 1'd1;
|
||||||
|
if(~hs_cnt[1]) begin
|
||||||
|
hs_cnt <= hs_cnt + 1'd1;
|
||||||
|
if(hs_cnt[0]) begin
|
||||||
|
sync_line <= (line_cnt - vs_line);
|
||||||
|
line_cnt <= 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
if(de_emu) hs_cnt <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
///////////////////////// Audio output ////////////////////////////////
|
///////////////////////// Audio output ////////////////////////////////
|
||||||
|
|
||||||
assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ;
|
assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ;
|
||||||
|
|
|
@ -185,41 +185,54 @@ end
|
||||||
wire hde = scandoubler ? ~hb_sd : ~hb_g;
|
wire hde = scandoubler ? ~hb_sd : ~hb_g;
|
||||||
wire vde = scandoubler ? ~vb_sd : ~vb_g;
|
wire vde = scandoubler ? ~vb_sd : ~vb_g;
|
||||||
|
|
||||||
|
reg [7:0] v_r,v_g,v_b;
|
||||||
|
reg v_vs,v_hs,v_de;
|
||||||
always @(posedge clk_vid) begin
|
always @(posedge clk_vid) begin
|
||||||
reg old_hde;
|
reg old_hde;
|
||||||
|
|
||||||
case(scanlines & {scanline, scanline})
|
if(ce_pix_out) begin
|
||||||
1: begin // reduce 25% = 1/2 + 1/4
|
case(scanlines & {scanline, scanline})
|
||||||
VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
|
1: begin // reduce 25% = 1/2 + 1/4
|
||||||
VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
|
v_r <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
|
||||||
VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
|
v_g <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
|
||||||
end
|
v_b <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
|
||||||
|
end
|
||||||
|
|
||||||
2: begin // reduce 50% = 1/2
|
2: begin // reduce 50% = 1/2
|
||||||
VGA_R <= {1'b0, r[7:1]};
|
v_r <= {1'b0, r[7:1]};
|
||||||
VGA_G <= {1'b0, g[7:1]};
|
v_g <= {1'b0, g[7:1]};
|
||||||
VGA_B <= {1'b0, b[7:1]};
|
v_b <= {1'b0, b[7:1]};
|
||||||
end
|
end
|
||||||
|
|
||||||
3: begin // reduce 75% = 1/4
|
3: begin // reduce 75% = 1/4
|
||||||
VGA_R <= {2'b00, r[7:2]};
|
v_r <= {2'b00, r[7:2]};
|
||||||
VGA_G <= {2'b00, g[7:2]};
|
v_g <= {2'b00, g[7:2]};
|
||||||
VGA_B <= {2'b00, b[7:2]};
|
v_b <= {2'b00, b[7:2]};
|
||||||
end
|
end
|
||||||
|
|
||||||
default: begin
|
default: begin
|
||||||
VGA_R <= r;
|
v_r <= r;
|
||||||
VGA_G <= g;
|
v_g <= g;
|
||||||
VGA_B <= b;
|
v_b <= b;
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
VGA_VS <= vs;
|
v_vs <= vs;
|
||||||
VGA_HS <= hs;
|
v_hs <= hs;
|
||||||
|
|
||||||
old_hde <= hde;
|
old_hde <= hde;
|
||||||
if(~old_hde && hde) VGA_DE <= vde;
|
if(~old_hde && hde) v_de <= vde;
|
||||||
if(old_hde && ~hde) VGA_DE <= 0;
|
if(old_hde && ~hde) v_de <= 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @(posedge clk_vid) if(ce_pix_out) begin
|
||||||
|
VGA_R <= v_r;
|
||||||
|
VGA_G <= v_g;
|
||||||
|
VGA_B <= v_b;
|
||||||
|
VGA_HS <= v_hs;
|
||||||
|
VGA_VS <= v_vs;
|
||||||
|
VGA_DE <= v_de;
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
Loading…
Reference in New Issue
Block a user