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Update sys.

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sorgelig 2020-01-22 00:55:46 +08:00
parent adfdaacd82
commit e956ad2f37
18 changed files with 2303 additions and 1776 deletions
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@ -13,7 +13,7 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Standard Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition"
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
@ -53,349 +53,4 @@ set_global_assignment -name SEED 1
source sys/sys.tcl
source sys/sys_analog.tcl
source files.qip
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to clk_sys -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "emu:emu|RESET" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "emu:emu|RESET" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[0] -to "emu:emu|RESET" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_GAP_RECORD=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_MODE=COMBINATIONAL" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY=basic,1," -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_cs" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_rs[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_rs[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_rs[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_we" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|ack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|atn" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|bsy" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cd" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|req" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_cs" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_rs[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_rs[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_rs[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_we" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|ack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|atn" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|bsy" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cd" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|req" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[1] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_cs" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[2] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_rs[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[3] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_rs[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[4] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_rs[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[5] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|bus_we" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[6] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[7] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[8] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[9] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[10] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[11] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[12] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[13] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|rdata[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[14] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|ack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[15] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|atn" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[16] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|bsy" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[17] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cd" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[18] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[19] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|req" -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|sd_buff_wr" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|sel" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|ack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|atn" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|bsy" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|cd" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|io" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|req" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|sd_buff_wr" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|sel" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "emu:emu|hps_io:hps_io|sd_ack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "emu:emu|hps_io:hps_io|sd_buff_addr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "emu:emu|hps_io:hps_io|sd_buff_addr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "emu:emu|hps_io:hps_io|sd_buff_addr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "emu:emu|hps_io:hps_io|sd_buff_addr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "emu:emu|hps_io:hps_io|sd_buff_addr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "emu:emu|hps_io:hps_io|sd_buff_addr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "emu:emu|hps_io:hps_io|sd_buff_addr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "emu:emu|hps_io:hps_io|sd_buff_addr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "emu:emu|hps_io:hps_io|sd_buff_addr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "emu:emu|hps_io:hps_io|sd_buff_dout[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "emu:emu|hps_io:hps_io|sd_buff_dout[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "emu:emu|hps_io:hps_io|sd_buff_dout[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "emu:emu|hps_io:hps_io|sd_buff_dout[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "emu:emu|hps_io:hps_io|sd_buff_dout[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "emu:emu|hps_io:hps_io|sd_buff_dout[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "emu:emu|hps_io:hps_io|sd_buff_dout[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "emu:emu|hps_io:hps_io|sd_buff_dout[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "emu:emu|hps_io:hps_io|sd_lba[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "emu:emu|hps_io:hps_io|sd_lba[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "emu:emu|hps_io:hps_io|sd_lba[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "emu:emu|hps_io:hps_io|sd_lba[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "emu:emu|hps_io:hps_io|sd_lba[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "emu:emu|hps_io:hps_io|sd_lba[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "emu:emu|hps_io:hps_io|sd_lba[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "emu:emu|hps_io:hps_io|sd_lba[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "emu:emu|hps_io:hps_io|sd_lba[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "emu:emu|hps_io:hps_io|sd_lba[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "emu:emu|hps_io:hps_io|sd_lba[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "emu:emu|hps_io:hps_io|sd_lba[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "emu:emu|hps_io:hps_io|sd_lba[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "emu:emu|hps_io:hps_io|sd_lba[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "emu:emu|hps_io:hps_io|sd_lba[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "emu:emu|hps_io:hps_io|sd_lba[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "emu:emu|hps_io:hps_io|sd_lba[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "emu:emu|hps_io:hps_io|sd_lba[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "emu:emu|hps_io:hps_io|sd_lba[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "emu:emu|hps_io:hps_io|sd_lba[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "emu:emu|hps_io:hps_io|sd_lba[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "emu:emu|hps_io:hps_io|sd_lba[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "emu:emu|hps_io:hps_io|sd_lba[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "emu:emu|hps_io:hps_io|sd_lba[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "emu:emu|hps_io:hps_io|sd_lba[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "emu:emu|hps_io:hps_io|sd_lba[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "emu:emu|hps_io:hps_io|sd_lba[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "emu:emu|hps_io:hps_io|sd_lba[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "emu:emu|hps_io:hps_io|sd_lba[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "emu:emu|hps_io:hps_io|sd_lba[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "emu:emu|hps_io:hps_io|sd_lba[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "emu:emu|hps_io:hps_io|sd_lba[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "emu:emu|hps_io:hps_io|sd_rd[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "emu:emu|hps_io:hps_io|sd_rd[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "emu:emu|hps_io:hps_io|sd_wr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "emu:emu|hps_io:hps_io|sd_wr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|sd_buff_wr" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|sel" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|ack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|atn" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|bsy" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|cd" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|io" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|req" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|sd_buff_wr" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|sel" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "emu:emu|hps_io:hps_io|sd_ack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "emu:emu|hps_io:hps_io|sd_buff_addr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "emu:emu|hps_io:hps_io|sd_buff_addr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "emu:emu|hps_io:hps_io|sd_buff_addr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "emu:emu|hps_io:hps_io|sd_buff_addr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "emu:emu|hps_io:hps_io|sd_buff_addr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "emu:emu|hps_io:hps_io|sd_buff_addr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "emu:emu|hps_io:hps_io|sd_buff_addr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "emu:emu|hps_io:hps_io|sd_buff_addr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "emu:emu|hps_io:hps_io|sd_buff_addr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "emu:emu|hps_io:hps_io|sd_buff_dout[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "emu:emu|hps_io:hps_io|sd_buff_dout[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "emu:emu|hps_io:hps_io|sd_buff_dout[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "emu:emu|hps_io:hps_io|sd_buff_dout[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "emu:emu|hps_io:hps_io|sd_buff_dout[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "emu:emu|hps_io:hps_io|sd_buff_dout[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "emu:emu|hps_io:hps_io|sd_buff_dout[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "emu:emu|hps_io:hps_io|sd_buff_dout[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "emu:emu|hps_io:hps_io|sd_lba[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "emu:emu|hps_io:hps_io|sd_lba[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "emu:emu|hps_io:hps_io|sd_lba[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "emu:emu|hps_io:hps_io|sd_lba[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "emu:emu|hps_io:hps_io|sd_lba[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "emu:emu|hps_io:hps_io|sd_lba[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "emu:emu|hps_io:hps_io|sd_lba[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "emu:emu|hps_io:hps_io|sd_lba[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "emu:emu|hps_io:hps_io|sd_lba[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "emu:emu|hps_io:hps_io|sd_lba[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "emu:emu|hps_io:hps_io|sd_lba[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "emu:emu|hps_io:hps_io|sd_lba[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "emu:emu|hps_io:hps_io|sd_lba[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "emu:emu|hps_io:hps_io|sd_lba[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "emu:emu|hps_io:hps_io|sd_lba[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "emu:emu|hps_io:hps_io|sd_lba[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "emu:emu|hps_io:hps_io|sd_lba[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "emu:emu|hps_io:hps_io|sd_lba[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "emu:emu|hps_io:hps_io|sd_lba[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "emu:emu|hps_io:hps_io|sd_lba[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "emu:emu|hps_io:hps_io|sd_lba[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "emu:emu|hps_io:hps_io|sd_lba[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "emu:emu|hps_io:hps_io|sd_lba[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "emu:emu|hps_io:hps_io|sd_lba[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "emu:emu|hps_io:hps_io|sd_lba[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "emu:emu|hps_io:hps_io|sd_lba[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "emu:emu|hps_io:hps_io|sd_lba[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "emu:emu|hps_io:hps_io|sd_lba[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "emu:emu|hps_io:hps_io|sd_lba[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "emu:emu|hps_io:hps_io|sd_lba[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "emu:emu|hps_io:hps_io|sd_lba[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "emu:emu|hps_io:hps_io|sd_lba[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "emu:emu|hps_io:hps_io|sd_rd[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "emu:emu|hps_io:hps_io|sd_rd[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "emu:emu|hps_io:hps_io|sd_wr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "emu:emu|hps_io:hps_io|sd_wr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[20] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|sd_buff_wr" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[21] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi2|sel" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[22] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|ack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[23] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|atn" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[24] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|bsy" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[25] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|cd" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[26] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|io" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[27] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|req" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[28] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|sd_buff_wr" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[29] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|scsi:scsi6|sel" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[30] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[31] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[32] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[33] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[34] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[35] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[36] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[37] -to "emu:emu|dataController_top:dc0|ncr5380:scsi|wdata[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[38] -to "emu:emu|hps_io:hps_io|sd_ack" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[39] -to "emu:emu|hps_io:hps_io|sd_buff_addr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[40] -to "emu:emu|hps_io:hps_io|sd_buff_addr[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[41] -to "emu:emu|hps_io:hps_io|sd_buff_addr[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[42] -to "emu:emu|hps_io:hps_io|sd_buff_addr[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[43] -to "emu:emu|hps_io:hps_io|sd_buff_addr[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[44] -to "emu:emu|hps_io:hps_io|sd_buff_addr[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[45] -to "emu:emu|hps_io:hps_io|sd_buff_addr[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[46] -to "emu:emu|hps_io:hps_io|sd_buff_addr[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[47] -to "emu:emu|hps_io:hps_io|sd_buff_addr[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[48] -to "emu:emu|hps_io:hps_io|sd_buff_dout[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[49] -to "emu:emu|hps_io:hps_io|sd_buff_dout[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[50] -to "emu:emu|hps_io:hps_io|sd_buff_dout[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[51] -to "emu:emu|hps_io:hps_io|sd_buff_dout[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[52] -to "emu:emu|hps_io:hps_io|sd_buff_dout[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[53] -to "emu:emu|hps_io:hps_io|sd_buff_dout[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[54] -to "emu:emu|hps_io:hps_io|sd_buff_dout[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[55] -to "emu:emu|hps_io:hps_io|sd_buff_dout[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[56] -to "emu:emu|hps_io:hps_io|sd_lba[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[57] -to "emu:emu|hps_io:hps_io|sd_lba[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[58] -to "emu:emu|hps_io:hps_io|sd_lba[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[59] -to "emu:emu|hps_io:hps_io|sd_lba[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[60] -to "emu:emu|hps_io:hps_io|sd_lba[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[61] -to "emu:emu|hps_io:hps_io|sd_lba[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[62] -to "emu:emu|hps_io:hps_io|sd_lba[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[63] -to "emu:emu|hps_io:hps_io|sd_lba[16]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[64] -to "emu:emu|hps_io:hps_io|sd_lba[17]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[65] -to "emu:emu|hps_io:hps_io|sd_lba[18]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[66] -to "emu:emu|hps_io:hps_io|sd_lba[19]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[67] -to "emu:emu|hps_io:hps_io|sd_lba[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[68] -to "emu:emu|hps_io:hps_io|sd_lba[20]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[69] -to "emu:emu|hps_io:hps_io|sd_lba[21]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[70] -to "emu:emu|hps_io:hps_io|sd_lba[22]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[71] -to "emu:emu|hps_io:hps_io|sd_lba[23]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[72] -to "emu:emu|hps_io:hps_io|sd_lba[24]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[73] -to "emu:emu|hps_io:hps_io|sd_lba[25]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[74] -to "emu:emu|hps_io:hps_io|sd_lba[26]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[75] -to "emu:emu|hps_io:hps_io|sd_lba[27]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[76] -to "emu:emu|hps_io:hps_io|sd_lba[28]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[77] -to "emu:emu|hps_io:hps_io|sd_lba[29]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[78] -to "emu:emu|hps_io:hps_io|sd_lba[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[79] -to "emu:emu|hps_io:hps_io|sd_lba[30]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[80] -to "emu:emu|hps_io:hps_io|sd_lba[31]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[81] -to "emu:emu|hps_io:hps_io|sd_lba[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[82] -to "emu:emu|hps_io:hps_io|sd_lba[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[83] -to "emu:emu|hps_io:hps_io|sd_lba[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[84] -to "emu:emu|hps_io:hps_io|sd_lba[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[85] -to "emu:emu|hps_io:hps_io|sd_lba[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[86] -to "emu:emu|hps_io:hps_io|sd_lba[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[87] -to "emu:emu|hps_io:hps_io|sd_lba[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[88] -to "emu:emu|hps_io:hps_io|sd_rd[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[89] -to "emu:emu|hps_io:hps_io|sd_rd[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[90] -to "emu:emu|hps_io:hps_io|sd_wr[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[91] -to "emu:emu|hps_io:hps_io|sd_wr[1]" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=92" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=92" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=92" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=578" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=277" -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

174
sys/alsa.sv
View File

@ -1,7 +1,7 @@
//============================================================================
//
// ALSA sound support for MiSTer
// (c)2019 Sorgelig
// (c)2019,2020 Alexey Melnikov
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
@ -22,111 +22,135 @@
module alsa
(
input reset,
output reg en_out,
input en_in,
input ram_clk,
output reg [28:0] ram_address,
output reg [7:0] ram_burstcount,
input ram_waitrequest,
input [63:0] ram_readdata,
input ram_readdatavalid,
output reg ram_read,
input clk,
output reg [31:3] ram_address,
input [63:0] ram_data,
output reg ram_req = 0,
input ram_ready,
input spi_ss,
input spi_sck,
input spi_mosi,
output spi_miso,
output reg [15:0] pcm_l,
output reg [15:0] pcm_r
);
reg spi_new = 0;
reg [127:0] spi_data;
reg [60:0] buf_info;
reg [6:0] spicnt = 0;
always @(posedge spi_sck, posedge spi_ss) begin
reg [7:0] mosi;
reg [6:0] spicnt = 0;
reg [95:0] spi_data;
if(spi_ss) spicnt <= 0;
else begin
mosi <= {mosi[6:0],spi_mosi};
spi_data[{spicnt[6:3],~spicnt[2:0]}] <= spi_mosi;
if(&spicnt) buf_info <= {spi_data[82:67],spi_data[50:35],spi_data[31:3]};
spicnt <= spicnt + 1'd1;
if(&spicnt[2:0]) begin
spi_data[{spicnt[6:3],3'b000} +:8] <= {mosi[6:0],spi_mosi};
spi_new <= &spicnt;
end
end
end
reg [31:0] buf_addr;
reg [31:0] buf_len;
reg [31:0] buf_wptr = 0;
assign spi_miso = spi_out[{spicnt[4:3],~spicnt[2:0]}];
always @(posedge ram_clk) begin
reg n1,n2,n3;
reg [127:0] data1,data2;
reg [31:0] spi_out = 0;
always @(posedge clk) if(spi_ss) spi_out <= {buf_rptr, hurryup, 8'h00};
n1 <= spi_new;
n2 <= n1;
n3 <= n2;
data1 <= spi_data;
reg [31:3] buf_addr;
reg [18:3] buf_len;
reg [18:3] buf_wptr = 0;
always @(posedge clk) begin
reg [60:0] data1,data2;
data1 <= buf_info;
data2 <= data1;
if(~n3 & n2) {buf_wptr,buf_len,buf_addr} <= data2[95:0];
if(data2 == data1) {buf_wptr,buf_len,buf_addr} <= data2;
end
reg [31:0] buf_rptr = 0;
always @(posedge ram_clk) begin
reg got_first = 0;
reg ready = 0;
reg ud = 0;
reg [31:0] readdata;
reg [2:0] hurryup = 0;
reg [18:3] buf_rptr = 0;
if(~ram_waitrequest) ram_read <= 0;
if(ram_readdatavalid && ram_burstcount) begin
ram_burstcount <= 0;
ready <= 1;
readdata <= ud ? ram_readdata[63:32] : ram_readdata[31:0];
if(buf_rptr[31:2] >= buf_len[31:2]) buf_rptr <= 0;
end
always @(posedge clk) begin
reg [18:3] len = 0;
reg [1:0] ready = 0;
reg [63:0] readdata;
reg got_first = 0;
reg [7:0] ce_cnt = 0;
reg [1:0] state = 0;
if(reset) {ready, got_first, ram_burstcount} <= 0;
else
if(buf_rptr[31:2] != buf_wptr[31:2]) begin
if(~got_first) begin
buf_rptr <= buf_wptr;
got_first <= 1;
end
else
if(!ram_burstcount && ~ram_waitrequest && ~ready && en_out == en_in) begin
ram_address <= buf_addr[31:3] + buf_rptr[31:3];
ud <= buf_rptr[2];
ram_burstcount <= 1;
ram_read <= 1;
buf_rptr <= buf_rptr + 4;
end
if(reset) begin
ready <= 0;
ce_cnt <= 0;
state <= 0;
got_first <= 0;
len <= 0;
end
else begin
if(ready & ce_48k) begin
{pcm_r,pcm_l} <= readdata;
ready <= 0;
//ramp up
if(len[18:14] && (hurryup < 1)) hurryup <= 1;
if(len[18:16] && (hurryup < 2)) hurryup <= 2;
if(len[18:17] && (hurryup < 4)) hurryup <= 4;
//ramp down
if(!len[18:15] && (hurryup > 2)) hurryup <= 2;
if(!len[18:13] && (hurryup > 1)) hurryup <= 1;
if(!len[18:10]) hurryup <= 0;
if(ce_sample && ~&ce_cnt) ce_cnt <= ce_cnt + 1'd1;
case(state)
0: if(!ce_sample) begin
if(ready) begin
if(ce_cnt) begin
{readdata[31:0],pcm_r,pcm_l} <= readdata;
ready <= ready - 1'd1;
ce_cnt <= ce_cnt - 1'd1;
end
end
else if(buf_rptr != buf_wptr) begin
if(~got_first) begin
buf_rptr <= buf_wptr;
got_first <= 1;
end
else begin
ram_address <= buf_addr + buf_rptr;
ram_req <= ~ram_req;
buf_rptr <= buf_rptr + 1'd1;
len <= (buf_wptr < buf_rptr) ? (buf_len + buf_wptr - buf_rptr) : (buf_wptr - buf_rptr);
state <= 1;
end
end
else begin
len <= 0;
ce_cnt <= 0;
hurryup <= 0;
end
end
1: if(ram_ready) begin
ready <= 2;
readdata <= ram_data;
if(buf_rptr >= buf_len) buf_rptr <= buf_rptr - buf_len;
state <= 0;
end
endcase
end
if(ce_48k) en_out <= ~en_out;
end
reg ce_48k;
always @(posedge ram_clk) begin
reg [15:0] acc = 0;
localparam F48K = 48000;
localparam F50M = 50000000;
ce_48k <= 0;
acc <= acc + 16'd48;
if(acc >= 50000) begin
acc <= acc - 16'd50000;
ce_48k <= 1;
reg ce_sample;
always @(posedge clk) begin
reg [31:0] acc = 0;
ce_sample <= 0;
acc <= acc + F48K + {hurryup,6'd0};
if(acc >= F50M) begin
acc <= acc - F50M;
ce_sample <= 1;
end
end

406
sys/arcade_video.v Normal file
View File

@ -0,0 +1,406 @@
//============================================================================
//
// Copyright (C) 2017-2020 Sorgelig
//
//============================================================================
//////////////////////////////////////////////////////////
// DW:
// 6 : 2R 2G 2B
// 8 : 3R 3G 2B
// 9 : 3R 3G 3B
// 12 : 4R 4G 4B
// 24 : 8R 8G 8B
module arcade_video #(parameter WIDTH=320, HEIGHT=240, DW=8, GAMMA=1)
(
input clk_video,
input ce_pix,
input[DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output VGA_CLK,
output VGA_CE,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE,
output HDMI_CLK,
output HDMI_CE,
output [7:0] HDMI_R,
output [7:0] HDMI_G,
output [7:0] HDMI_B,
output HDMI_HS,
output HDMI_VS,
output HDMI_DE,
output [1:0] HDMI_SL,
input [2:0] fx,
input forced_scandoubler,
input no_rotate,
input rotate_ccw,
inout [21:0] gamma_bus
);
wire [7:0] R,G,B;
wire CE,HS,VS,HBL,VBL;
wire [DW-1:0] RGB_fix;
wire VGA_HBL, VGA_VBL;
arcade_vga #(DW) vga
(
.clk_video(clk_video),
.ce_pix(ce_pix),
.RGB_in(RGB_in),
.HBlank(HBlank),
.VBlank(VBlank),
.HSync(HSync),
.VSync(VSync),
.RGB_out(RGB_fix),
.VGA_CLK(VGA_CLK),
.VGA_CE(CE),
.VGA_R(R),
.VGA_G(G),
.VGA_B(B),
.VGA_HS(HS),
.VGA_VS(VS),
.VGA_HBL(HBL),
.VGA_VBL(VBL)
);
wire [DW-1:0] RGB_out;
wire rhs,rvs,rhblank,rvblank;
screen_rotate #(WIDTH,HEIGHT,DW,4) rotator
(
.clk(VGA_CLK),
.ce(CE),
.ccw(rotate_ccw),
.video_in(RGB_fix),
.hblank(HBL),
.vblank(VBL),
.ce_out(CE | (~scandoubler & ~gamma_bus[19])),
.video_out(RGB_out),
.hsync(rhs),
.vsync(rvs),
.hblank_out(rhblank),
.vblank_out(rvblank)
);
generate
if(DW == 6) begin
wire [3:0] Rr = {RGB_out[5:4],RGB_out[5:4]};
wire [3:0] Gr = {RGB_out[3:2],RGB_out[3:2]};
wire [3:0] Br = {RGB_out[1:0],RGB_out[1:0]};
end
else if(DW == 8) begin
wire [3:0] Rr = {RGB_out[7:5],RGB_out[7]};
wire [3:0] Gr = {RGB_out[4:2],RGB_out[4]};
wire [3:0] Br = {RGB_out[1:0],RGB_out[1:0]};
end
else if(DW == 9) begin
wire [3:0] Rr = {RGB_out[8:6],RGB_out[8]};
wire [3:0] Gr = {RGB_out[5:3],RGB_out[5]};
wire [3:0] Br = {RGB_out[2:0],RGB_out[2]};
end
else if(DW == 12) begin
wire [3:0] Rr = RGB_out[11:8];
wire [3:0] Gr = RGB_out[7:4];
wire [3:0] Br = RGB_out[3:0];
end
else begin // 24
wire [7:0] Rr = RGB_out[23:16];
wire [7:0] Gr = RGB_out[15:8];
wire [7:0] Br = RGB_out[7:0];
end
endgenerate
assign HDMI_CLK = VGA_CLK;
assign HDMI_SL = sl[1:0];
wire [2:0] sl = fx ? fx - 1'd1 : 3'd0;
wire scandoubler = fx || forced_scandoubler;
video_mixer #(.LINE_LENGTH(WIDTH+4), .HALF_DEPTH(DW!=24), .GAMMA(GAMMA)) video_mixer
(
.clk_vid(HDMI_CLK),
.ce_pix(CE | (~scandoubler & ~gamma_bus[19] & ~no_rotate)),
.ce_pix_out(HDMI_CE),
.scandoubler(scandoubler),
.hq2x(fx==1),
.gamma_bus(gamma_bus),
.R(no_rotate ? ((DW!=24) ? R[7:4] : R) : Rr),
.G(no_rotate ? ((DW!=24) ? G[7:4] : G) : Gr),
.B(no_rotate ? ((DW!=24) ? B[7:4] : B) : Br),
.HSync (no_rotate ? HS : rhs),
.VSync (no_rotate ? VS : rvs),
.HBlank(no_rotate ? HBL : rhblank),
.VBlank(no_rotate ? VBL : rvblank),
.VGA_R(HDMI_R),
.VGA_G(HDMI_G),
.VGA_B(HDMI_B),
.VGA_VS(HDMI_VS),
.VGA_HS(HDMI_HS),
.VGA_DE(HDMI_DE)
);
assign VGA_CE = no_rotate ? HDMI_CE : CE;
assign VGA_R = no_rotate ? HDMI_R : R;
assign VGA_G = no_rotate ? HDMI_G : G;
assign VGA_B = no_rotate ? HDMI_B : B;
assign VGA_HS = no_rotate ? HDMI_HS : HS;
assign VGA_VS = no_rotate ? HDMI_VS : VS;
assign VGA_DE = no_rotate ? HDMI_DE : ~(HBL | VBL);
endmodule
//////////////////////////////////////////////////////////
module arcade_vga #(parameter DW)
(
input clk_video,
input ce_pix,
input [DW-1:0] RGB_in,
input HBlank,
input VBlank,
input HSync,
input VSync,
output[DW-1:0] RGB_out,
output VGA_CLK,
output reg VGA_CE,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output reg VGA_HS,
output reg VGA_VS,
output reg VGA_HBL,
output reg VGA_VBL
);
assign VGA_CLK = clk_video;
wire hs_fix,vs_fix;
sync_fix sync_v(VGA_CLK, HSync, hs_fix);
sync_fix sync_h(VGA_CLK, VSync, vs_fix);
reg [DW-1:0] RGB_fix;
always @(posedge VGA_CLK) begin
reg old_ce;
old_ce <= ce_pix;
VGA_CE <= 0;
if(~old_ce & ce_pix) begin
VGA_CE <= 1;
VGA_HS <= hs_fix;
if(~VGA_HS & hs_fix) VGA_VS <= vs_fix;
RGB_fix <= RGB_in;
VGA_HBL <= HBlank;
if(VGA_HBL & ~HBlank) VGA_VBL <= VBlank;
end
end
assign RGB_out = RGB_fix;
generate
if(DW == 6) begin
assign VGA_R = {RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4],RGB_fix[5:4]};
assign VGA_G = {RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2],RGB_fix[3:2]};
assign VGA_B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 8) begin
assign VGA_R = {RGB_fix[7:5],RGB_fix[7:5],RGB_fix[7:6]};
assign VGA_G = {RGB_fix[4:2],RGB_fix[4:2],RGB_fix[4:3]};
assign VGA_B = {RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0],RGB_fix[1:0]};
end
else if(DW == 9) begin
assign VGA_R = {RGB_fix[8:6],RGB_fix[8:6],RGB_fix[8:7]};
assign VGA_G = {RGB_fix[5:3],RGB_fix[5:3],RGB_fix[5:4]};
assign VGA_B = {RGB_fix[2:0],RGB_fix[2:0],RGB_fix[2:1]};
end
else if(DW == 12) begin
assign VGA_R = {RGB_fix[11:8],RGB_fix[11:8]};
assign VGA_G = {RGB_fix[7:4],RGB_fix[7:4]};
assign VGA_B = {RGB_fix[3:0],RGB_fix[3:0]};
end
else begin // 24
assign VGA_R = RGB_fix[23:16];
assign VGA_G = RGB_fix[15:8];
assign VGA_B = RGB_fix[7:0];
end
endgenerate
endmodule
//============================================================================
//
// Screen +90/-90 deg. rotation
// Copyright (C) 2017-2019 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
//
// Output timings are incompatible with any TV/VGA mode.
// The output is supposed to be send to scaler input.
//
module screen_rotate #(parameter WIDTH=320, HEIGHT=240, DEPTH=8, MARGIN=4)
(
input clk,
input ce,
input ccw,
input [DEPTH-1:0] video_in,
input hblank,
input vblank,
input ce_out,
output [DEPTH-1:0] video_out,
output reg hsync,
output reg vsync,
output reg hblank_out,
output reg vblank_out
);
localparam bufsize = WIDTH*HEIGHT;
localparam memsize = bufsize*2;
localparam aw = $clog2(memsize); // resolutions up to ~ 512x256
reg [aw-1:0] addr_in, addr_out;
reg we_in;
reg buff = 0;
(* ramstyle="no_rw_check" *) reg [DEPTH-1:0] ram[memsize];
always @ (posedge clk) if (en_we) ram[addr_in] <= video_in;
always @ (posedge clk) out <= ram[addr_out];
reg [DEPTH-1:0] out;
reg [DEPTH-1:0] vout;
assign video_out = vout;
wire en_we = ce & ~blank & en_x & en_y;
wire en_x = (xpos<WIDTH);
wire en_y = (ypos<HEIGHT);
integer xpos, ypos;
wire blank = hblank | vblank;
always @(posedge clk) begin
reg old_blank, old_vblank;
reg [aw-1:0] addr_row;
if(en_we) begin
addr_in <= ccw ? addr_in-HEIGHT[aw-1:0] : addr_in+HEIGHT[aw-1:0];
xpos <= xpos + 1;
end
old_blank <= blank;
old_vblank <= vblank;
if(~old_blank & blank) begin
xpos <= 0;
ypos <= ypos + 1;
addr_in <= ccw ? addr_row + 1'd1 : addr_row - 1'd1;
addr_row <= ccw ? addr_row + 1'd1 : addr_row - 1'd1;
end
if(~old_vblank & vblank) begin
if(buff) begin
addr_in <= ccw ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
addr_row <= ccw ? bufsize[aw-1:0]-HEIGHT[aw-1:0] : HEIGHT[aw-1:0]-1'd1;
end else begin
addr_in <= ccw ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
addr_row <= ccw ? bufsize[aw-1:0]+bufsize[aw-1:0]-HEIGHT[aw-1:0] : bufsize[aw-1:0]+HEIGHT[aw-1:0]-1'd1;
end
buff <= ~buff;
ypos <= 0;
xpos <= 0;
end
end
always @(posedge clk) begin
reg old_buff;
reg hs;
reg ced;
integer vbcnt;
integer xposo, yposo, xposd, yposd;
ced <= 0;
if(ce_out) begin
ced <= 1;
xposd <= xposo;
yposd <= yposo;
if(xposo == (HEIGHT + 8)) hsync <= 1;
if(xposo == (HEIGHT + 10)) hsync <= 0;
if((yposo>=MARGIN) && (yposo<WIDTH+MARGIN)) begin
if(xposo < HEIGHT) addr_out <= addr_out + 1'd1;
end
xposo <= xposo + 1;
if(xposo > (HEIGHT + 16)) begin
xposo <= 0;
if(yposo >= (WIDTH+MARGIN+MARGIN)) begin
vblank_out <= 1;
vbcnt <= vbcnt + 1;
if(vbcnt == 10 ) vsync <= 1;
if(vbcnt == 12) vsync <= 0;
end
else yposo <= yposo + 1;
old_buff <= buff;
if(old_buff != buff) begin
addr_out <= buff ? {aw{1'b0}} : bufsize[aw-1:0];
yposo <= 0;
vsync <= 0;
vbcnt <= 0;
vblank_out <= 0;
end
end
end
if(ced) begin
if((yposd<MARGIN) || (yposd>=WIDTH+MARGIN)) begin
vout <= 0;
end else begin
vout <= out;
end
if(xposd == 0) hblank_out <= 0;
if(xposd == HEIGHT) hblank_out <= 1;
end
end
endmodule

35
sys/ascal.vhd
View File

@ -164,9 +164,9 @@ ENTITY ascal IS
-- Framebuffer palette in 8bpp mode
pal_clk : IN std_logic :='0';
pal_dw : IN unsigned(23 DOWNTO 0) :=x"000000"; -- R G B
pal_dr : OUT unsigned(23 DOWNTO 0) :=x"000000";
pal_a : IN unsigned(7 DOWNTO 0) :=x"00"; -- Colour index
pal_dw : IN unsigned(47 DOWNTO 0) :=x"000000000000"; -- R1 G1 B1 R0 G0 B0
pal_dr : OUT unsigned(47 DOWNTO 0) :=x"000000000000";
pal_a : IN unsigned(6 DOWNTO 0) :="0000000"; -- Colour index/2
pal_wr : IN std_logic :='0';
------------------------------------
@ -283,11 +283,11 @@ ARCHITECTURE rtl OF ascal IS
SUBTYPE uint12 IS natural RANGE 0 TO 4095;
SUBTYPE uint13 IS natural RANGE 0 TO 8191;
TYPE arr_uv24 IS ARRAY (natural RANGE <>) OF unsigned(23 DOWNTO 0);
TYPE arr_uv48 IS ARRAY (natural RANGE <>) OF unsigned(47 DOWNTO 0);
TYPE arr_uv36 IS ARRAY (natural RANGE <>) OF unsigned(35 DOWNTO 0);
TYPE arr_int9 IS ARRAY (natural RANGE <>) OF integer RANGE -256 TO 255;
TYPE arr_uint12 IS ARRAY (natural RANGE <>) OF uint12;
----------------------------------------------------------
-- Input image
SIGNAL i_pvs,i_pfl,i_pde,i_pce : std_logic;
@ -385,8 +385,12 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_run : std_logic;
SIGNAL o_mode,o_hmode,o_vmode : unsigned(4 DOWNTO 0);
SIGNAL o_format : unsigned(5 DOWNTO 0);
SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0);
SIGNAL pal_mem : arr_uv24(0 TO 255);
SIGNAL o_fb_pal_dr : unsigned(23 DOWNTO 0);
SIGNAL o_fb_pal_dr_x2 : unsigned(47 DOWNTO 0);
SIGNAL pal_idx: unsigned(7 DOWNTO 0);
SIGNAL pal_idx_lsb: std_logic;
SIGNAL pal_mem : arr_uv48(0 TO 127);
ATTRIBUTE ramstyle of pal_mem : signal is "no_rw_check";
SIGNAL o_htotal,o_hsstart,o_hsend : uint12;
SIGNAL o_hmin,o_hmax,o_hdisp : uint12;
SIGNAL o_hsize,o_vsize : uint12;
@ -422,7 +426,8 @@ ARCHITECTURE rtl OF ascal IS
SIGNAL o_wr : unsigned(3 DOWNTO 0);
SIGNAL o_hcpt,o_vcpt,o_vcpt_pre,o_vcpt_pre2,o_vcpt_pre3 : uint12;
SIGNAL o_ihsize,o_ivsize : uint12;
SIGNAL o_ihsize_temp, o_ihsize_temp2 : natural RANGE 0 TO 32767;
SIGNAL o_vfrac,o_hfrac,o_hfrac1,o_hfrac2,o_hfrac3,o_hfrac4 : unsigned(11 DOWNTO 0);
SIGNAL o_hacc,o_hacc_ini,o_hacc_next,o_vacc,o_vacc_next,o_vacc_ini : natural RANGE 0 TO 4*OHRES-1;
SIGNAL o_hsv,o_vsv,o_dev,o_pev : unsigned(0 TO 5);
@ -1709,8 +1714,9 @@ BEGIN
o_format<=o_fb_format;
END IF;
o_hburst<=(o_ihsize * (to_integer(o_format(2 DOWNTO 0)) - 2) +
N_BURST - 1) / N_BURST;
o_ihsize_temp <= o_ihsize * to_integer(o_format(2 DOWNTO 0) - 2);
o_ihsize_temp2 <= (o_ihsize_temp + N_BURST - 1);
o_hburst <= o_ihsize_temp2 / N_BURST;
IF o_vsv(1)='1' AND o_vsv(0)='0' AND o_bufup0='1' THEN
o_obuf0<=buf_next(o_obuf0,o_ibuf0);
@ -2043,10 +2049,11 @@ BEGIN
pal_dr<=pal_mem(to_integer(pal_a));
END IF;
END PROCESS;
o_fb_pal_dr<=
pal_mem(to_integer(shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7)))
WHEN rising_edge(o_clk);
pal_idx <= shift_opack(o_acpt4,o_shift,o_dr,o_format)(0 TO 7);
pal_idx_lsb <= pal_idx(0) WHEN rising_edge(o_clk);
o_fb_pal_dr_x2 <= pal_mem(to_integer(pal_idx(7 DOWNTO 1))) WHEN rising_edge(o_clk);
o_fb_pal_dr <= o_fb_pal_dr_x2(47 DOWNTO 24) WHEN pal_idx_lsb = '1' ELSE o_fb_pal_dr_x2(23 DOWNTO 0);
END GENERATE GenPal;
GenNoPal:IF NOT PALETTE GENERATE

28
sys/build_id.tcl
View File

@ -1,25 +1,29 @@
# Build TimeStamp Verilog Module
# Jeff Wiencrot - 8/1/2011
# Sorgelig - 02/11/2019
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
set buildDate "`define BUILD_DATE \"[clock format [ clock seconds ] -format %y%m%d]\""
# Create a Verilog file for output
set outputFileName "build_id.v"
set outputFile [open $outputFileName "w"]
set fileData ""
if { [file exists $outputFileName]} {
set outputFile [open $outputFileName "r"]
set fileData [read $outputFile]
close $outputFile
}
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
if {$buildDate ne $fileData} {
set outputFile [open $outputFileName "w"]
puts -nonewline $outputFile $buildDate
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated: [pwd]/$outputFileName: $buildDate"
}
}
# Build CDF file

108
sys/ddr_svc.sv Normal file
View File

@ -0,0 +1,108 @@
//
// Copyright (c) 2020 Alexey Melnikov
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ------------------------------------------
//
// 16-bit version
module ddr_svc
(
input clk,
input ram_waitrequest,
output [7:0] ram_burstcnt,
output [28:0] ram_addr,
input [63:0] ram_readdata,
input ram_read_ready,
output reg ram_read,
output [63:0] ram_writedata,
output [7:0] ram_byteenable,
output reg ram_write,
output [7:0] ram_bcnt,
input [31:3] ch0_addr,
input [7:0] ch0_burst,
output [63:0] ch0_data,
input ch0_req,
output ch0_ready,
input [31:3] ch1_addr,
input [7:0] ch1_burst,
output [63:0] ch1_data,
input ch1_req,
output ch1_ready
);
assign ram_burstcnt = ram_burst;
assign ram_byteenable = 8'hFF;
assign ram_addr = ram_address;
assign ram_writedata = 0;
assign ch0_data = ram_q[0];
assign ch1_data = ram_q[1];
assign ch0_ready = ready[0];
assign ch1_ready = ready[1];
reg [7:0] ram_burst;
reg [63:0] ram_q[2];
reg [31:3] ram_address;
reg [1:0] ack = 0;
reg [1:0] ready;
reg state = 0;
reg ch = 0;
always @(posedge clk) begin
ready <= 0;
if(!ram_waitrequest) begin
ram_read <= 0;
ram_write <= 0;
case(state)
0: if(ch0_req != ack[0]) begin
ack[0] <= ch0_req;
ram_address <= ch0_addr;
ram_burst <= ch0_burst;
ram_read <= 1;
ch <= 0;
ram_bcnt <= 8'hFF;
state <= 1;
end
else if(ch1_req != ack[1]) begin
ack[1] <= ch1_req;
ram_address <= ch1_addr;
ram_burst <= ch1_burst;
ram_read <= 1;
ch <= 1;
ram_bcnt <= 8'hFF;
state <= 1;
end
1: begin
if(ram_read_ready) begin
ram_bcnt <= ram_bcnt + 1'd1;
ram_q[ch] <= ram_readdata;
ready[ch] <= 1;
if ((ram_bcnt+2'd2) == ram_burst) state <= 0;
end
end
endcase
end
end
endmodule

86
sys/fbpal.sv
View File

@ -1,86 +0,0 @@
//============================================================================
//
// Framebuffer Palette support for MiSTer
// (c)2019 Sorgelig
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module fbpal
(
input reset,
input en_in,
output reg en_out,
input ram_clk,
output reg [28:0] ram_address,
output reg [7:0] ram_burstcount,
input ram_waitrequest,
input [63:0] ram_readdata,
input ram_readdatavalid,
output reg ram_read,
input [31:0] fb_address,
input pal_en,
output reg [7:0] pal_a,
output reg [23:0] pal_d,
output reg pal_wr
);
reg [31:0] base_addr;
always @(posedge ram_clk) base_addr <= fb_address - 4096;
reg [6:0] buf_rptr = 0;
always @(posedge ram_clk) begin
reg [23:0] odd_d;
if(~pal_a[0] & pal_wr) {pal_a[0], pal_d} <= {1'b1, odd_d};
else pal_wr <= 0;
if(~ram_waitrequest) ram_read <= 0;
if(pal_en & ~reset) begin
if(ram_burstcount) begin
if(ram_readdatavalid) begin
ram_burstcount <= 0;
odd_d <= ram_readdata[55:32];
pal_d <= ram_readdata[23:0];
pal_a <= {buf_rptr, 1'b0};
pal_wr <= 1;
en_out <= en_in;
buf_rptr <= buf_rptr + 1'd1;
end
end
else begin
if(~ram_waitrequest && en_out != en_in) begin
ram_address <= base_addr[31:3] + buf_rptr;
ram_burstcount <= 1;
ram_read <= 1;
end
end
end
else begin
en_out <= en_in;
buf_rptr <= 0;
ram_burstcount <= 0;
end
end
endmodule

122
sys/gamma_corr.sv Normal file
View File

@ -0,0 +1,122 @@
module gamma_corr
(
input clk_sys,
input clk_vid,
input ce_pix,
input gamma_en,
input gamma_wr,
input [9:0] gamma_wr_addr,
input [7:0] gamma_value,
input HSync,
input VSync,
input HBlank,
input VBlank,
input [23:0] RGB_in,
output reg HSync_out,
output reg VSync_out,
output reg HBlank_out,
output reg VBlank_out,
output reg [23:0] RGB_out
);
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve[768];
always @(posedge clk_sys) if (gamma_wr) gamma_curve[gamma_wr_addr] <= gamma_value;
always @(posedge clk_vid) gamma <= gamma_curve[gamma_index];
reg [9:0] gamma_index;
reg [7:0] gamma;
always @(posedge clk_vid) begin
reg [7:0] R_in, G_in, B_in;
reg [7:0] R_gamma, G_gamma;
reg hs,vs,hb,vb;
reg [1:0] ctr = 0;
if(ce_pix) begin
{R_in,G_in,B_in} <= RGB_in;
hs <= HSync; vs <= VSync;
hb <= HBlank; vb <= VBlank;
RGB_out <= gamma_en ? {R_gamma,G_gamma,gamma} : {R_in,G_in,B_in};
HSync_out <= hs; VSync_out <= vs;
HBlank_out <= hb; VBlank_out <= vb;
ctr <= 1;
gamma_index <= {2'b00,RGB_in[23:16]};
end
if (|ctr) ctr <= ctr + 1'd1;
case(ctr)
1: begin gamma_index <= {2'b01,G_in}; end
2: begin R_gamma <= gamma; gamma_index <= {2'b10,B_in}; end
3: begin G_gamma <= gamma; end
endcase
end
endmodule
module gamma_fast
(
input clk_vid,
input ce_pix,
inout [21:0] gamma_bus,
input HSync,
input VSync,
input HBlank,
input VBlank,
input DE,
input [23:0] RGB_in,
output reg HSync_out,
output reg VSync_out,
output reg HBlank_out,
output reg VBlank_out,
output reg DE_out,
output reg [23:0] RGB_out
);
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_r[256];
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_g[256];
(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_b[256];
assign gamma_bus[21] = 1;
wire clk_sys = gamma_bus[20];
wire gamma_en = gamma_bus[19];
wire gamma_wr = gamma_bus[18];
wire [9:0] gamma_wr_addr = gamma_bus[17:8];
wire [7:0] gamma_value = gamma_bus[7:0];
always @(posedge clk_sys) if (gamma_wr) begin
case(gamma_wr_addr[9:8])
0: gamma_curve_r[gamma_wr_addr[7:0]] <= gamma_value;
1: gamma_curve_g[gamma_wr_addr[7:0]] <= gamma_value;
2: gamma_curve_b[gamma_wr_addr[7:0]] <= gamma_value;
endcase
end
reg [7:0] gamma_index_r,gamma_index_g,gamma_index_b;
always @(posedge clk_vid) begin
reg [7:0] R_in, G_in, B_in;
reg [7:0] R_gamma, G_gamma;
reg hs,vs,hb,vb,de;
if(ce_pix) begin
{gamma_index_r,gamma_index_g,gamma_index_b} <= RGB_in;
hs <= HSync; vs <= VSync;
hb <= HBlank; vb <= VBlank;
de <= DE;
RGB_out <= gamma_en ? {gamma_curve_r[gamma_index_r],gamma_curve_g[gamma_index_g],gamma_curve_b[gamma_index_b]}
: {gamma_index_r,gamma_index_g,gamma_index_b};
HSync_out <= hs; VSync_out <= vs;
HBlank_out <= hb; VBlank_out <= vb;
DE_out <= de;
end
end
endmodule

1828
sys/hps_io.v
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File diff suppressed because it is too large Load Diff

254
sys/hq2x.sv
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@ -8,9 +8,7 @@
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
// altera message_off 10030
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
@ -34,24 +32,29 @@ localparam AWIDTH = $clog2(LENGTH)-1;
localparam DWIDTH = HALF_DEPTH ? 11 : 23;
localparam DWIDTH1 = DWIDTH+1;
wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
(* romstyle = "MLAB" *) reg [5:0] hqTable[256];
initial begin
hqTable = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
end
wire [5:0] hqrule = hqTable[nextpatt];
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
reg [23:0] A, B, D, F, G, H;
@ -70,7 +73,7 @@ wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
wire [23:0] blend_result_pre;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result_pre);
Blend blender(clk, ce_in, disable_hq2x ? 6'd0 : hqrule, Curr0, X, B, D, F, H, blend_result_pre);
wire [DWIDTH:0] Curr20tmp;
wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
@ -146,12 +149,28 @@ reg [AWIDTH:0] offs;
always @(posedge clk) begin
reg old_reset_line;
reg old_reset_frame;
reg [3:0] wrdata_finished;
reg [AWIDTH+1:0] waddr;
wrout_en <= 0;
wrin_en <= 0;
if(ce_in) begin
// blend_result has been delayed by 4 cycles
case(cyc)
0: wrdata[DWIDTH:0] <= blend_result;
1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
2: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
endcase
wrdata_finished <= wrdata_finished << 1;
if(wrdata_finished[3]) begin
wrout_en <= 1;
wrout_addr <= waddr;
end
if(~&offs) begin
if (cyc == 1) begin
Prev2 <= Curr20;
@ -162,17 +181,10 @@ always @(posedge clk) begin
wrin_en <= 1;
end
case({cyc[1],^cyc})
0: wrdata[DWIDTH:0] <= blend_result;
1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
2: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
3: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
endcase
if(cyc==3) begin
offs <= offs + 1'd1;
wrout_addr <= {offs, curbuf};
wrout_en <= 1;
waddr <= {offs, curbuf};
wrdata_finished[0] <= 1;
end
end
@ -225,26 +237,27 @@ module hq2x_in #(parameter LENGTH, parameter DWIDTH)
input wren
);
localparam AWIDTH = $clog2(LENGTH)-1;
wire [DWIDTH:0] out[2];
assign q0 = out[rdbuf0];
assign q1 = out[rdbuf1];
localparam AWIDTH = $clog2(LENGTH)-1;
wire [DWIDTH:0] out[2];
assign q0 = out[rdbuf0];
assign q1 = out[rdbuf1];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output logic [DWIDTH:0] q
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output reg [DWIDTH:0] q
);
logic [DWIDTH:0] ram[0:NUMWORDS-1];
reg [DWIDTH:0] ram[0:NUMWORDS-1];
always_ff@(posedge clock) begin
if(wren) ram[wraddress] <= data;
@ -259,15 +272,14 @@ module DiffCheck
(
input [23:0] rgb1,
input [23:0] rgb2,
output result
output result
);
wire [7:0] r = rgb1[7:1] - rgb2[7:1];
wire [7:0] g = rgb1[15:9] - rgb2[15:9];
wire [7:0] b = rgb1[23:17] - rgb2[23:17];
wire [8:0] t = $signed(r) + $signed(b);
wire [8:0] gx = {g[7], g};
wire [9:0] y = $signed(t) + $signed(gx);
wire [9:0] y = $signed(t) + $signed({g[7], g});
wire [8:0] u = $signed(r) - $signed(b);
wire [9:0] v = $signed({g, 1'b0}) - $signed(t);
@ -275,48 +287,19 @@ module DiffCheck
wire y_inside = (y < 10'h60 || y >= 10'h3a0);
// if u is inside (-16, 16)
wire u_inside = (u < 9'h10 || u >= 9'h1f0);
wire u_inside = (!u[8:4] || &u[8:4]); //(u < 9'h10 || u >= 9'h1f0);
// if v is inside (-24, 24)
wire v_inside = (v < 10'h18 || v >= 10'h3e8);
assign result = !(y_inside && u_inside && v_inside);
endmodule
module InnerBlend
(
input [8:0] Op,
input [7:0] A,
input [7:0] B,
input [7:0] C,
output [7:0] O
);
function [10:0] mul8x3;
input [7:0] op1;
input [2:0] op2;
begin
mul8x3 = 11'd0;
if(op2[0]) mul8x3 = mul8x3 + op1;
if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
end
endfunction
wire OpOnes = Op[4];
wire [10:0] Amul = mul8x3(A, Op[7:5]);
wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0});
wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0});
wire [10:0] At = Amul;
wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
wire [11:0] Res = {At, 1'b0} + Bt + Ct;
assign O = Op[8] ? A : Res[11:4];
endmodule
module Blend
(
input clk,
input clk_en,
input [5:0] rule,
input disable_hq2x,
input [23:0] E,
input [23:0] A,
input [23:0] B,
@ -326,66 +309,63 @@ module Blend
output [23:0] Result
);
reg [1:0] input_ctrl;
reg [8:0] op;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
localparam BLEND1 = 7'b110_10_00; // (A * 12 + B * 4 ) >> 4
localparam BLEND2 = 7'b100_10_10; // (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 7'b101_10_01; // (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 7'b110_01_01; // (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 7'b010_11_11; // (A * 4 + B * 6 + C * 6) >> 4
localparam BLEND6 = 7'b111_00_00; // (A * 14 + B * 1 + C * 1) >> 4
always @* begin
case({!is_diff, rule[5:2]})
1,17: {op, input_ctrl} = {BLEND1, AB};
2,18: {op, input_ctrl} = {BLEND1, DB};
3,19: {op, input_ctrl} = {BLEND1, BD};
4,20: {op, input_ctrl} = {BLEND2, DB};
5,21: {op, input_ctrl} = {BLEND2, AB};
6,22: {op, input_ctrl} = {BLEND2, AD};
8: {op, input_ctrl} = {BLEND0, 2'bxx};
9: {op, input_ctrl} = {BLEND0, 2'bxx};
10: {op, input_ctrl} = {BLEND0, 2'bxx};
11: {op, input_ctrl} = {BLEND1, AB};
12: {op, input_ctrl} = {BLEND1, AB};
13: {op, input_ctrl} = {BLEND1, AB};
14: {op, input_ctrl} = {BLEND1, DB};
15: {op, input_ctrl} = {BLEND1, BD};
24: {op, input_ctrl} = {BLEND2, DB};
25: {op, input_ctrl} = {BLEND5, DB};
26: {op, input_ctrl} = {BLEND6, DB};
27: {op, input_ctrl} = {BLEND2, DB};
28: {op, input_ctrl} = {BLEND4, DB};
29: {op, input_ctrl} = {BLEND5, DB};
30: {op, input_ctrl} = {BLEND3, BD};
31: {op, input_ctrl} = {BLEND3, DB};
default: {op, input_ctrl} = {11{1'bx}};
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] = 1;
reg [23:0] a,b,d,e,h,f;
reg [3:0] bl_rule;
reg [1:0] df_rule;
always @(posedge clk) if (clk_en) begin
{bl_rule,df_rule} <= rule;
a <= A; b <= B; d <= D; e <= E; f <= F; h <= H;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
wire [23:0] Input1 = E;
wire [23:0] Input2 = !input_ctrl[1] ? A :
!input_ctrl[0] ? D : B;
wire is_diff;
DiffCheck diff_checker(df_rule[1] ? b : h, df_rule[0] ? d : f, is_diff);
reg [23:0] i10,i20,i30;
reg [6:0] op0;
always @(posedge clk) if (clk_en) begin
i10 <= e;
case({!is_diff, bl_rule})
1,11,12,13,17: {op0, i20, i30} <= {BLEND1, a, 24'd0};
2,14,18: {op0, i20, i30} <= {BLEND1, d, 24'd0};
3,15,19: {op0, i20, i30} <= {BLEND1, b, 24'd0};
4,20,24,27: {op0, i20, i30} <= {BLEND2, d, b};
5,21: {op0, i20, i30} <= {BLEND2, a, b};
6,22: {op0, i20, i30} <= {BLEND2, a, d};
25,29: {op0, i20, i30} <= {BLEND5, d, b};
26: {op0, i20, i30} <= {BLEND6, d, b};
28: {op0, i20, i30} <= {BLEND4, d, b};
30: {op0, i20, i30} <= {BLEND3, b, d};
31: {op0, i20, i30} <= {BLEND3, d, b};
default: {op0, i20, i30} <= {BLEND1, e, 24'd0};
endcase
end
reg [23:0] i1,i2,i3;
reg [6:0] op;
always @(posedge clk) if (clk_en) begin
op <= op0; i1 <= i10; i2 <= i20; i3 <= i30;
end
function [34:0] mul24x3;
input [23:0] op1;
input [2:0] op2;
begin
mul24x3 = 0;
if(op2[0]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0]};
if(op2[1]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 1'b0};
if(op2[2]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 2'b00};
end
endfunction
wire [35:0] res = {mul24x3(i1, op[6:4]), 1'b0} + mul24x3(i2, {op[3:2], !op[3:2]}) + mul24x3(i3, {op[1:0], !op[3:2]});
always @(posedge clk) if (clk_en) Result <= {res[35:28],res[23:16],res[11:4]};
wire [23:0] Input3 = !input_ctrl[0] ? B : D;
InnerBlend inner_blend1(op, Input1[7:0], Input2[7:0], Input3[7:0], Result[7:0]);
InnerBlend inner_blend2(op, Input1[15:8], Input2[15:8], Input3[15:8], Result[15:8]);
InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]);
endmodule

103
sys/osd.v
View File

@ -22,27 +22,29 @@ module osd
);
parameter OSD_COLOR = 3'd4;
parameter OSD_X_OFFSET = 12'd0;
parameter OSD_Y_OFFSET = 12'd0;
localparam OSD_WIDTH = 12'd256;
localparam OSD_HEIGHT = 12'd64;
`ifdef OSD_HEADER
localparam OSD_HDR = 12'd32;
localparam OSD_HDR = 12'd24;
`else
localparam OSD_HDR = 12'd0;
`endif
reg osd_enable;
reg [7:0] osd_buffer[OSD_HDR ? (4096+1024) : 4096];
(* ramstyle="no_rw_check" *) reg [7:0] osd_buffer[OSD_HDR ? (4096+1024) : 4096];
reg info = 0;
reg [8:0] infoh;
reg [8:0] infow;
reg [11:0] infox;
reg [21:0] infoy;
reg [21:0] hrheight;
reg [21:0] osd_h;
reg [21:0] osd_t;
reg [21:0] osd_w;
reg [1:0] rot = 0;
always@(posedge clk_sys) begin
reg [12:0] bcnt;
@ -51,7 +53,9 @@ always@(posedge clk_sys) begin
reg old_strobe;
reg highres = 0;
hrheight <= info ? infoh : ((OSD_HEIGHT<<highres)+OSD_HDR);
osd_t <= rot[0] ? OSD_WIDTH : (OSD_HEIGHT<<1);
osd_h <= rot[0] ? (info ? infow : OSD_WIDTH) : info ? infoh : (OSD_HEIGHT<<highres);
osd_w <= rot[0] ? (info ? infoh : (OSD_HEIGHT<<highres)) : (info ? infow : OSD_WIDTH);
old_strobe <= io_strobe;
@ -83,6 +87,7 @@ always@(posedge clk_sys) begin
if(bcnt == 1) infoy <= io_din[11:0];
if(bcnt == 2) infow <= {io_din[5:0], 3'b000};
if(bcnt == 3) infoh <= {io_din[5:0], 3'b000};
if(bcnt == 4) rot <= io_din[1:0];
end
// command 0x20: OSDCMDWRITE
@ -95,22 +100,22 @@ always@(posedge clk_sys) begin
end
(* direct_enable *) reg ce_pix;
always @(negedge clk_video) begin
integer cnt = 0;
integer pixsz, pixcnt;
always @(posedge clk_video) begin
reg [21:0] cnt = 0;
reg [21:0] pixsz, pixcnt;
reg deD;
cnt <= cnt + 1;
cnt <= cnt + 1'd1;
deD <= de_in;
pixcnt <= pixcnt + 1;
pixcnt <= pixcnt + 1'd1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(~deD && de_in) cnt <= 0;
if(deD && ~de_in) begin
pixsz <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0;
pixsz <= (((cnt+1'b1) >> (9-rot[0])) > 1) ? (((cnt+1'b1) >> (9-rot[0])) - 1'd1) : 22'd0;
pixcnt <= 0;
end
end
@ -119,19 +124,24 @@ reg [2:0] osd_de;
reg osd_pixel;
reg [21:0] v_cnt;
reg v_cnt_below320, v_cnt_below640, v_cnt_below960;
reg v_cnt_half, v_cnt_single, v_cnt_double, v_cnt_triple;
reg [21:0] v_osd_start_320, v_osd_start_640, v_osd_start_960, v_osd_start_other;
reg [21:0] v_osd_start_h, v_osd_start_s, v_osd_start_d, v_osd_start_t, v_osd_start_q;
wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR);
// pipeline the comparisons a bit
always @(posedge clk_video) if(ce_pix) begin
v_cnt_below320 <= v_cnt < 320;
v_cnt_below640 <= v_cnt < 640;
v_cnt_below960 <= v_cnt < 960;
v_osd_start_320 <= ((v_cnt-hrheight)>>1) + OSD_Y_OFFSET;
v_osd_start_640 <= ((v_cnt-(hrheight<<1))>>1) + OSD_Y_OFFSET;
v_osd_start_960 <= ((v_cnt-(hrheight + (hrheight<<1)))>>1) + OSD_Y_OFFSET;
v_osd_start_other <= ((v_cnt-(hrheight<<2))>>1) + OSD_Y_OFFSET;
v_cnt_half <= v_cnt < osd_t;
v_cnt_single <= v_cnt < 320;
v_cnt_double <= v_cnt < 640;
v_cnt_triple <= v_cnt < 960;
v_osd_start_h <= ((v_cnt-(osd_h_hdr>>1))>>1);
v_osd_start_s <= ((v_cnt-osd_h_hdr)>>1);
v_osd_start_d <= ((v_cnt-(osd_h_hdr<<1))>>1);
v_osd_start_t <= ((v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1);
v_osd_start_q <= ((v_cnt-(osd_h_hdr<<2))>>1);
end
always @(posedge clk_video) begin
@ -145,22 +155,31 @@ always @(posedge clk_video) begin
reg [21:0] h_osd_start;
reg [21:0] v_osd_start;
reg [21:0] osd_hcnt;
reg [21:0] osd_hcnt2;
reg osd_de1,osd_de2;
reg [1:0] osd_en;
reg f1;
reg half;
if(ce_pix) begin
deD <= de_in;
if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1;
if(~&osd_hcnt) osd_hcnt <= osd_hcnt + 1'd1;
if(~&osd_hcnt2) osd_hcnt2 <= osd_hcnt2 + 1'd1;
if (h_cnt == h_osd_start) begin
osd_de[0] <= osd_en[1] && hrheight && (info ? (osd_vcnt < hrheight) :
(!osd_vcnt[11:7] || (osd_vcnt[11] && osd_vcnt[7] && (osd_vcnt[6:0] >= 4) && (osd_vcnt[6:0] < 19))));
osd_de[0] <= osd_en[1] && osd_h && (
osd_vcnt[11] ? (osd_vcnt[7] && (osd_vcnt[6:0] >= 4) && (osd_vcnt[6:0] < 19)) :
(info && (rot == 3)) ? !osd_vcnt[21:8] :
(osd_vcnt < osd_h)
);
osd_hcnt <= 0;
osd_hcnt2 <= 0;
if(info && rot == 1) osd_hcnt2 <= 22'd128-infoh;
end
if (osd_hcnt+1 == (info ? infow : OSD_WIDTH)) osd_de[0] <= 0;
if (osd_hcnt+1 == osd_w) osd_de[0] <= 0;
// falling edge of de
if(!de_in && deD) dsp_width <= h_cnt[21:0];
@ -169,7 +188,7 @@ always @(posedge clk_video) begin
if(de_in && !deD) begin
h_cnt <= 0;
v_cnt <= v_cnt + 1'd1;
h_osd_start <= info ? infox : (((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET - 2'd2);
h_osd_start <= info ? (rot[0] ? infoy : infox) : (((dsp_width - osd_w)>>1) - 2'd2);
if(h_cnt > {dsp_width, 2'b00}) begin
v_cnt <= 1;
@ -179,21 +198,27 @@ always @(posedge clk_video) begin
osd_en <= (osd_en << 1) | osd_enable;
if(~osd_enable) osd_en <= 0;
if(v_cnt_below320) begin
half <= 0;
if(v_cnt_half) begin
multiscan <= 0;
v_osd_start <= info ? infoy : v_osd_start_320;
v_osd_start <= info ? (rot[0] ? infox : infoy) : v_osd_start_h;
half <= 1;
end
else if(v_cnt_below640) begin
else if(v_cnt_single | (rot[0] & v_cnt_double)) begin
multiscan <= 0;
v_osd_start <= info ? (rot[0] ? infox : infoy) : v_osd_start_s;
end
else if(rot[0] ? v_cnt_triple : v_cnt_double) begin
multiscan <= 1;
v_osd_start <= info ? (infoy<<1) : v_osd_start_640;
v_osd_start <= info ? (rot[0] ? (infox<<1) : (infoy<<1)) : v_osd_start_d;
end
else if(v_cnt_below960) begin
else if(v_cnt_triple | rot[0]) begin
multiscan <= 2;
v_osd_start <= info ? (infoy + (infoy << 1)) : v_osd_start_960;
v_osd_start <= info ? (rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1))) : v_osd_start_t;
end
else begin
multiscan <= 3;
v_osd_start <= info ? (infoy<<2) : v_osd_start_other;
v_osd_start <= info ? (rot[0] ? (infox<<2) : (infoy<<2)) : v_osd_start_q;
end
end
end
@ -201,14 +226,18 @@ always @(posedge clk_video) begin
osd_div <= osd_div + 1'd1;
if(osd_div == multiscan) begin
osd_div <= 0;
if(~osd_vcnt[10]) osd_vcnt <= osd_vcnt + 1'd1;
if(~osd_vcnt[10]) osd_vcnt <= osd_vcnt + 1'd1 + half;
if(osd_vcnt == 'b100010011111 && ~info) osd_vcnt <= 0;
end
if(v_osd_start == v_cnt) {osd_div, osd_vcnt} <= OSD_HDR ? {~info, 3'b000, ~info, 7'b0000000} : 22'd0;
if(v_osd_start == v_cnt) begin
{osd_div,osd_vcnt} <= 0;
if(info && rot == 3) osd_vcnt <= 22'd256-infow;
else if(OSD_HDR && !rot) osd_vcnt <= {~info, 3'b000, ~info, 7'b0000000};
end
end
osd_byte <= osd_buffer[{osd_vcnt[7:3], osd_hcnt[7:0]}];
osd_pixel <= osd_byte[osd_vcnt[2:0]];
osd_byte <= osd_buffer[rot[0] ? ({osd_hcnt2[6:3], osd_vcnt[7:0]} ^ { {4{~rot[1]}}, {8{rot[1]}} }) : {osd_vcnt[7:3], osd_hcnt[7:0]}];
osd_pixel <= osd_byte[rot[0] ? ((osd_hcnt2[2:0]-1'd1) ^ {3{~rot[1]}}) : osd_vcnt[2:0]];
osd_de[2:1] <= osd_de[1:0];
end
end

12
sys/scandoubler.v
View File

@ -22,7 +22,7 @@
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input clk_vid,
input ce_pix,
output ce_pix_out,
@ -59,7 +59,7 @@ wire [7:0] pc_in = pix_in_cnt + 1'b1;
reg [7:0] pixsz, pixsz2, pixsz4 = 0;
reg ce_x4i, ce_x1i;
always @(negedge clk_sys) begin
always @(posedge clk_vid) begin
reg old_ce, valid, hs;
if(~&pix_len) pix_len <= pl;
@ -94,7 +94,7 @@ end
reg req_line_reset;
reg [DWIDTH:0] r_d, g_d, b_d;
always @(posedge clk_sys) begin
always @(posedge clk_vid) begin
if(ce_x1i) begin
req_line_reset <= hb_in;
r_d <= r_in;
@ -105,7 +105,7 @@ end
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.clk(clk_vid),
.ce_in(ce_x4i),
.inputpixel({b_d,g_d,r_d}),
@ -124,7 +124,7 @@ reg [7:0] pix_out_cnt = 0;
wire [7:0] pc_out = pix_out_cnt + 1'b1;
reg ce_x4o, ce_x2o;
always @(negedge clk_sys) begin
always @(posedge clk_vid) begin
reg hs;
if(~&pix_out_cnt) pix_out_cnt <= pc_out;
@ -148,7 +148,7 @@ reg [1:0] sd_line;
reg [3:0] vbo;
reg [3:0] vso;
reg [8:0] hbo;
always @(posedge clk_sys) begin
always @(posedge clk_vid) begin
reg [31:0] hcnt;
reg [30:0] sd_hcnt;

4
sys/sys.qip
View File

@ -3,12 +3,13 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) s
set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) sys_top.sdc ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ascal.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) pll_hdmi_adj.vhd ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) fbpal.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hq2x.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scanlines.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_cleaner.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) gamma_corr.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) video_mixer.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_video.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) vga_out.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) i2c.v ]
@ -20,6 +21,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) l
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sigma_delta_dac.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) hdmi_config.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) mcp23009.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) ddr_svc.sv ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sysmem.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) sd_card.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) hps_io.v ]

46
sys/sys.tcl
View File

@ -99,12 +99,9 @@ set_location_assignment PIN_W14 -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_*
#============================================================
@ -132,41 +129,17 @@ set_location_assignment PIN_E11 -to FPGA_CLK3_50
#============================================================
# HDMI
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_*
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_D[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_CLK
set_location_assignment PIN_U10 -to HDMI_I2C_SCL
set_location_assignment PIN_AA4 -to HDMI_I2C_SDA
set_location_assignment PIN_T13 -to HDMI_I2S
@ -245,7 +218,6 @@ set_location_assignment PIN_W20 -to SW[3]
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALSPIMASTER_X52_Y72_N111 -entity sys_top -to spi
set_instance_assignment -name HPS_LOCATION HPSINTERFACEPERIPHERALUART_X52_Y67_N111 -entity sys_top -to uart
set_location_assignment FRACTIONALPLL_X89_Y1_N0 -to emu:emu|pll:pll|pll_0002:pll_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"

7
sys/sys_dual_sdram.tcl
View File

@ -42,12 +42,9 @@ set_location_assignment PIN_AE17 -to SDRAM2_A[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM2_*
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM2_*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_A*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_BA*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_DQM*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_n*
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM2_*
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM2_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM2_DQ[*]
set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM2_*
set_global_assignment -name VERILOG_MACRO "DUAL_SDRAM=1"

27
sys/sys_top.sdc
View File

@ -6,11 +6,6 @@ create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
create_clock -period "100.0 MHz" [get_pins -compatibility_mode spi|sclk_out] -name spi_sck
derive_pll_clocks
create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|*[0].*|divclk}] \
-name HDMI_CLK [get_ports HDMI_TX_CLK]
derive_clock_uncertainty
# Decouple different clock groups (to simplify routing)
@ -22,9 +17,6 @@ set_clock_groups -exclusive \
-group [get_clocks { FPGA_CLK2_50 }] \
-group [get_clocks { FPGA_CLK3_50 }]
set_output_delay -max -clock HDMI_CLK 4.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_output_delay -min -clock HDMI_CLK 3.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
set_false_path -from [get_ports {KEY*}]
set_false_path -from [get_ports {BTN_*}]
set_false_path -to [get_ports {LED_*}]
@ -34,4 +26,23 @@ set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
set_false_path -to {cfg[*]}
set_false_path -from {cfg[*]}
set_false_path -from {VSET[*]}
set_false_path -to {wcalc[*] hcalc[*]}
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 2
set_false_path -to {*_osd|v_cnt*}
set_false_path -to {*_osd|v_osd_start*}
set_false_path -to {*_osd|h_osd_start*}
set_false_path -from {*_osd|v_osd_start*}
set_false_path -from {*_osd|h_osd_start*}
set_false_path -from {*_osd|rot*}
set_false_path -from {*_osd|dsp_width*}
set_false_path -to {*_osd|half}
set_false_path -to {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
set_false_path -from {WIDTH[*] HFP[*] HS[*] HBP[*] HEIGHT[*] VFP[*] VS[*] VBP[*]}
set_false_path -to {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] FB_HMIN[*] FB_HMAX[*] FB_VMIN[*] FB_VMAX[*]}
set_false_path -from {FB_BASE[*] FB_BASE[*] FB_WIDTH[*] FB_HEIGHT[*] FB_HMIN[*] FB_HMAX[*] FB_VMIN[*] FB_VMAX[*]}
set_false_path -to {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}
set_false_path -from {vol_att[*] scaler_flt[*] led_overtake[*] led_state[*]}

384
sys/sys_top.v
View File

@ -1,7 +1,7 @@
//============================================================================
//
// MiSTer hardware abstraction module
// (c)2017-2019 Alexey Melnikov
// (c)2017-2020 Alexey Melnikov
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
@ -19,6 +19,11 @@
//
//============================================================================
`ifndef ARCADE_SYS
`define USE_DDRAM
`define USE_SDRAM
`endif
module sys_top
(
/////////// CLOCK //////////
@ -125,25 +130,33 @@ module sys_top
);
////////////////////// Secondary SD ///////////////////////////////////
wire SD_CS, SD_CLK, SD_MOSI;
wire sd_miso;
wire SD_CS, SD_CLK, SD_MOSI, SD_MISO;
`ifdef ARCADE_SYS
assign SD_CS = 1'bZ;
assign SD_CLK = 1'bZ;
assign SD_MOSI = 1'bZ;
`else
`ifndef DUAL_SDRAM
wire sd_miso = SW[3] | SDIO_DAT[0];
`else
wire sd_miso = 1;
`endif
wire SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO;
`endif
`ifndef DUAL_SDRAM
assign SDIO_DAT[2:1]= 2'bZZ;
assign SDIO_DAT[3] = SW[3] ? 1'bZ : SD_CS;
assign SDIO_CLK = SW[3] ? 1'bZ : SD_CLK;
assign SDIO_CMD = SW[3] ? 1'bZ : SD_MOSI;
assign sd_miso = SW[3] ? 1'b1 : SDIO_DAT[0];
assign SD_SPI_CS = mcp_sdcd ? ((~VGA_EN & sog & ~cs1) ? 1'b1 : 1'bZ) : SD_CS;
`else
assign sd_miso = 1'b1;
assign SD_SPI_CS = mcp_sdcd ? 1'bZ : SD_CS;
`endif
assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK;
assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI;
assign SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO;
assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK;
assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI;
////////////////////// LEDs/Buttons ///////////////////////////////////
@ -266,6 +279,7 @@ reg [15:0] cfg;
reg cfg_got = 0;
reg cfg_set = 0;
wire vga_fb = cfg[12];
wire [1:0] hdmi_limited = {cfg[11],cfg[8]};
wire direct_video = cfg[10];
wire dvi_mode = cfg[7];
@ -395,7 +409,9 @@ end
cyclonev_hps_interface_peripheral_uart uart
(
.ri(0),
.ri(0)
`ifndef ARCADE_SYS
,
.dsr(uart_dsr),
.dcd(uart_dsr),
.dtr(uart_dtr),
@ -404,14 +420,15 @@ cyclonev_hps_interface_peripheral_uart uart
.rts(uart_rts),
.rxd(uart_rxd),
.txd(uart_txd)
`endif
);
wire aspi_sck,aspi_mosi,aspi_ss;
wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso;
cyclonev_hps_interface_peripheral_spi_master spi
(
.sclk_out(aspi_sck),
.txd(aspi_mosi), // mosi
.rxd(1), // miso
.rxd(aspi_miso), // miso
.ss_0_n(aspi_ss),
.ss_in_n(1)
@ -444,7 +461,7 @@ always @(posedge FPGA_CLK2_50) begin
end
wire clk_100m;
wire clk_hdmi = ~hdmi_clk_out; // Internal HDMI clock, inverted in relation to external clock
wire clk_hdmi = hdmi_clk_out;
wire clk_audio = FPGA_CLK3_50;
wire clk_pal = FPGA_CLK3_50;
@ -461,6 +478,7 @@ sysmem_lite sysmem
//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
.reset_hps_cold_req(btn_r),
`ifdef USE_DDRAM
//64-bit DDR3 RAM access
.ram1_clk(ram_clk),
.ram1_address(ram_address),
@ -472,18 +490,19 @@ sysmem_lite sysmem
.ram1_writedata(ram_writedata),
.ram1_byteenable(ram_byteenable),
.ram1_write(ram_write),
`endif
//64-bit DDR3 RAM access
.ram2_clk(clk_audio),
.ram2_address((ap_en1 == ap_en2) ? aram_address : pram_address),
.ram2_burstcount((ap_en1 == ap_en2) ? aram_burstcount : pram_burstcount),
.ram2_waitrequest(aram_waitrequest),
.ram2_readdata(aram_readdata),
.ram2_readdatavalid(aram_readdatavalid),
.ram2_read((ap_en1 == ap_en2) ? aram_read : pram_read),
.ram2_writedata(0),
.ram2_byteenable(8'hFF),
.ram2_write(0),
.ram2_address(ram2_address),
.ram2_burstcount(ram2_burstcount),
.ram2_waitrequest(ram2_waitrequest),
.ram2_readdata(ram2_readdata),
.ram2_readdatavalid(ram2_readdatavalid),
.ram2_read(ram2_read),
.ram2_writedata(ram2_writedata),
.ram2_byteenable(ram2_byteenable),
.ram2_write(ram2_write),
//128-bit DDR3 RAM access
// HDMI frame buffer
@ -499,6 +518,46 @@ sysmem_lite sysmem
.vbuf_read(vbuf_read)
);
wire [28:0] ram2_address;
wire [7:0] ram2_burstcount;
wire [7:0] ram2_byteenable;
wire ram2_waitrequest;
wire [63:0] ram2_readdata;
wire [63:0] ram2_writedata;
wire ram2_readdatavalid;
wire ram2_read;
wire ram2_write;
wire [7:0] ram2_bcnt;
ddr_svc ddr_svc
(
.clk(clk_audio),
.ram_waitrequest(ram2_waitrequest),
.ram_burstcnt(ram2_burstcount),
.ram_addr(ram2_address),
.ram_readdata(ram2_readdata),
.ram_read_ready(ram2_readdatavalid),
.ram_read(ram2_read),
.ram_writedata(ram2_writedata),
.ram_byteenable(ram2_byteenable),
.ram_write(ram2_write),
.ram_bcnt(ram2_bcnt),
.ch0_addr(alsa_address),
.ch0_burst(1),
.ch0_data(alsa_readdata),
.ch0_req(alsa_req),
.ch0_ready(alsa_ready),
.ch1_addr(pal_addr),
.ch1_burst(128),
.ch1_data(pal_data),
.ch1_req(pal_req),
.ch1_ready(pal_wr)
);
wire [27:0] vbuf_address;
wire [7:0] vbuf_burstcount;
wire vbuf_waitrequest;
@ -524,15 +583,15 @@ ascal
.run (1),
.freeze (0),
.i_clk (clk_vid),
.i_ce (ce_pix),
.i_r (r_out),
.i_g (g_out),
.i_b (b_out),
.i_hs (hs_fix),
.i_vs (vs_fix),
.i_clk (clk_ihdmi),
.i_ce (ce_hpix),
.i_r (hr_out),
.i_g (hg_out),
.i_b (hb_out),
.i_hs (hhs_fix),
.i_vs (hvs_fix),
.i_fl (f1),
.i_de (de_emu),
.i_de (hde_emu),
.iauto (1),
.himin (0),
.himax (0),
@ -668,37 +727,21 @@ pll_hdmi_adj pll_hdmi_adj
.o_writedata(cfg_data)
);
wire [23:0] pal_d;
wire [7:0] pal_a;
wire [63:0] pal_data;
wire [47:0] pal_d = {pal_data[55:32], pal_data[23:0]};
wire [6:0] pal_a = ram2_bcnt[6:0];
wire pal_wr;
wire ap_en1, ap_en2;
reg [28:0] pal_addr;
reg pal_req = 0;
always @(posedge clk_pal) begin
reg old_vs;
wire [28:0] pram_address;
wire [7:0] pram_burstcount;
wire pram_read;
pal_addr <= FB_BASE[31:3] - 29'd512;
fbpal fbpal
(
.reset(reset),
.en_in(ap_en2),
.en_out(ap_en1),
.ram_clk(clk_pal),
.ram_address(pram_address),
.ram_burstcount(pram_burstcount),
.ram_waitrequest(aram_waitrequest),
.ram_readdata(aram_readdata),
.ram_readdatavalid(aram_readdatavalid),
.ram_read(pram_read),
.fb_address(FB_BASE),
.pal_en(~FB_FMT[2] & FB_FMT[1] & FB_FMT[0] & FB_EN),
.pal_a(pal_a),
.pal_d(pal_d),
.pal_wr(pal_wr)
);
old_vs <= hdmi_vs;
if(~old_vs & hdmi_vs & ~FB_FMT[2] & FB_FMT[1] & FB_FMT[0] & FB_EN) pal_req <= ~pal_req;
end
///////////////////////// HDMI output /////////////////////////////////
@ -830,14 +873,19 @@ osd hdmi_osd
.dout(hdmi_data_osd),
.hs_out(hdmi_hs_osd),
.vs_out(hdmi_vs_osd),
.de_out(hdmi_de_osd),
.de_out(hdmi_de_osd)
`ifndef ARCADE_SYS
,
.osd_status(osd_status)
`endif
);
wire hdmi_cs_osd;
csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd);
reg [23:0] dv_data;
reg dv_hs, dv_vs, dv_de;
always @(negedge clk_vid) begin
always @(posedge clk_vid) begin
reg [23:0] dv_d1, dv_d2;
reg dv_de1, dv_de2, dv_hs1, dv_hs2, dv_vs1, dv_vs2;
reg [12:0] vsz, vcnt;
@ -876,11 +924,63 @@ always @(negedge clk_vid) begin
dv_vs <= dv_vs2;
end
assign HDMI_TX_CLK = direct_video ? clk_vid : hdmi_clk_out;
assign HDMI_TX_HS = direct_video ? dv_hs : hdmi_hs_osd;
assign HDMI_TX_VS = direct_video ? dv_vs : hdmi_vs_osd;
assign HDMI_TX_DE = direct_video ? dv_de : hdmi_de_osd;
assign HDMI_TX_D = direct_video ? dv_data : hdmi_data_osd;
wire hdmi_tx_clk;
cyclonev_clkselect hdmi_clk_sw
(
.clkselect({1'b1, ~vga_fb & direct_video}),
.inclk({clk_vid, hdmi_clk_out, 2'b00}),
.outclk(hdmi_tx_clk)
);
altddio_out
#(
.extend_oe_disable("OFF"),
.intended_device_family("Cyclone V"),
.invert_output("OFF"),
.lpm_hint("UNUSED"),
.lpm_type("altddio_out"),
.oe_reg("UNREGISTERED"),
.power_up_high("OFF"),
.width(1)
)
hdmiclk_ddr
(
.datain_h(1'b0),
.datain_l(1'b1),
.outclock(hdmi_tx_clk),
.dataout(HDMI_TX_CLK),
.aclr(1'b0),
.aset(1'b0),
.oe(1'b1),
.outclocken(1'b1),
.sclr(1'b0),
.sset(1'b0)
);
reg hdmi_out_hs;
reg hdmi_out_vs;
reg hdmi_out_de;
reg [23:0] hdmi_out_d;
always @(posedge hdmi_tx_clk) begin
reg hs,vs,de;
reg [23:0] d;
hs <= (~vga_fb & direct_video) ? dv_hs : (direct_video & csync_en) ? hdmi_cs_osd : hdmi_hs_osd;
vs <= (~vga_fb & direct_video) ? dv_vs : hdmi_vs_osd;
de <= (~vga_fb & direct_video) ? dv_de : hdmi_de_osd;
d <= (~vga_fb & direct_video) ? dv_data : hdmi_data_osd;
hdmi_out_hs <= hs;
hdmi_out_vs <= vs;
hdmi_out_de <= de;
hdmi_out_d <= d;
end
assign HDMI_TX_HS = hdmi_out_hs;
assign HDMI_TX_VS = hdmi_out_vs;
assign HDMI_TX_DE = hdmi_out_de;
assign HDMI_TX_D = hdmi_out_d;
///////////////////////// VGA output //////////////////////////////////
@ -933,15 +1033,12 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
.ypbpr_full(0),
.ypbpr_en(ypbpr_en),
.dout(vga_o),
.din(vga_scaler ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd)
.din((vga_fb | vga_scaler) ? {24{hdmi_de_osd}} & hdmi_data_osd : vga_data_osd)
);
wire hdmi_cs_osd;
csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd);
wire vs1 = vga_scaler ? hdmi_vs_osd : vga_vs_osd;
wire hs1 = vga_scaler ? hdmi_hs_osd : vga_hs_osd;
wire cs1 = vga_scaler ? hdmi_cs_osd : vga_cs_osd;
wire vs1 = (vga_fb | vga_scaler) ? hdmi_vs_osd : vga_vs_osd;
wire hs1 = (vga_fb | vga_scaler) ? hdmi_hs_osd : vga_hs_osd;
wire cs1 = (vga_fb | vga_scaler) ? hdmi_cs_osd : vga_cs_osd;
assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? 1'b1 : ~vs1;
assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : csync_en ? ~cs1 : ~hs1;
@ -1014,32 +1111,28 @@ audio_out audio_out
.spdif(spdif)
);
wire [28:0] aram_address;
wire [7:0] aram_burstcount;
wire aram_waitrequest;
wire [63:0] aram_readdata;
wire aram_readdatavalid;
wire aram_read;
wire [28:0] alsa_address;
wire [63:0] alsa_readdata;
wire alsa_ready;
wire alsa_req;
wire alsa_late;
wire [15:0] alsa_l, alsa_r;
alsa alsa
(
.reset(reset),
.en_in(ap_en1),
.en_out(ap_en2),
.clk(clk_audio),
.ram_clk(clk_audio),
.ram_address(aram_address),
.ram_burstcount(aram_burstcount),
.ram_waitrequest(aram_waitrequest),
.ram_readdata(aram_readdata),
.ram_readdatavalid(aram_readdatavalid),
.ram_read(aram_read),
.ram_address(alsa_address),
.ram_data(alsa_readdata),
.ram_req(alsa_req),
.ram_ready(alsa_ready),
.spi_ss(aspi_ss),
.spi_sck(aspi_sck),
.spi_mosi(aspi_mosi),
.spi_miso(aspi_miso),
.pcm_l(alsa_l),
.pcm_r(alsa_r)
@ -1067,52 +1160,76 @@ assign user_in[6] = USER_IO[6];
/////////////////// User module connection ////////////////////////////
wire clk_sys;
wire [15:0] audio_ls, audio_rs;
wire audio_s;
wire [1:0] audio_mix;
wire [7:0] r_out, g_out, b_out;
wire vs_fix, hs_fix, de_emu, f1;
wire [1:0] scanlines;
wire clk_sys, clk_vid, ce_pix;
wire [7:0] r_out, g_out, b_out, hr_out, hg_out, hb_out;
wire vs_fix, hs_fix, de_emu, vs_emu, hs_emu, f1;
wire hvs_fix, hhs_fix, hde_emu;
wire clk_vid, ce_pix, clk_ihdmi, ce_hpix;
wire ram_clk;
wire [28:0] ram_address;
wire [7:0] ram_burstcount;
wire ram_waitrequest;
wire [63:0] ram_readdata;
wire ram_readdatavalid;
wire ram_read;
wire [63:0] ram_writedata;
wire [7:0] ram_byteenable;
wire ram_write;
`ifdef USE_DDRAM
wire ram_clk;
wire [28:0] ram_address;
wire [7:0] ram_burstcount;
wire ram_waitrequest;
wire [63:0] ram_readdata;
wire ram_readdatavalid;
wire ram_read;
wire [63:0] ram_writedata;
wire [7:0] ram_byteenable;
wire ram_write;
`endif
wire led_user;
wire [1:0] led_power;
wire [1:0] led_disk;
wire [1:0] btn;
wire vs_emu, hs_emu;
sync_fix sync_v(clk_vid, vs_emu, vs_fix);
sync_fix sync_h(clk_vid, hs_emu, hs_fix);
wire uart_dtr;
wire uart_dsr;
wire uart_cts;
wire uart_rts;
wire uart_rxd;
wire uart_txd;
wire osd_status;
wire [6:0] user_out, user_in;
`ifndef USE_SDRAM
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = {39'bZ};
`endif
`ifdef ARCADE_SYS
wire hvs_emu, hhs_emu;
sync_fix hdmi_sync_v(clk_ihdmi, hvs_emu, hvs_fix);
sync_fix hdmi_sync_h(clk_ihdmi, hhs_emu, hhs_fix);
assign audio_mix = 0;
assign {ADC_SCK, ADC_SDI, ADC_CONVST} = 0;
assign btn = 0;
`else
assign clk_ihdmi= clk_vid;
assign ce_hpix = ce_pix;
assign hr_out = r_out;
assign hg_out = g_out;
assign hb_out = b_out;
assign hhs_fix = hs_fix;
assign hvs_fix = vs_fix;
assign hde_emu = de_emu;
wire uart_dtr;
wire uart_dsr;
wire uart_cts;
wire uart_rts;
wire uart_rxd;
wire uart_txd;
wire osd_status;
`endif
emu emu
(
.CLK_50M(FPGA_CLK2_50),
.RESET(reset),
.HPS_BUS({f1, HDMI_TX_VS, clk_100m, clk_vid, ce_pix, de_emu, hs_fix, vs_fix, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
.CLK_VIDEO(clk_vid),
.CE_PIXEL(ce_pix),
.HPS_BUS({f1, HDMI_TX_VS, clk_100m, clk_ihdmi, ce_hpix, hde_emu, hhs_fix, hvs_fix, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
.VGA_R(r_out),
.VGA_G(g_out),
@ -1121,23 +1238,41 @@ emu emu
.VGA_VS(vs_emu),
.VGA_DE(de_emu),
.VGA_F1(f1),
`ifdef ARCADE_SYS
.VGA_CLK(clk_vid),
.VGA_CE(ce_pix),
.HDMI_CLK(clk_ihdmi),
.HDMI_CE(ce_hpix),
.HDMI_R(hr_out),
.HDMI_G(hg_out),
.HDMI_B(hb_out),
.HDMI_HS(hhs_emu),
.HDMI_VS(hvs_emu),
.HDMI_DE(hde_emu),
.HDMI_SL(scanlines),
.HDMI_ARX(ARX),
.HDMI_ARY(ARY),
`else
.CLK_VIDEO(clk_vid),
.CE_PIXEL(ce_pix),
.VGA_SL(scanlines),
.VIDEO_ARX(ARX),
.VIDEO_ARY(ARY),
.AUDIO_MIX(audio_mix),
.ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}),
`endif
.LED_USER(led_user),
.LED_POWER(led_power),
.LED_DISK(led_disk),
.BUTTONS(btn),
.VIDEO_ARX(ARX),
.VIDEO_ARY(ARY),
.AUDIO_L(audio_ls),
.AUDIO_R(audio_rs),
.AUDIO_S(audio_s),
.AUDIO_MIX(audio_mix),
.ADC_BUS({ADC_SCK,ADC_SDO,ADC_SDI,ADC_CONVST}),
`ifdef USE_DDRAM
.DDRAM_CLK(ram_clk),
.DDRAM_ADDR(ram_address),
.DDRAM_BURSTCNT(ram_burstcount),
@ -1148,7 +1283,9 @@ emu emu
.DDRAM_DIN(ram_writedata),
.DDRAM_BE(ram_byteenable),
.DDRAM_WE(ram_write),
`endif
`ifdef USE_SDRAM
.SDRAM_DQ(SDRAM_DQ),
.SDRAM_A(SDRAM_A),
.SDRAM_DQML(SDRAM_DQML),
@ -1160,6 +1297,7 @@ emu emu
.SDRAM_nCAS(SDRAM_nCAS),
.SDRAM_CLK(SDRAM_CLK),
.SDRAM_CKE(SDRAM_CKE),
`endif
`ifdef DUAL_SDRAM
.SDRAM2_DQ(SDRAM2_DQ),
@ -1173,6 +1311,9 @@ emu emu
.SDRAM2_EN(SW[3]),
`endif
`ifndef ARCADE_SYS
.BUTTONS(btn),
.OSD_STATUS(osd_status),
.SD_SCK(SD_CLK),
.SD_MOSI(SD_MOSI),
.SD_MISO(SD_MISO),
@ -1189,11 +1330,10 @@ emu emu
.UART_TXD(uart_rxd),
.UART_DTR(uart_dsr),
.UART_DSR(uart_dtr),
`endif
.USER_OUT(user_out),
.USER_IN(user_in),
.OSD_STATUS(osd_status)
.USER_IN(user_in)
);
endmodule

108
sys/video_mixer.sv
View File

@ -17,17 +17,21 @@
// HALF_DEPTH: If =1 then color dept is 4 bits per component
// For half depth 8 bits monochrome is available with
// mono signal enabled and color = {G, R}
//
// altera message_off 10720
// altera message_off 12161
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0
parameter HALF_DEPTH = 0,
parameter GAMMA = 0
)
(
// master clock
// video clock
// it should be multiple by (ce_pix*4).
input clk_sys,
input clk_vid,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
output ce_pix_out,
@ -48,6 +52,8 @@ module video_mixer
// Monochrome mode (for HALF_DEPTH only)
input mono,
inout [21:0] gamma_bus,
// Positive pulses.
input HSync,
input VSync,
@ -64,22 +70,74 @@ module video_mixer
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
localparam DWIDTH_SD = GAMMA ? 7 : DWIDTH;
localparam HALF_DEPTH_SD = GAMMA ? 0 : HALF_DEPTH;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
generate
if(GAMMA && HALF_DEPTH) begin
wire [7:0] R_in = mono ? {G,R} : {R,R};
wire [7:0] G_in = mono ? {G,R} : {G,G};
wire [7:0] B_in = mono ? {G,R} : {B,B};
end else begin
wire [DWIDTH:0] R_in = R;
wire [DWIDTH:0] G_in = G;
wire [DWIDTH:0] B_in = B;
end
endgenerate
wire hs_g, vs_g;
wire hb_g, vb_g;
wire [DWIDTH_SD:0] R_gamma, G_gamma, B_gamma;
generate
if(GAMMA) begin
assign gamma_bus[21] = 1;
gamma_corr gamma(
.clk_sys(gamma_bus[20]),
.clk_vid(clk_vid),
.ce_pix(ce_pix),
.gamma_en(gamma_bus[19]),
.gamma_wr(gamma_bus[18]),
.gamma_wr_addr(gamma_bus[17:8]),
.gamma_value(gamma_bus[7:0]),
.HSync(HSync),
.VSync(VSync),
.HBlank(HBlank),
.VBlank(VBlank),
.RGB_in({R_in,G_in,B_in}),
.HSync_out(hs_g),
.VSync_out(vs_g),
.HBlank_out(hb_g),
.VBlank_out(vb_g),
.RGB_out({R_gamma,G_gamma,B_gamma})
);
end else begin
assign gamma_bus[21] = 0;
assign {R_gamma,G_gamma,B_gamma} = {R_in,G_in,B_in};
assign {hs_g, vs_g, hb_g, vb_g} = {HSync, VSync, HBlank, VBlank};
end
endgenerate
wire [DWIDTH_SD:0] R_sd;
wire [DWIDTH_SD:0] G_sd;
wire [DWIDTH_SD:0] B_sd;
wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH_SD)) sd
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.hb_in(HBlank),
.vb_in(VBlank),
.r_in(R),
.g_in(G),
.b_in(B),
.hs_in(hs_g),
.vs_in(vs_g),
.hb_in(hb_g),
.vb_in(vb_g),
.r_in(R_gamma),
.g_in(G_gamma),
.b_in(B_gamma),
.ce_pix_out(ce_pix_sd),
.hs_out(hs_sd),
@ -91,12 +149,12 @@ scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoubler ? R_sd : R);
wire [DWIDTH:0] gt = (scandoubler ? G_sd : G);
wire [DWIDTH:0] bt = (scandoubler ? B_sd : B);
wire [DWIDTH_SD:0] rt = (scandoubler ? R_sd : R_gamma);
wire [DWIDTH_SD:0] gt = (scandoubler ? G_sd : G_gamma);
wire [DWIDTH_SD:0] bt = (scandoubler ? B_sd : B_gamma);
generate
if(HALF_DEPTH) begin
if(!GAMMA && HALF_DEPTH) begin
wire [7:0] r = mono ? {gt,rt} : {rt,rt};
wire [7:0] g = mono ? {gt,rt} : {gt,gt};
wire [7:0] b = mono ? {gt,rt} : {bt,bt};
@ -107,14 +165,14 @@ generate
end
endgenerate
wire hs = (scandoubler ? hs_sd : HSync);
wire vs = (scandoubler ? vs_sd : VSync);
wire hs = (scandoubler ? hs_sd : hs_g);
wire vs = (scandoubler ? vs_sd : vs_g);
assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
reg scanline = 0;
always @(posedge clk_sys) begin
always @(posedge clk_vid) begin
reg old_hs, old_vs;
old_hs <= hs;
@ -124,10 +182,10 @@ always @(posedge clk_sys) begin
if(old_vs && ~vs) scanline <= 0;
end
wire hde = scandoubler ? ~hb_sd : ~HBlank;
wire vde = scandoubler ? ~vb_sd : ~VBlank;
wire hde = scandoubler ? ~hb_sd : ~hb_g;
wire vde = scandoubler ? ~vb_sd : ~vb_g;
always @(posedge clk_sys) begin
always @(posedge clk_vid) begin
reg old_hde;
case(scanlines & {scanline, scanline})