146 lines
4.6 KiB
Verilog
146 lines
4.6 KiB
Verilog
/*
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($000000 - $03FFFF) RAM 4MB, or Overlay ROM 4MB
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($400000 - $4FFFFF) ROM 1MB
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64K Mac 128K/512K ROM is $400000 - $40FFFF
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128K Mac 512Ke/Plus ROM is $400000 - $41FFFF
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If ROM is mirrored when A17 is 1, then SCSI is assumed to be unavailable
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($580000 - $580FFF) SCSI (Mac Plus only, not implemented here)
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($600000 - $7FFFFF) Overlay RAM 2MB
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($9FFFF8 - $BFFFFF) SCC
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The SCC is on the upper byte of the data bus, so you must use only even-addressed byte reads.
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When writing, you must use only odd-addressed byte writes (the MC68000 puts your data on both bytes of the bus, so it works correctly).
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A byte read of an odd SCC read address tries to reset the entire SCC.
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A word access to any SCC address will shift the phase of the computer's high-frequency timing by 128 ns.
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($9FFFF8) SCC read channel B control
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($9FFFFA) SCC read channel A control
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($9FFFFC) SCC read channel B data in/out
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($9FFFFE) SCC read channel A data in/out
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($BFFFF9) SCC write channel B control
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($BFFFFB) SCC write channel A control
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($BFFFFD) SCC write channel B data in/out
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($BFFFFF) SCC write channel A data in/out
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($DFE1FF - $DFFFFF) IWM
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The IWM is on the lower byte of the data bus, so use odd-addressed byte accesses only.
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The 16 IWM registers are {8'hDF, 8'b111xxxx1, 8'hFF}:
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0 $0 ph0L CA0 off (0)
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1 $200 ph0H CA0 on (1)
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2 $400 ph1L CA1 off (0)
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3 $600 ph1H CA1 on (1)
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4 $800 h2L CA2 off (0)
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5 $A00 ph2H CA2 on (1)
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6 $C00 ph3L LSTRB off (low)
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7 $E00 ph3H LSTRB on (high)
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8 $1000 mtrOff disk enable off
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9 $1200 mtrOn disk enable on
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10 $1400 intDrive select internal drive
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11 $1600 extDrive select external drive
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12 $1800 q6L Q6 off
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13 $1A00 q6H Q6 on
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14 $1C00 q7L Q7 off, read register
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15 $1E00 q7H Q7 on, write register
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($EFE1FE - $EFFFFE) VIA
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The VIA is on the upper byte of the data bus, so use even-addressed byte accesses only.
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The 16 VIA registers are {8'hEF, 8'b111xxxx1, 8'hFE}:
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0 $0 vBufB register B
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1 $200 ????? not used?
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2 $400 vDirB register B direction register
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3 $600 vDirA register A direction register
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4 $800 vT1C timer 1 counter (low-order byte)
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5 $A00 vT1CH timer 1 counter (high-order byte)
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6 $C00 vT1L timer 1 latch (low-order byte)
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7 $E00 vT1LH timer 1 latch (high-order byte)
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8 $1000 vT2C timer 2 counter (low-order byte)
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9 $1200 vT2CH timer 2 counter (high-order byte)
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10 $1400 vSR shift register (keyboard)
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11 $1600 vACR auxiliary control register
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12 $1800 vPCR peripheral control register
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13 $1A00 vIFR interrupt flag register
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14 $1C00 vIER interrupt enable register
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15 $1E00 vBufA register A
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($F00000 - $F00005) memory phase read test
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($F80000 - $FFFFEF) space for test software
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($FFFFF0 - $FFFFFF) interrupt vectors
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Note: This can all be decoded using only the highest 4 address bits, if SCSI, phase read test, and test software are not used.
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7 other address bits are used by peripherals to determine which register to access:
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A12-A9 - IWM and VIA
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A2-A0 - SCC
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*/
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module addrDecoder(
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input [1:0] configROMSize,
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input [23:0] address,
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input _cpuAS,
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input memoryOverlayOn,
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output reg selectRAM,
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output reg selectROM,
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output reg selectSCSI,
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output reg selectSCC,
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output reg selectIWM,
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output reg selectVIA,
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output reg selectSEOverlay
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);
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always @(*) begin
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selectRAM = 0;
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selectROM = 0;
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selectSCSI = 0;
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selectSCC = 0;
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selectIWM = 0;
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selectVIA = 0;
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selectSEOverlay = 0;
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casez (address[23:20])
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4'b00??: begin //00 0000 - 3F FFFF
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if (memoryOverlayOn == 0)
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selectRAM = !_cpuAS;
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else begin
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if (address[23:20] == 0) begin
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// Mac Plus: repeated images of overlay ROM only extend to $0F0000
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// Mac 512K: more repeated ROM images at $020000-$02FFFF
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// Mac SE: overlay ROM at $00 0000 - $0F FFFF
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selectROM = !_cpuAS;
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end
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end
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end
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4'b0100: begin //40 0000 - 4F FFFF
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if(configROMSize[1] || address[17] == 1'b0) // <- this detects SCSI (on Plus)!!!
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selectROM = !_cpuAS;
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selectSEOverlay = !_cpuAS;
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end
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4'b0101: begin //50 000 - 5F FFFF
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if (address[19]) // 58 000 - 5F FFFF
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selectSCSI = !_cpuAS;
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selectSEOverlay = !_cpuAS;
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end
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4'b0110:
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if (memoryOverlayOn)
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selectRAM = !_cpuAS;
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4'b10?1:
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selectSCC = !_cpuAS;
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4'b1100: // C0 000 - CF FFF
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if (!configROMSize[1])
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selectIWM = !_cpuAS;
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4'b1101:
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selectIWM = !_cpuAS;
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4'b1110:
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if (address[19]) // E8 000 - EF FFF
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selectVIA = !_cpuAS;
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default:
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; // select nothing
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endcase
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end
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endmodule
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