342 lines
12 KiB
Verilog
342 lines
12 KiB
Verilog
/* Synchronous 8-bit replica of 3.5 inch floppy disk drive.
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Differences from the true floppy interace at the Mac's DB-19 port:
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True interface has a writeReq control line, only 1-bit readData and writeData, and no clk.
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True interface does not have newByteReady signal. Instead the IWM must watch the data in bit and synchronize with it to
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determine the timing and framing of bytes.
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*/
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/* Disk register (read):
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State-control lines Register
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CA2 CA1 CA0 SEL addressed Information in register
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0 0 0 0 DIRTN Head step direction (0=toward track 79, 1=toward track 0)
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0 0 0 1 CSTIN Disk in place (0=disk is inserted)
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0 0 1 0 STEP Drive head stepping (setting to 0 performs a step, returns to 1 when step is complete)
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0 0 1 1 WRTPRT Disk locked (0=locked)
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0 1 0 0 MOTORON Drive motor running (0=on, 1=off)
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0 1 0 1 TKO Head at track 0 (0=at track 0)
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0 1 1 0 SWITCHED Disk switched (1=yes?)
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0 1 1 1 TACH Tachometer (produces 60 pulses for each rotation of the drive motor)
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1 0 0 0 RDDATA0 Read data, lower head, side 0
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1 0 0 1 RDDATA1 Read data, upper head, side 1
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1 0 1 0 SUPERDR Drive is a Superdrive (0=no, 1=yes)
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1 1 0 0 SIDES Single- or double-sided drive (0=single side, 1=double side)
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1 1 0 1 READY 0 = yes
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1 1 1 0 INSTALLED 0 = yes
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1 1 1 1 DRVIN 400K/800K: Drive installed (0=drive is present), Superdrive: Inserted disk capacity (0=HD, 1=DD)
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Disk registers (write):
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Control lines Register
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CA1 CA0 SEL addressed Register function
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0 0 0 DIRTN Set stepping direction (0=toward track 79, 1=toward track 0)
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0 0 1 SWITCHED Reset disk switched flag (writing 1 sets switch flag to 0)
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0 1 0 STEP Step the drive head one track (setting to 0 performs a step, returns to 1 when step is complete)
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1 0 0 MOTORON Turn on/off drive motor (0=on, 1=off)
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1 1 0 EJECT Eject the disk (writing 1 ejects the disk)
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*/
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`define DRIVE_REG_DIRTN 0 /* R/W: step direction (0=toward track 79, 1=toward track 0) */
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`define DRIVE_REG_CSTIN 1 /* R: disk in place (1 = no disk) */
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/* W: ?? reset disk switch flag ? */
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`define DRIVE_REG_STEP 2 /* R: drive head is stepping (1 = complete) */
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/* W: 0 = step drive head */
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`define DRIVE_REG_WRTPRT 3 /* R: 0 = disk is write-protected */
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`define DRIVE_REG_MOTORON 4 /* R/W: 0 = motor on */
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`define DRIVE_REG_TK0 5 /* R: 0 = head at track 0 */
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`define DRIVE_REG_EJECT 6 /* R: disk switched (1=yes?)*/
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/* W: 1 = eject the disk */
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`define DRIVE_REG_TACH 7 /* R: tach-o-meter */
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`define DRIVE_REG_RDDATA0 8 /* R: activate lower head: side 0 */
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`define DRIVE_REG_RDDATA1 9 /* R: activate upper head: side 1 */
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`define DRIVE_REG_SUPERDR 10 /* R: drive is a superdrive (0=no, 1=yes) */
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`define DRIVE_REG_SIDES 12 /* R: number of sides (0=single, 1=dbl) */
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`define DRIVE_REG_READY 13 /* R: drive ready (head loaded) (0=ready) */
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`define DRIVE_REG_INSTALLED 14 /* R: drive present (0 = yes ??) */
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`define DRIVE_REG_DRVIN 15 /* R: 400K/800k: drive present (0=yes, 1=no), Superdrive: disk capacity (0=HD, 1=DD) */
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module floppy
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(
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input clk,
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input cep,
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input cen,
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input _reset,
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input ca0, // PH0
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input ca1, // PH1
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input ca2, // PH2
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input SEL, // HDSEL from VIA
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input lstrb, // aka PH3
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input _enable,
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input [7:0] writeData,
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output [7:0] readData,
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input advanceDriveHead, // prevents overrun when debugging, does not exist on a real Mac!
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output reg newByteReady,
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input insertDisk,
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input diskSides,
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output diskEject,
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output motor,
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output act,
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output [21:0] dskReadAddr,
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input dskReadAck,
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input [7:0] dskReadData
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);
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assign motor = ~driveRegs[`DRIVE_REG_MOTORON];
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assign act = lstrbEdge;
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reg [15:0] driveRegs;
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reg [6:0] driveTrack;
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reg driveSide;
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reg [7:0] diskDataIn; // incoming byte from the floppy disk
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// read drive registers
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wire [15:0] driveRegsAsRead = {
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1'b0, // DRVIN = yes
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1'b0, // INSTALLED = yes
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1'b0, // READY = yes
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1'b1, // SIDES = double-sided drive
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1'b0, // UNUSED
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1'b0, // SUPERDR
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1'b0, // RDDATA1
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1'b0, // RDDATA0
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driveRegs[`DRIVE_REG_TACH], // TACH: 60 pules for each rotation of the drive motor
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1'b0, // disk switched?
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~(driveTrack == 7'h00), // TK0: track 0 indicator
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driveRegs[`DRIVE_REG_MOTORON], // motor on
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1'b0, // WRTPRT = locked
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1'b1, // STEP = complete
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driveRegs[`DRIVE_REG_CSTIN], // disk in drive
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driveRegs[`DRIVE_REG_DIRTN] // step direction
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};
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reg dskReadAckD;
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always @(posedge clk) if(cen) dskReadAckD <= dskReadAck;
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// latch incoming data
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reg [7:0] dskReadDataLatch;
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always @(posedge clk) if(cep && dskReadAckD) dskReadDataLatch <= dskReadData;
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wire [7:0] dskReadDataEnc;
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reg old_newByteReady;
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always @(posedge clk) old_newByteReady <= newByteReady;
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// include track encoder
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floppy_track_encoder enc
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(
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.clk ( clk ),
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.ready ( ~old_newByteReady & newByteReady ),
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.rst ( !_reset ),
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.side ( driveSide ),
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.sides ( doubleSidedDisk ),
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.track ( driveTrack ),
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.addr ( dskReadAddr ),
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.idata ( dskReadDataLatch ),
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.odata ( dskReadDataEnc )
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);
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// TODO: auto-detect doubleSidedDisk from image file size
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wire doubleSidedDisk = diskSides;
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wire [3:0] driveReadAddr = {ca2,ca1,ca0,SEL};
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// a byte is read or written every 128 clocks (2 us per bit * 8 bits = 16 us, @ 8 MHz = 128 clocks)
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// The CPU must poll for data at least this often, or else an overrun will occur.
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reg [6:0] diskDataByteTimer;
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reg [7:0] diskImageData;
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reg readyToAdvanceHead;
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always @(posedge clk or negedge _reset) begin
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if (_reset == 0) begin
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driveSide <= 0;
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diskImageData <= 8'h00;
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diskDataIn <= 8'hFF;
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diskDataByteTimer <= 0;
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readyToAdvanceHead <= 1;
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newByteReady <= 1'b0;
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end
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else begin
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if(cep) begin
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// at time 0, latch a new byte and advance the drive head
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if (diskDataByteTimer == 0 && readyToAdvanceHead && diskImageData != 0) begin
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diskDataIn <= diskImageData;
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newByteReady <= 1;
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diskDataByteTimer <= 1; // make timer run again
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// clear diskImageData after it's used, so we can tell when we get a new one from the disk
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diskImageData <= 0;
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// for debugging, don't advance the head until the IWM says it's ready
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readyToAdvanceHead <= 1'b1; // TEMP: treat IWM as always ready
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end
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// extraRomReadAck comes every hsync which is every 21us. The iwm data rates
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// is 8MHZ/128 = 16us
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else begin
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// a timer governs when the next disk byte will become available
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diskDataByteTimer <= diskDataByteTimer + 1'b1;
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newByteReady <= 1'b0;
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if (dskReadAck) begin
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// whenever ACK is received, store the data from the current diskImageAddr
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diskImageData <= dskReadDataEnc; // xyz
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end
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if (advanceDriveHead) begin
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readyToAdvanceHead <= 1'b1;
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end
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end
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// switch drive sides if DRIVE_REG_RDDATA0 or DRIVE_REG_RDDATA1 are read
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// TODO: we don't know if this is a true read, since we don't know if IWM is selected or
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// could be bad if we use this test to flush a cache of encoded disk data
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if (driveReadAddr == `DRIVE_REG_RDDATA0 && lstrb == 1'b0)
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driveSide <= 0;
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if (driveReadAddr == `DRIVE_REG_RDDATA1 && lstrb == 1'b0)
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driveSide <= 1;
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end
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end
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end
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// create a signal on the falling edge of lstrb
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reg lstrbPrev;
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always @(posedge clk) if(cep) lstrbPrev <= lstrb;
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wire lstrbEdge = lstrb == 1'b0 && lstrbPrev == 1'b1;
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assign readData = _enable ? 8'hFF :
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(driveReadAddr == `DRIVE_REG_RDDATA0 || driveReadAddr == `DRIVE_REG_RDDATA1) ? diskDataIn :
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{ driveRegsAsRead[driveReadAddr], 7'h00 };
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// write drive registers
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wire [2:0] driveWriteAddr = {ca1,ca0,SEL};
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// DRIVE_REG_DIRTN 0 /* R/W: step direction (0=toward track 79, 1=toward track 0) */
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0) begin
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driveRegs[`DRIVE_REG_DIRTN] <= 1'b0;
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end
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else if(cep && _enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_DIRTN) begin
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driveRegs[`DRIVE_REG_DIRTN] <= ca2;
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end
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end
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// DRIVE_REG_CSTIN 1 /* R: disk in place (1 = no disk) */
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/* W: ?? reset disk switch flag ? */
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// disk in drive indicators
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reg [23:0] ejectIndicatorTimer;
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assign diskEject = (ejectIndicatorTimer != 0);
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0) begin
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driveRegs[`DRIVE_REG_CSTIN] <= 1'b1;
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ejectIndicatorTimer <= 24'd0;
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end
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else if(cep) begin
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if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_EJECT && ca2 == 1'b1) begin
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// eject the disk
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driveRegs[`DRIVE_REG_CSTIN] <= 1'b1;
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ejectIndicatorTimer <= 24'hFFFFFF;
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end
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else if (insertDisk) begin
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// insert a disk
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driveRegs[`DRIVE_REG_CSTIN] <= 1'b0;
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end
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else begin
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if (ejectIndicatorTimer != 0)
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ejectIndicatorTimer <= ejectIndicatorTimer - 1'b1;
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end
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end
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end
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//`define DRIVE_REG_STEP 2 /* R: drive head stepping (1 = complete) */
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/* W: 0 = step drive head */
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0) begin
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driveTrack <= 0;
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end
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else if(cep && _enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_STEP && ca2 == 1'b0) begin
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if (driveRegs[`DRIVE_REG_DIRTN] == 1'b0 && driveTrack != 7'h4F) begin
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driveTrack <= driveTrack + 1'b1;
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end
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if (driveRegs[`DRIVE_REG_DIRTN] == 1'b1 && driveTrack != 0) begin
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driveTrack <= driveTrack - 1'b1;
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end
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end
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end
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// DRIVE_REG_MOTORON 4 /* R/W: 0 = motor on */
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0) begin
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driveRegs[`DRIVE_REG_MOTORON] <= 1'b1;
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end
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else if (cep && _enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_MOTORON) begin
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driveRegs[`DRIVE_REG_MOTORON] <= ca2;
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end
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end
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// DRIVE_REG_TACH 7 Tachometer (produces 60 pulses for each rotation of the drive motor)
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/* Data from MESS, sonydriv.c:
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Tracks RPM Timing Value
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00-15: 500 timing value $117B (acceptable range {1135-11E9})
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16-31: 550 timing value $???? (acceptable range {12C6-138A})
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32-47: 600 timing value $???? (acceptable range {14A7-157F})
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48-63: 675 timing value $???? (acceptable range {16F2-17E2})
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64-79: 750 timing value $???? (acceptable range {19D0-1ADE})
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Experimentally determined toggle rates for Plus Too with 8.125 MHz CPU clock:
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TACH Half Period Clocks Resulting Timing Value
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9996 $117B (4475)
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9122 $1328 (4904)
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8292 $1513 (5395)
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7463 $176A (5994)
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6634 $1A56 (6742)
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*/
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reg [13:0] driveTachTimer;
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reg [13:0] driveTachPeriod;
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always @(*) begin
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case (driveTrack[6:4])
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0: // tracks 0-15
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driveTachPeriod <= 9996;
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1: // tracks 16-31
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driveTachPeriod <= 9122;
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2: // tracks 32-47
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driveTachPeriod <= 8292;
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3: // tracks 48-63
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driveTachPeriod <= 7463;
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default: // tracks 64-79
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driveTachPeriod <= 6634;
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endcase
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end
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0) begin
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driveRegs[`DRIVE_REG_TACH] <= 1'b0;
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driveTachTimer <= 0;
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end
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else if(cep) begin
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if (driveTachTimer == driveTachPeriod) begin
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driveTachTimer <= 0;
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driveRegs[`DRIVE_REG_TACH] <= ~driveRegs[`DRIVE_REG_TACH];
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end
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else begin
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driveTachTimer <= driveTachTimer + 1'b1;
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end
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end
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end
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endmodule
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