370 lines
11 KiB
Verilog
370 lines
11 KiB
Verilog
/*
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floppy_track_encoder.v
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encode a full floppy track from raw sector data on the fly
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*/
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/* verilator lint_off UNUSED */
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/* verilator lint_off UNDRIVEN */
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/* verilator lint_off CASEINCOMPLETE */
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module floppy_track_encoder (
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// system signals
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input clk, // clock at which data bytes are delivered via odata
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input ready,
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input rst,
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input side,
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input sides,
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input [6:0] track, // current track
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output reg [21:0] addr, // address to fetch from
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input [7:0] idata,
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output [7:0] odata
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);
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always @(posedge clk) begin
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addr <=
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{ 3'b00, soff, 9'd0 } + // sector offset * 512 for two sides
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(sides?{ 3'b00, soff, 9'd0 }:22'd0) + // another sector offset * 512 for two sides
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(side?{ 9'd0, spt, 9'd0 }:22'd0) + // side * sectors * 512
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{ 9'd0, sector, src_offset }; // offset within track
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end
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// number of sectors on current track
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wire [3:0] spt =
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(track[6:4] == 3'd0)?4'd12: // track 0 - 15
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(track[6:4] == 3'd1)?4'd11: // track 16 - 31
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(track[6:4] == 3'd2)?4'd10: // track 32 - 47
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(track[6:4] == 3'd3)?4'd9: // track 48 - 63
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4'd8; // track 64 - ...
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// all possible tack*sector factors
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wire [9:0] track_times_12 = // x*12 = x*8 + x*4
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{ track, 3'b000 } + // x<<3 +
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{ 1'b0, track, 2'b00 }; // x<<2
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wire [9:0] track_times_11 = // x*11 = x*8 + x*2 + x*1
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{ track, 3'b000 } + // x<<3 +
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{ 2'b00, track, 1'b0 } + // x<<1 +
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{ 3'b000, track }; // x<<0
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wire [9:0] track_times_10 = // x*10 = x*8 + x*2
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{ track, 3'b000 } + // x<<3 +
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{ 2'b00, track, 1'b0 }; // x<<1
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wire [9:0] track_times_9 = // x*9 = x*8 + x*1
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{ track, 3'b000 } + // x<<3 +
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{ 3'b000, track }; // x<<0
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wire [9:0] track_times_8 = // x*8
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{ track, 3'b000 }; // x<<3
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// sector offset of current track is the sum of all sectors on all tracks before
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wire [6:0] trackm1 = track - 7'd1;
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wire [9:0] soff =
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(track == 0)?10'd0: // track 0
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(trackm1[6:4] == 3'd0)?track_times_12: // track 1 - 16
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(trackm1[6:4] == 3'd1)?(track_times_11 + 10'd16): // track 17 - 32
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(trackm1[6:4] == 3'd2)?(track_times_10 + 10'd32 + 10'd16): // track 33 - 48
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(trackm1[6:4] == 3'd3)?(track_times_9 + 10'd48 + 10'd32 + 10'd16): // track 49 - 64
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(track_times_8 + 10'd64 + 10'd48 + 10'd32 + 10'd16); // track 65 -
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// parts of an address block
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wire [5:0] sec_in_tr = {2'b00, sector};
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wire [5:0] track_low = track[5:0];
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wire [5:0] track_hi = { side, 4'b0000, track[6] };
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wire [5:0] format = { sides, 5'h2 }; // double sided = 22, single sided = 2
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wire [5:0] checksum = track_low ^ sec_in_tr ^ track_hi ^ format;
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// data input to the sony encoder during address block
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wire [5:0] sony_addr_in =
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(count == 3)?track_low:
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(count == 4)?sec_in_tr:
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(count == 5)?track_hi:
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(count == 6)?format:
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checksum;
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// data input to the sony encoder during data header
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wire [5:0] sony_dhdr_in = sec_in_tr;
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wire [5:0] sony_dsum_in =
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(count == 0)?{ c3[7:6], c2[7:6], c1[7:6] }:
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(count == 1)?c3[5:0]:
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(count == 2)?c2[5:0]:
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c1[5:0];
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// feed data into sony encoder
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wire [5:0] si =
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(state == STATE_ADDR)?sony_addr_in:
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(state == STATE_DHDR)?sony_dhdr_in:
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(state == STATE_DZRO)?nib_out:
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(state == STATE_DPRE)?nib_out:
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(state == STATE_DATA)?nib_out:
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(state == STATE_DSUM)?sony_dsum_in:
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6'h3f;
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// encoder table taken from MESS emulator
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wire [7:0] sony_to_disk_byte =
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(si==6'h00)?8'h96:(si==6'h01)?8'h97:(si==6'h02)?8'h9a:(si==6'h03)?8'h9b: // 0x00
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(si==6'h04)?8'h9d:(si==6'h05)?8'h9e:(si==6'h06)?8'h9f:(si==6'h07)?8'ha6:
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(si==6'h08)?8'ha7:(si==6'h09)?8'hab:(si==6'h0a)?8'hac:(si==6'h0b)?8'had:
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(si==6'h0c)?8'hae:(si==6'h0d)?8'haf:(si==6'h0e)?8'hb2:(si==6'h0f)?8'hb3:
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(si==6'h10)?8'hb4:(si==6'h11)?8'hb5:(si==6'h12)?8'hb6:(si==6'h13)?8'hb7: // 0x10
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(si==6'h14)?8'hb9:(si==6'h15)?8'hba:(si==6'h16)?8'hbb:(si==6'h17)?8'hbc:
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(si==6'h18)?8'hbd:(si==6'h19)?8'hbe:(si==6'h1a)?8'hbf:(si==6'h1b)?8'hcb:
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(si==6'h1c)?8'hcd:(si==6'h1d)?8'hce:(si==6'h1e)?8'hcf:(si==6'h1f)?8'hd3:
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(si==6'h20)?8'hd6:(si==6'h21)?8'hd7:(si==6'h22)?8'hd9:(si==6'h23)?8'hda: // 0x20
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(si==6'h24)?8'hdb:(si==6'h25)?8'hdc:(si==6'h26)?8'hdd:(si==6'h27)?8'hde:
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(si==6'h28)?8'hdf:(si==6'h29)?8'he5:(si==6'h2a)?8'he6:(si==6'h2b)?8'he7:
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(si==6'h2c)?8'he9:(si==6'h2d)?8'hea:(si==6'h2e)?8'heb:(si==6'h2f)?8'hec:
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(si==6'h30)?8'hed:(si==6'h31)?8'hee:(si==6'h32)?8'hef:(si==6'h33)?8'hf2: // 0x30
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(si==6'h34)?8'hf3:(si==6'h35)?8'hf4:(si==6'h36)?8'hf5:(si==6'h37)?8'hf6:
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(si==6'h38)?8'hf7:(si==6'h39)?8'hf9:(si==6'h3a)?8'hfa:(si==6'h3b)?8'hfb:
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(si==6'h3c)?8'hfc:(si==6'h3d)?8'hfd:(si==6'h3e)?8'hfe: 8'hff;
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// states of encoder state machine
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localparam STATE_SYN0 = 4'd0; // 56 bytes sync pattern (0xff)
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localparam STATE_ADDR = 4'd1; // 10 bytes address block
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localparam STATE_SYN1 = 4'd2; // 5 bytes sync pattern (0xff)
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localparam STATE_DHDR = 4'd3; // 4 bytes data block header
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localparam STATE_DZRO = 4'd4; // 8 encoded zero bytes in data block
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localparam STATE_DPRE = 4'd5; // 4 bytes data prefetch
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localparam STATE_DATA = 4'd6; // the payload itself
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localparam STATE_DSUM = 4'd7; // 4 bytes data checksum
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localparam STATE_DTRL = 4'd8; // 3 bytes data block trailer
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localparam STATE_WAIT = 4'd15; // wait until start of next sector
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// output data during address block
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wire [7:0] odata_addr =
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(count == 0)?8'hd5:
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(count == 1)?8'haa:
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(count == 2)?8'h96:
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(count == 8)?8'hde:
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(count == 9)?8'haa:
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sony_to_disk_byte;
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wire [7:0] odata_dhdr =
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(count == 0)?8'hd5:
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(count == 1)?8'haa:
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(count == 2)?8'had:
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sony_to_disk_byte;
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wire [7:0] odata_dtrl =
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(count == 0)?8'hde:
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(count == 1)?8'haa:
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8'hff;
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// demultiplex output data
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assign odata = (state == STATE_ADDR)?odata_addr:
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(state == STATE_DHDR)?odata_dhdr:
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(state == STATE_DZRO)?sony_to_disk_byte:
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(state == STATE_DPRE)?sony_to_disk_byte:
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(state == STATE_DATA)?sony_to_disk_byte:
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(state == STATE_DSUM)?sony_to_disk_byte:
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(state == STATE_DTRL)?odata_dtrl:
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8'hff;
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// ------------------------ nibbler ----------------------------
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reg [7:0] c1;
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reg [7:0] c2;
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reg c2x;
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reg [7:0] c3;
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reg c3x;
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wire nibbler_reset = (state == STATE_DHDR);
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reg [1:0] cnt;
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reg [7:0] nib_xor_0;
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reg [7:0] nib_xor_1;
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reg [7:0] nib_xor_2;
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// request an input byte. this happens 4 byte ahead of output.
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// only three bytes are read while four bytes are written due
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// to 6:2 encoding
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wire strobe = ((state == STATE_DPRE) ||
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((state == STATE_DATA) && (count < 683-4-1)))
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&& (cnt != 3);
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reg [7:0] data_latch;
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always @(posedge clk) if(ready && strobe) data_latch <= idata;
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always @(posedge clk or posedge nibbler_reset) begin
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if(nibbler_reset) begin
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c1 <= 8'h00;
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c2 <= 8'h00;
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c2x <= 1'b0;
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c3 <= 8'h00;
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c3x <= 1'b0;
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cnt <= 2'd0;
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nib_xor_0 <= 8'h00;
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nib_xor_1 <= 8'h00;
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nib_xor_2 <= 8'h00;
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end else if(ready && ((state == STATE_DPRE) || (state == STATE_DATA))) begin
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cnt <= cnt + 2'd1;
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// memory read during cnt 0-3
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if(count < 683-4) begin
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// encode first byte
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if(cnt == 1) begin
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c1 <= { c1[6:0], c1[7] };
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{ c3x, c3 } <= { 1'b0, c3 } + { 1'b0, nib_in } + { 8'd0, c1[7] };
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nib_xor_0 <= nib_in ^ { c1[6:0], c1[7] };
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end
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// encode second byte
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if(cnt == 2) begin
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{ c2x, c2 } <= { 1'b0, c2 } + { 1'b0, nib_in } + { 8'd0, c3x };
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c3x <= 1'b0;
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nib_xor_1 <= nib_in ^ c3;
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end
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// encode third byte
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if(cnt == 3) begin
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c1 <= c1 + nib_in + { 7'd0, c2x };
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c2x <= 1'b0;
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nib_xor_2 <= nib_in ^ c2;
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end
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end else begin
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// since there are 512/3 = 170 2/3 three byte blocks in a sector the
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// last run has to be filled up with zeros
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if(cnt == 3)
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nib_xor_2 <= 8'h00;
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end
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end
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end
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// bytes going into the nibbler
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wire [7:0] nib_in =
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(state == STATE_DZRO)?8'h00:
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data_latch;
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// four six bit units come out of the nibbler
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wire [5:0] nib_out =
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(cnt == 1)?nib_xor_0[5:0]:
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(cnt == 2)?nib_xor_1[5:0]:
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(cnt == 3)?nib_xor_2[5:0]:
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{ nib_xor_0[7:6], nib_xor_1[7:6], nib_xor_2[7:6] };
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// count bytes per sector
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reg [3:0] state;
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reg [9:0] count;
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reg [3:0] sector;
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reg [8:0] src_offset;
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always @(posedge clk or posedge rst) begin
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if(rst) begin
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count <= 10'd0;
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state <= STATE_SYN0;
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sector <= 4'd0;
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src_offset <= 9'd0;
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end else if(ready) begin
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count <= count + 10'd1;
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if(strobe)
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src_offset <= src_offset + 9'd1;
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case(state)
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// send 14*4=56 sync bytes
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STATE_SYN0: begin
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if(count == 55) begin
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state <= STATE_ADDR;
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count <= 10'd0;
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end
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end
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// send 10 bytes address block
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STATE_ADDR: begin
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if(count == 9) begin
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state <= STATE_SYN1;
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count <= 10'd0;
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end
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end
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// send 5 sync bytes
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STATE_SYN1: begin
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if(count == 4) begin
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state <= STATE_DHDR;
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count <= 10'd0;
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end
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end
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// send 4 bytes data block hdr
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STATE_DHDR: begin
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if(count == 3) begin
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state <= STATE_DZRO;
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count <= 10'd0;
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end
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end
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// send 8 zero bytes before data block
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STATE_DZRO: begin
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if(count == 11) begin
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state <= STATE_DPRE;
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count <= 10'd0;
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end
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end
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// start prefetching 4 bytes data
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STATE_DPRE: begin
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if(count == 3) begin
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state <= STATE_DATA;
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count <= 10'd0;
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end
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end
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// send 512 bytes data block 6:2 encoded in 683 bytes
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STATE_DATA: begin
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if(count == 682) begin
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state <= STATE_DSUM;
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count <= 10'd0;
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end
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end
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// send 4 bytes data checksum
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STATE_DSUM: begin
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if(count == 3) begin
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state <= STATE_DTRL;
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count <= 10'd0;
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end
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end
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// send 3 bytes data block trailer
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STATE_DTRL: begin
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if(count == 2) begin
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state <= STATE_WAIT;
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count <= 10'd0;
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end
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end
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// fill sector up to 1024 bytes
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STATE_WAIT: begin
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// if(count == 1023-56-10-5-4-12-4-683-4-3)
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begin
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count <= 10'd0;
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state <= STATE_SYN0;
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src_offset <= 9'd0;
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// interleave of 1
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// if(sector != spt-4'd1) sector <= sector + 4'd1;
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// else sector <= 4'd0;
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// interleave of 2
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if((sector == spt-4'd2) ||
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(sector == spt-4'd1)) sector <= { 3'd0, !sector[0] };
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else sector <= sector + 4'd2;
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end
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end
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endcase
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end
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end
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endmodule
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