304 lines
8.8 KiB
Verilog
304 lines
8.8 KiB
Verilog
/* IWM
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Mapped to $DFE1FF - $DFFFFF
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The 16 IWM one-bit registers are {8'hDF, 8'b111xxxx1, 8'hFF}:
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0 $0 ca0L CA0 off (0)
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1 $200 ca0H CA0 on (1)
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2 $400 ca1L CA1 off (0)
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3 $600 ca1H CA1 on (1)
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4 $800 ca2L CA2 off (0)
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5 $A00 ca2H CA2 on (1)
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6 $C00 ph3L LSTRB off (low)
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7 $E00 ph3H LSTRB on (high)
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8 $1000 mtrOff ENABLE disk enable off
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9 $1200 mtrOn ENABLE disk enable on
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10 $1400 intDrive SELECT select internal drive
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11 $1600 extDrive SELECT select external drive
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12 $1800 q6L Q6 off
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13 $1A00 q6H Q6 on
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14 $1C00 q7L Q7 off, read register
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15 $1E00 q7H Q7 on, write register
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Notes from IWM manual:
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Serial data is shifted in/out MSB first, with a bit transferred every 2 microseconds.
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When writing data, a 1 is written as a transition on writeData at a bit cell boundary time, and a 0 is written as no transition.
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When reading data, a falling transition within a bit cell window is considered to be a 1, and no falling transition is considered a 0.
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When reading data, the read data register will latch the shift register when a 1 is shifted into the MSB.
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The read data register will be cleared 14 fclk periods (about 2 microseconds) after a valid data read takes place-- a valid data read
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being defined as both /DEV being low and D7 (the MSB) outputting a one from the read data register for at least one fclk period.
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*/
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module iwm
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(
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input clk,
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input cep,
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input cen,
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input _reset,
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input selectIWM,
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input _cpuRW,
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input _cpuLDS,
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input [15:0] dataIn,
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input [3:0] cpuAddrRegHi,
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input SEL, // from VIA
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input driveSel, // internal drive select, 0 - upper, 1 - lower
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output [15:0] dataOut,
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input [1:0] insertDisk,
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output [1:0] diskEject,
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input [1:0] diskSides,
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output [1:0] diskMotor,
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output [1:0] diskAct,
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// interface to fetch data for internal drive
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output [21:0] dskReadAddrInt,
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input dskReadAckInt,
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output [21:0] dskReadAddrExt,
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input dskReadAckExt,
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input [7:0] dskReadData
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);
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wire [7:0] dataInLo = dataIn[7:0];
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reg [7:0] dataOutLo;
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assign dataOut = { 8'hBE, dataOutLo };
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// IWM state
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reg ca0, ca1, ca2, lstrb, selectExternalDrive, q6, q7;
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reg ca0Next, ca1Next, ca2Next, lstrbNext, selectExternalDriveNext, q6Next, q7Next;
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wire advanceDriveHead; // prevents overrun when debugging, does not exit on a real Mac!
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reg [7:0] writeData;
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reg [7:0] readDataLatch;
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wire _iwmBusy, _writeUnderrun;
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assign _iwmBusy = 1'b1; // for writes, a value of 1 here indicates the IWM write buffer is empty
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assign _writeUnderrun = 1'b1;
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// floppy disk drives
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reg diskEnableExt, diskEnableInt;
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reg diskEnableExtNext, diskEnableIntNext;
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wire newByteReadyInt;
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wire [7:0] readDataInt;
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wire senseInt = readDataInt[7]; // bit 7 doubles as the sense line here
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wire newByteReadyExt;
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wire [7:0] readDataExt;
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wire senseExt = readDataExt[7]; // bit 7 doubles as the sense line here
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floppy floppyInt
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(
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.clk(clk),
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.cep(cep),
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.cen(cen),
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._reset(_reset),
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.ca0(ca0),
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.ca1(ca1),
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.ca2(ca2),
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.SEL(SEL),
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.lstrb(lstrb),
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._enable(~(diskEnableInt & driveSel)),
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.writeData(writeData),
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.readData(readDataInt),
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.advanceDriveHead(advanceDriveHead),
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.newByteReady(newByteReadyInt),
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.insertDisk(insertDisk[0]),
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.diskSides(diskSides[0]),
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.diskEject(diskEject[0]),
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.motor(diskMotor[0]),
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.act(diskAct[0]),
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.dskReadAddr(dskReadAddrInt),
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.dskReadAck(dskReadAckInt),
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.dskReadData(dskReadData)
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);
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floppy floppyExt
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(
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.clk(clk),
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.cep(cep),
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.cen(cen),
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._reset(_reset),
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.ca0(ca0),
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.ca1(ca1),
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.ca2(ca2),
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.SEL(SEL),
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.lstrb(lstrb),
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._enable(~diskEnableExt),
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.writeData(writeData),
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.readData(readDataExt),
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.advanceDriveHead(advanceDriveHead),
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.newByteReady(newByteReadyExt),
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.insertDisk(insertDisk[1]),
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.diskSides(diskSides[1]),
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.diskEject(diskEject[1]),
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.motor(diskMotor[1]),
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.act(diskAct[1]),
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.dskReadAddr(dskReadAddrExt),
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.dskReadAck(dskReadAckExt),
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.dskReadData(dskReadData)
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);
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wire [7:0] readData = selectExternalDrive ? readDataExt : readDataInt;
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wire newByteReady = selectExternalDrive ? newByteReadyExt : newByteReadyInt;
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reg [4:0] iwmMode;
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/* IWM mode register: S C M H L
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S Clock speed:
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0 = 7 MHz
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1 = 8 MHz
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Should always be 1 for Macintosh.
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C Bit cell time:
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0 = 4 usec/bit (for 5.25 drives)
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1 = 2 usec/bit (for 3.5 drives) (Macintosh mode)
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M Motor-off timer:
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0 = leave drive on for 1 sec after program turns
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it off
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1 = no delay (Macintosh mode)
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Should be 0 for 5.25 and 1 for 3.5.
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H Handshake protocol:
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0 = synchronous (software must supply proper
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timing for writing data)
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1 = asynchronous (IWM supplies timing) (Macintosh Mode)
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Should be 0 for 5.25 and 1 for 3.5.
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L Latch mode:
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0 = read-data stays valid for about 7 usec
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1 = read-data stays valid for full byte time (Macintosh mode)
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Should be 0 for 5.25 and 1 for 3.5.
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*/
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// any read/write access to IWM bit registers will change their values
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always @(*) begin
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ca0Next <= ca0;
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ca1Next <= ca1;
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ca2Next <= ca2;
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lstrbNext <= lstrb;
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diskEnableExtNext <= diskEnableExt;
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diskEnableIntNext <= diskEnableInt;
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selectExternalDriveNext <= selectExternalDrive;
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q6Next <= q6;
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q7Next <= q7;
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if (selectIWM == 1'b1 && _cpuLDS == 1'b0) begin
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case (cpuAddrRegHi[3:1])
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3'h0: // ca0
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ca0Next <= cpuAddrRegHi[0];
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3'h1: // ca1
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ca1Next <= cpuAddrRegHi[0];
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3'h2: // ca2
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ca2Next <= cpuAddrRegHi[0];
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3'h3: // lstrb
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lstrbNext <= cpuAddrRegHi[0];
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3'h4: // disk enable
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if (selectExternalDrive)
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diskEnableExtNext <= cpuAddrRegHi[0];
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else
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diskEnableIntNext <= cpuAddrRegHi[0];
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3'h5: // external drive
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selectExternalDriveNext <= cpuAddrRegHi[0];
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3'h6: // Q6
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q6Next <= cpuAddrRegHi[0];
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3'h7: // Q7
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q7Next <= cpuAddrRegHi[0];
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endcase
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end
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end
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// update IWM bit registers
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0) begin
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ca0 <= 0;
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ca1 <= 0;
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ca2 <= 0;
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lstrb <= 0;
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diskEnableExt <= 0;
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diskEnableInt <= 0;
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selectExternalDrive <= 0;
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q6 <= 0;
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q7 <= 0;
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end
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else begin
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ca0 <= ca0Next;
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ca1 <= ca1Next;
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ca2 <= ca2Next;
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lstrb <= lstrbNext;
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diskEnableExt <= diskEnableExtNext;
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diskEnableInt <= diskEnableIntNext;
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selectExternalDrive <= selectExternalDriveNext;
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q6 <= q6Next;
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q7 <= q7Next;
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end
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end
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// read IWM state
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always @(*) begin
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dataOutLo = 8'hEF;
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// reading any IWM address returns state as selected by Q7 and Q6
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case ({q7Next,q6Next})
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2'b00: // data-in register (from disk drive) - MSB is 1 when data is valid
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dataOutLo <= readDataLatch;
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2'b01: // IWM status register - read only
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dataOutLo <= { (selectExternalDriveNext ? senseExt : senseInt), 1'b0, diskEnableExt & diskEnableInt, iwmMode };
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2'b10: // handshake - read only
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dataOutLo <= { _iwmBusy, _writeUnderrun, 6'b000000 };
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2'b11: // IWM mode register when not enabled (write-only), or (write?) data register when enabled
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dataOutLo <= 0;
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endcase
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end
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// write IWM state
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0) begin
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iwmMode <= 0;
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writeData <= 0;
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end
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else if(cen) begin
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if (_cpuRW == 0 && selectIWM == 1'b1 && _cpuLDS == 1'b0) begin
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// writing to any IWM address modifies state as selected by Q7 and Q6
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case ({q7Next,q6Next})
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2'b11: begin
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if (diskEnableExt | diskEnableInt)
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writeData <= dataInLo;
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else
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iwmMode <= dataInLo[4:0];
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end
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endcase
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end
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end
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end
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// Manage incoming bytes from the disk drive
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wire iwmRead = (_cpuRW == 1'b1 && selectIWM == 1'b1 && _cpuLDS == 1'b0);
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reg [3:0] readLatchClearTimer;
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always @(posedge clk or negedge _reset) begin
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if (_reset == 1'b0) begin
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readDataLatch <= 0;
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readLatchClearTimer <= 0;
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end
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else if(cen) begin
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// a countdown timer governs how long after a data latch read before the latch is cleared
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if (readLatchClearTimer != 0) begin
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readLatchClearTimer <= readLatchClearTimer - 1'b1;
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end
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// the conclusion of a valid CPU read from the IWM will start the timer to clear the latch
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if (iwmRead && readDataLatch[7]) begin
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readLatchClearTimer <= 4'hD; // clear latch 14 clocks after the conclusion of a valid read
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end
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// when the drive indicates that a new byte is ready, latch it
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// NOTE: the real IWM must self-synchronize with the incoming data to determine when to latch it
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if (newByteReady) begin
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readDataLatch <= readData;
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end
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else if (readLatchClearTimer == 1'b1) begin
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readDataLatch <= 0;
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end
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end
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end
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assign advanceDriveHead = readLatchClearTimer == 1'b1; // prevents overrun when debugging, does not exist on a real Mac!
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endmodule
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