303 lines
8.1 KiB
Systemverilog
303 lines
8.1 KiB
Systemverilog
/* verilator lint_off UNUSED */
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/* based on minimigmac by Benjamin Herrenschmidt */
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/* Read registers */
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`define RREG_CDR 3'h0 /* Current SCSI data */
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`define RREG_ICR 3'h1 /* Initiator Command */
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`define RREG_MR 3'h2 /* Mode register */
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`define RREG_TCR 3'h3 /* Target Command */
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`define RREG_CSR 3'h4 /* SCSI bus status */
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`define RREG_BSR 3'h5 /* Bus and status */
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`define RREG_IDR 3'h6 /* Input data */
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`define RREG_RST 3'h7 /* Reset */
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/* Write registers */
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`define WREG_ODR 3'h0 /* Output data */
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`define WREG_ICR 3'h1 /* Initiator Command */
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`define WREG_MR 3'h2 /* Mode register */
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`define WREG_TCR 3'h3 /* Target Command */
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`define WREG_SER 3'h4 /* Select Enable */
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`define WREG_DMAS 3'h5 /* Start DMA Send */
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`define WREG_DMATR 3'h6 /* Start DMA Target receive */
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`define WREG_IDMAR 3'h7 /* Start DMA Initiator receive */
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/* MR bit numbers */
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`define MR_DMA_MODE 1
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`define MR_ARB 0
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/* ICR bit numbers */
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`define ICR_A_RST 7
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`define ICR_TEST_MODE 6
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`define ICR_DIFF_ENBL 5
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`define ICR_A_ACK 4
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`define ICR_A_BSY 3
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`define ICR_A_SEL 2
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`define ICR_A_ATN 1
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`define ICR_A_DATA 0
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/* TCR bit numbers */
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`define TCR_A_REQ 3
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`define TCR_A_MSG 2
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`define TCR_A_CD 1
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`define TCR_A_IO 0
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module ncr5380
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(
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input clk,
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input reset,
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/* Bus interface. 3-bit address, to be wired
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* appropriately upstream (to A4..A6) plus one
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* more bit (A9) wired as dack.
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*/
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input bus_cs,
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input [2:0] bus_rs,
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input ior,
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input iow,
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input dack,
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output dreq,
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input [7:0] wdata,
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output [7:0] rdata,
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// connections to io controller
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input [DEVS-1:0] img_mounted,
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input [31:0] img_size,
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output reg [31:0] io_lba[DEVS],
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output [DEVS-1:0] io_rd,
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output [DEVS-1:0] io_wr,
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input [DEVS-1:0] io_ack,
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input [7:0] sd_buff_addr,
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input [15:0] sd_buff_dout,
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output [15:0] sd_buff_din[DEVS],
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input sd_buff_wr
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);
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parameter DEVS = 2;
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assign dreq = scsi_req & dma_en;
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reg [7:0] mr; /* Mode Register */
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reg [7:0] icr; /* Initiator Command Register */
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reg [3:0] tcr; /* Target Command Register */
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wire [7:0] csr; /* SCSI bus status register */
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/* Data in and out latches and associated
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* control logic for DMA
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*/
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reg [7:0] din;
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reg [7:0] dout;
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reg dma_en;
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/* --- Main host-side interface --- */
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/* Register & DMA accesses decodes */
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reg dma_wr;
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reg reg_wr;
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reg dma_ack;
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wire i_dma_rd = bus_cs & dack & ior;
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wire i_dma_wr = bus_cs & dack & iow;
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wire i_reg_wr = bus_cs & ~dack & iow;
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always @(posedge clk) begin
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reg old_dma_rd, old_dma_wr, old_reg_wr;
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old_dma_rd <= i_dma_rd;
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old_dma_wr <= i_dma_wr;
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old_reg_wr <= i_reg_wr;
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dma_wr <= 0;
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dma_ack <= 0;
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reg_wr <= 0;
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if(~old_dma_wr & i_dma_wr) dma_wr <= 1;
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if(~old_reg_wr & i_reg_wr) reg_wr <= 1;
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if((old_dma_wr & ~i_dma_wr) | (old_dma_rd & ~i_dma_rd)) dma_ack <= dma_en;
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end
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/* System bus reads */
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assign rdata = dack ? cur_data :
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bus_rs == `RREG_CDR ? cur_data :
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bus_rs == `RREG_ICR ? icr_read :
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bus_rs == `RREG_MR ? mr :
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bus_rs == `RREG_TCR ? { 4'h0, tcr } :
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bus_rs == `RREG_CSR ? csr :
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bus_rs == `RREG_BSR ? bsr :
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bus_rs == `RREG_IDR ? cur_data :
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bus_rs == `RREG_RST ? 8'hff :
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8'hff;
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/* Data out latch (in DMA mode, this is one cycle after we've
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* asserted ACK)
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*/
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always@(posedge clk) if((reg_wr && bus_rs == `WREG_ODR) || dma_wr) dout <= wdata;
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/* Current data register. Simplified logic: We loop back the
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* output data if we are asserting the bus, else we get the
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* input latch
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*/
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wire [7:0] cur_data = out_en ? dout : din;
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/* Logic for "asserting the bus" simplified */
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wire out_en = icr[`ICR_A_DATA] | mr[`MR_ARB];
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/* ICR read wires */
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wire [7:0] icr_read = { icr[`ICR_A_RST],
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icr_aip,
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icr_la,
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icr[`ICR_A_ACK],
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icr[`ICR_A_BSY],
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icr[`ICR_A_SEL],
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icr[`ICR_A_ATN],
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icr[`ICR_A_DATA] };
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/* ICR write */
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always@(posedge clk or posedge reset) begin
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if (reset) begin
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icr <= 0;
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end else if (reg_wr && (bus_rs == `WREG_ICR)) begin
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icr <= wdata;
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end
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end
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/* MR write */
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always@(posedge clk or posedge reset) begin
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if (reset) mr <= 8'b0;
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else if (reg_wr && (bus_rs == `WREG_MR)) mr <= wdata;
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end
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/* TCR write */
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always@(posedge clk or posedge reset) begin
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if (reset) tcr <= 4'b0;
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else if (reg_wr && (bus_rs == `WREG_TCR)) tcr <= wdata[3:0];
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end
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/* DMA start send & receive registers. We currently ignore
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* the direction.
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*/
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always@(posedge clk or posedge reset) begin
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if (reset) begin
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dma_en <= 0;
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end else begin
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if (!mr[`MR_DMA_MODE]) begin
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dma_en <= 0;
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end else if (reg_wr && (bus_rs == `WREG_DMAS)) begin
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dma_en <= 1;
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end else if (reg_wr && (bus_rs == `WREG_IDMAR)) begin
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dma_en <= 1;
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end
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end
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end
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/* CSR (read only). We don't do parity */
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assign csr = { scsi_rst, scsi_bsy, scsi_req, scsi_msg,
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scsi_cd, scsi_io, scsi_sel, 1'b0 };
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/* Bus and Status register */
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/* BSR (read only). We don't do a few things... */
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wire bsr_eodma = 1'b0; /* We don't do EOP */
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wire bsr_dmarq = scsi_req & dma_en;
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wire bsr_perr = 1'b0; /* We don't do parity */
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wire bsr_irq = 1'b0; /* XXX ? Does MacOS use this ? */
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wire bsr_pmatch =
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tcr[`TCR_A_MSG] == scsi_msg &&
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tcr[`TCR_A_CD ] == scsi_cd &&
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tcr[`TCR_A_IO ] == scsi_io;
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wire bsr_berr = 1'b0; /* XXX ? Does MacOS use this ? */
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wire [7:0] bsr = { bsr_eodma, bsr_dmarq, bsr_perr, bsr_irq,
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bsr_pmatch, bsr_berr, scsi_atn, scsi_ack };
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/* --- Simulated SCSI Signals --- */
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/* BSY logic (simplified arbitration, see notes) */
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wire scsi_bsy =
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icr[`ICR_A_BSY] |
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|target_bsy |
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//scsi2_bsy |
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//scsi6_bsy |
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mr[`MR_ARB];
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/* Remains of simplified arbitration logic */
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wire icr_aip = mr[`MR_ARB];
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wire icr_la = 0;
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/* Other ORed SCSI signals */
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wire scsi_sel = icr[`ICR_A_SEL];
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wire scsi_rst = icr[`ICR_A_RST];
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wire scsi_ack = icr[`ICR_A_ACK] | dma_ack;
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wire scsi_atn = icr[`ICR_A_ATN];
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/* Mux target signals */
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reg scsi_cd, scsi_io, scsi_msg, scsi_req;
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always begin
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integer i;
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scsi_cd = 0;
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scsi_io = 0;
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scsi_msg = 0;
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scsi_req = 0;
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din = 8'h55;
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for (i = 0; i < DEVS; i = i + 1) begin
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if (target_bsy[i]) begin
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scsi_cd = target_cd[i];
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scsi_io = target_io[i];
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scsi_msg = target_msg[i];
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scsi_req = target_req[i];
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din = target_dout[i];
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end
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end
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end
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// input signals from targets
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wire [DEVS-1:0] target_bsy;
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wire [DEVS-1:0] target_msg;
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wire [DEVS-1:0] target_io;
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wire [DEVS-1:0] target_cd;
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wire [DEVS-1:0] target_req;
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wire [7:0] target_dout[DEVS];
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generate
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genvar i;
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for (i = 0; i < DEVS; i = i + 1) begin : target
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// connect a target
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scsi #(.ID(3'd6 - i[2:0])) target
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(
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.clk ( clk ),
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.rst ( scsi_rst ),
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.sel ( scsi_sel ),
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.atn ( scsi_atn ),
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.ack ( scsi_ack ),
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.bsy ( target_bsy[i] ),
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.msg ( target_msg[i] ),
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.cd ( target_cd[i] ),
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.io ( target_io[i] ),
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.req ( target_req[i] ),
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.dout ( target_dout[i] ),
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.din ( dout ),
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// connection to io controller to read and write sectors
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// to sd card
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.img_mounted(img_mounted[i]),
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.img_blocks(img_size),
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.io_lba ( io_lba[i] ),
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.io_rd ( io_rd[i] ),
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.io_wr ( io_wr[i] ),
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.io_ack ( io_ack[i] & target_bsy[i] ),
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.sd_buff_addr( sd_buff_addr ),
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.sd_buff_dout( sd_buff_dout ),
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.sd_buff_din( sd_buff_din[i] ),
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.sd_buff_wr( sd_buff_wr & target_bsy[i] )
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);
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end
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endgenerate
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endmodule
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