95 lines
2.0 KiB
Verilog
95 lines
2.0 KiB
Verilog
`timescale 1ns / 100ps
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/*
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* PS2 mouse protocol
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* Bit 7 6 5 4 3 2 1 0
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* Byte 0: YOVR XOVR YSGN XSGN 1 MBUT RBUT LBUT
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* Byte 1: XMOVE
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* Byte 2: YMOVE
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*/
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/*
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* PS2 Mouse to Mac interface module
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*/
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module ps2_mouse
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(
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input clk,
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input ce,
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input reset,
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input [24:0] ps2_mouse,
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output reg x1,
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output reg y1,
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output reg x2,
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output reg y2,
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output reg button
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);
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reg [9:0] xacc;
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reg [9:0] yacc;
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reg [11:0] clkdiv;
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wire strobe = (old_stb != ps2_mouse[24]);
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reg old_stb = 0;
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always @(posedge clk) old_stb <= ps2_mouse[24];
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/* Capture button state */
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always@(posedge clk or posedge reset)
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if (reset) button <= 1;
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else if (strobe) button <= ~(|ps2_mouse[2:0]);
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/* Clock divider to flush accumulators */
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always@(posedge clk or posedge reset)
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if (reset) clkdiv <= 0;
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else if(ce) clkdiv <= clkdiv + 1'b1;
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wire tick = (ce && clkdiv == 0);
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/* Toggle output lines base on accumulator */
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always@(posedge clk or posedge reset) begin
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if (reset) begin
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x1 <= 0;
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x2 <= 0;
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end else if (tick && xacc != 0) begin
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x1 <= ~x1;
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x2 <= ~x1 ^ ~xacc[9];
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end
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end
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always@(posedge clk or posedge reset) begin
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if (reset) begin
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y1 <= 0;
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y2 <= 0;
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end else if (tick && yacc != 0) begin
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y1 <= ~y1;
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y2 <= ~y1 ^ ~yacc[9];
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end
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end
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/* Movement accumulators. Needs tuning ! */
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always@(posedge clk or posedge reset) begin
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if (reset) xacc <= 0;
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else begin
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/* Add movement, convert to a 10-bit number if not over */
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if (strobe && xacc[8] == xacc[9]) xacc <= xacc + { ps2_mouse[4], ps2_mouse[4], ps2_mouse[15:8] };
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else
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/* Decrement */
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if (tick && xacc != 0) xacc <= xacc + { {9{~xacc[9]}}, 1'b1 };
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end
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end
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always@(posedge clk or posedge reset) begin
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if (reset) yacc <= 0;
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else begin
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/* Add movement, convert to a 10-bit number if not over*/
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if (strobe && yacc[8] == yacc[9]) yacc <= yacc + { ps2_mouse[5], ps2_mouse[5], ps2_mouse[23:16] };
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else
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/* Decrement */
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if (tick && yacc != 0) yacc <= yacc + { {9{~yacc[9]}}, 1'b1 };
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end
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end
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endmodule
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