126 lines
2.7 KiB
Verilog
126 lines
2.7 KiB
Verilog
/* PRAM - RTC implementation for plus_too */
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module rtc (
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input clk,
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input reset,
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input [32:0] timestamp, // unix timestamp
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input _cs,
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input ck,
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input dat_i,
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output reg dat_o
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);
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reg [2:0] bit_cnt;
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reg ck_d;
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reg [7:0] din;
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reg [7:0] cmd;
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reg [7:0] dout;
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reg cmd_mode;
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reg receiving;
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reg [31:0] secs;
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reg [31:0] secs2;
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reg [7:0] ram[20];
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reg [24:0] clocktoseconds;
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initial begin
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ram[5'h00] = 8'hA8;
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ram[5'h01] = 8'h00;
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ram[5'h02] = 8'h00;
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ram[5'h03] = 8'h22;
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ram[5'h04] = 8'hCC;
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ram[5'h05] = 8'h0A;
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ram[5'h06] = 8'hCC;
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ram[5'h07] = 8'h0A;
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ram[5'h08] = 8'h00;
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ram[5'h09] = 8'h00;
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ram[5'h0A] = 8'h00;
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ram[5'h0B] = 8'h00;
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ram[5'h0C] = 8'h00;
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ram[5'h0D] = 8'h02;
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ram[5'h0E] = 8'h63;
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ram[5'h0F] = 8'h00;
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ram[5'h10] = 8'h03;
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ram[5'h11] = 8'h88;
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ram[5'h12] = 8'h00;
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ram[5'h13] = 8'h6C;
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end
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initial secs = 0;
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always @(posedge clk) begin
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if (reset) begin
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bit_cnt <= 0;
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receiving <= 1;
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cmd_mode <= 1;
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dat_o <= 1;
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// sec_cnt <= 0;
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end
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else begin
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// timestamp is only sent at core load
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if (secs==0)
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secs <= timestamp[31:0] + 2082844800; // difference between unix epoch and mac epoch
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// we need to add one to the seconds
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clocktoseconds<= clocktoseconds + 1'd1;
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if (32499999==clocktoseconds) // every 32mhz we increment secs by one
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begin
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clocktoseconds<=0;
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secs<=secs+1;
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end
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if (_cs) begin
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bit_cnt <= 0;
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receiving <= 1;
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cmd_mode <= 1;
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dat_o <= 1;
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end
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else begin
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ck_d <= ck;
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// transmit at the falling edge
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if (ck_d & ~ck & !receiving)
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dat_o <= dout[7-bit_cnt];
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// receive at the rising edge of ck
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if (~ck_d & ck) begin
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bit_cnt <= bit_cnt + 1'd1;
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if (receiving)
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din <= {din[6:0], dat_i};
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if (bit_cnt == 7) begin
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if (receiving && cmd_mode) begin
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// command byte received
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cmd_mode <= 0;
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receiving <= ~din[6];
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cmd <= {din[6:0], dat_i};
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casez ({din[5:0], dat_i})
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7'b00?0001: dout <= secs[7:0];
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7'b00?0101: dout <= secs[15:8];
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7'b00?1001: dout <= secs[23:16];
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7'b00?1101: dout <= secs[31:24];
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7'b010??01: dout <= ram[{3'b100, din[2:1]}];
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7'b1????01: dout <= ram[din[4:1]];
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default: ;
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endcase
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end
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if (receiving && !cmd_mode) begin
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// data byte received
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casez (cmd[6:0])
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7'b0000001: secs[7:0] <= {din[6:0], dat_i};
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7'b0000101: secs[15:8] <= {din[6:0], dat_i};
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7'b0001001: secs[23:16] <= {din[6:0], dat_i};
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7'b0001101: secs[31:24] <= {din[6:0], dat_i};
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7'b010??01: ram[{3'b100, cmd[3:2]}] <= {din[6:0], dat_i};
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7'b1????01: ram[cmd[5:2]] <= {din[6:0], dat_i};
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default: ;
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endcase
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end
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end
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end
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end
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end
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end
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endmodule
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