158 lines
3.7 KiB
Systemverilog
158 lines
3.7 KiB
Systemverilog
//============================================================================
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//
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// ALSA sound support for MiSTer
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// (c)2019,2020 Alexey Melnikov
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//============================================================================
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module alsa
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#(
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parameter CLK_RATE = 24576000
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)
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(
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input reset,
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input clk,
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output reg [31:3] ram_address,
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input [63:0] ram_data,
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output reg ram_req = 0,
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input ram_ready,
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input spi_ss,
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input spi_sck,
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input spi_mosi,
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output spi_miso,
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output reg [15:0] pcm_l,
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output reg [15:0] pcm_r
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);
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reg [60:0] buf_info;
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reg [6:0] spicnt = 0;
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always @(posedge spi_sck, posedge spi_ss) begin
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reg [95:0] spi_data;
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if(spi_ss) spicnt <= 0;
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else begin
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spi_data[{spicnt[6:3],~spicnt[2:0]}] <= spi_mosi;
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if(&spicnt) buf_info <= {spi_data[82:67],spi_data[50:35],spi_data[31:3]};
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spicnt <= spicnt + 1'd1;
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end
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end
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assign spi_miso = spi_out[{spicnt[4:3],~spicnt[2:0]}];
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reg [31:0] spi_out = 0;
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always @(posedge clk) if(spi_ss) spi_out <= {buf_rptr, hurryup, 8'h00};
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reg [31:3] buf_addr;
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reg [18:3] buf_len;
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reg [18:3] buf_wptr = 0;
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always @(posedge clk) begin
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reg [60:0] data1,data2;
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data1 <= buf_info;
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data2 <= data1;
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if(data2 == data1) {buf_wptr,buf_len,buf_addr} <= data2;
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end
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reg [2:0] hurryup = 0;
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reg [18:3] buf_rptr = 0;
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always @(posedge clk) begin
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reg [18:3] len = 0;
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reg [1:0] ready = 0;
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reg [63:0] readdata;
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reg got_first = 0;
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reg [7:0] ce_cnt = 0;
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reg [1:0] state = 0;
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if(reset) begin
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ready <= 0;
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ce_cnt <= 0;
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state <= 0;
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got_first <= 0;
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len <= 0;
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end
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else begin
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//ramp up
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if(len[18:14] && (hurryup < 1)) hurryup <= 1;
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if(len[18:16] && (hurryup < 2)) hurryup <= 2;
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if(len[18:17] && (hurryup < 4)) hurryup <= 4;
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//ramp down
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if(!len[18:15] && (hurryup > 2)) hurryup <= 2;
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if(!len[18:13] && (hurryup > 1)) hurryup <= 1;
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if(!len[18:10]) hurryup <= 0;
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if(ce_sample && ~&ce_cnt) ce_cnt <= ce_cnt + 1'd1;
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case(state)
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0: if(!ce_sample) begin
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if(ready) begin
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if(ce_cnt) begin
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{readdata[31:0],pcm_r,pcm_l} <= readdata;
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ready <= ready - 1'd1;
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ce_cnt <= ce_cnt - 1'd1;
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end
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end
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else if(buf_rptr != buf_wptr) begin
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if(~got_first) begin
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buf_rptr <= buf_wptr;
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got_first <= 1;
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end
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else begin
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ram_address <= buf_addr + buf_rptr;
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ram_req <= ~ram_req;
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buf_rptr <= buf_rptr + 1'd1;
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len <= (buf_wptr < buf_rptr) ? (buf_len + buf_wptr - buf_rptr) : (buf_wptr - buf_rptr);
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state <= 1;
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end
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end
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else begin
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len <= 0;
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ce_cnt <= 0;
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hurryup <= 0;
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end
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end
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1: if(ram_ready) begin
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ready <= 2;
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readdata <= ram_data;
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if(buf_rptr >= buf_len) buf_rptr <= buf_rptr - buf_len;
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state <= 0;
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end
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endcase
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end
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end
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reg ce_sample;
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always @(posedge clk) begin
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reg [31:0] acc = 0;
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ce_sample <= 0;
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acc <= acc + 48000 + {hurryup,6'd0};
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if(acc >= CLK_RATE) begin
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acc <= acc - CLK_RATE;
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ce_sample <= 1;
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end
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end
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endmodule
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