109 lines
2.6 KiB
Systemverilog
109 lines
2.6 KiB
Systemverilog
//
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// Copyright (c) 2020 Alexey Melnikov
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ------------------------------------------
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//
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// 16-bit version
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module ddr_svc
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(
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input clk,
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input ram_waitrequest,
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output [7:0] ram_burstcnt,
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output [28:0] ram_addr,
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input [63:0] ram_readdata,
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input ram_read_ready,
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output reg ram_read,
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output [63:0] ram_writedata,
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output [7:0] ram_byteenable,
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output reg ram_write,
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output [7:0] ram_bcnt,
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input [31:3] ch0_addr,
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input [7:0] ch0_burst,
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output [63:0] ch0_data,
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input ch0_req,
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output ch0_ready,
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input [31:3] ch1_addr,
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input [7:0] ch1_burst,
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output [63:0] ch1_data,
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input ch1_req,
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output ch1_ready
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);
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assign ram_burstcnt = ram_burst;
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assign ram_byteenable = 8'hFF;
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assign ram_addr = ram_address;
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assign ram_writedata = 0;
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assign ch0_data = ram_q[0];
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assign ch1_data = ram_q[1];
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assign ch0_ready = ready[0];
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assign ch1_ready = ready[1];
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reg [7:0] ram_burst;
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reg [63:0] ram_q[2];
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reg [31:3] ram_address;
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reg [1:0] ack = 0;
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reg [1:0] ready;
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reg state = 0;
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reg ch = 0;
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always @(posedge clk) begin
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ready <= 0;
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if(!ram_waitrequest) begin
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ram_read <= 0;
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ram_write <= 0;
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case(state)
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0: if(ch0_req != ack[0]) begin
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ack[0] <= ch0_req;
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ram_address <= ch0_addr;
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ram_burst <= ch0_burst;
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ram_read <= 1;
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ch <= 0;
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ram_bcnt <= 8'hFF;
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state <= 1;
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end
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else if(ch1_req != ack[1]) begin
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ack[1] <= ch1_req;
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ram_address <= ch1_addr;
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ram_burst <= ch1_burst;
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ram_read <= 1;
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ch <= 1;
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ram_bcnt <= 8'hFF;
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state <= 1;
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end
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1: begin
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if(ram_read_ready) begin
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ram_bcnt <= ram_bcnt + 1'd1;
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ram_q[ch] <= ram_readdata;
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ready[ch] <= 1;
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if ((ram_bcnt+2'd2) == ram_burst) state <= 0;
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end
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end
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endcase
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end
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end
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endmodule
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