251 lines
8.0 KiB
Systemverilog
251 lines
8.0 KiB
Systemverilog
// ============================================================================
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//
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// f2sdram_safe_terminator for MiSTer platform
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//
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// ============================================================================
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// Copyright (c) 2021 bellwood420
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//
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// Background:
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//
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// Terminating a transaction of burst writing(/reading) in its midstream
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// seems to cause an illegal state to f2sdram interface.
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//
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// Forced reset request that occurs when loading other core is inevitable.
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//
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// So if it happens exactly within the transaction period,
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// unexpected issues with accessing to f2sdram interface will be caused
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// in next loaded core.
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//
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// It seems that only way to reset broken f2sdram interface is to reset
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// whole SDRAM Controller Subsystem from HPS via permodrst register
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// in Reset Manager.
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// But it cannot be done safely while Linux is running.
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// It is usually done when cold or warm reset is issued in HPS.
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//
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// Main_MiSTer is issuing reset for FPGA <> HPS bridges
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// via brgmodrst register in Reset Manager when loading rbf.
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// But it has no effect on f2sdram interface.
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// f2sdram interface seems to belong to SDRAM Controller Subsystem
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// rather than FPGA-to-HPS bridge.
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//
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// Main_MiSTer is also trying to issuing reset for f2sdram ports
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// via fpgaportrst register in SDRAM Controller Subsystem when loading rbf.
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// But according to the Intel's document, fpgaportrst register can be
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// used to stretch the port reset.
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// It seems that it cannot be used to assert the port reset.
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//
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// According to the Intel's document, there seems to be a reset port on
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// Avalon-MM slave interface, but it cannot be found in Qsys generated HDL.
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//
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// To conclude, the only thing FPGA can do is not to break the transaction.
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// ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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//
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// Purpose:
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// To prevent the issue, this module completes ongoing transaction
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// on behalf of user logic, when reset is asserted.
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//
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// Usage:
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// Insert this module into the bus line between
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// f2sdram (Avalon-MM slave) and user logic (Avalon-MM master).
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//
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// Notice:
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// Asynchronous reset request is not supported.
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// Please feed reset request synchronized to clock.
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//
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module f2sdram_safe_terminator #(
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parameter DATA_WIDTH = 64,
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parameter BURSTCOUNT_WIDTH = 8
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) (
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// clk should be the same as one provided to f2sdram port
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// clk should not be stop when reset is asserted
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input clk,
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// rst_req_sync should be synchronized to clk
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// Asynchronous reset request is not supported
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input rst_req_sync,
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// Master port: connecting to Alavon-MM slave(f2sdram)
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input waitrequest_master,
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output [BURSTCOUNT_WIDTH-1:0] burstcount_master,
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output [ADDRESS_WITDH-1:0] address_master,
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input [DATA_WIDTH-1:0] readdata_master,
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input readdatavalid_master,
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output read_master,
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output [DATA_WIDTH-1:0] writedata_master,
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output [BYTEENABLE_WIDTH-1:0] byteenable_master,
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output write_master,
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// Slave port: connecting to Alavon-MM master(user logic)
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output waitrequest_slave,
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input [BURSTCOUNT_WIDTH-1:0] burstcount_slave,
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input [ADDRESS_WITDH-1:0] address_slave,
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output [DATA_WIDTH-1:0] readdata_slave,
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output readdatavalid_slave,
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input read_slave,
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input [DATA_WIDTH-1:0] writedata_slave,
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input [BYTEENABLE_WIDTH-1:0] byteenable_slave,
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input write_slave
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);
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localparam BYTEENABLE_WIDTH = DATA_WIDTH/8;
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localparam ADDRESS_WITDH = 32-$clog2(BYTEENABLE_WIDTH);
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/*
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* Capture init reset deaseert
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*/
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reg init_reset_deasserted = 1'b0;
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always_ff @(posedge clk) begin
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if (!rst_req_sync) begin
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init_reset_deasserted <= 1'b1;
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end
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end
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/*
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* Lock stage
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*/
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reg lock_stage = 1'b0;
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always_ff @(posedge clk) begin
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if (rst_req_sync) begin
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// Reset assert
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if (init_reset_deasserted) begin
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lock_stage <= 1'b1;
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end
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end
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else begin
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// Reset deassert
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lock_stage <= 1'b0;
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end
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end
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/*
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* Write burst transaction observer
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*/
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reg state_write = 1'b0;
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wire next_state_write;
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wire burst_write_start = !state_write && next_state_write;
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wire valid_write_data = state_write && !waitrequest_master;
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wire burst_write_end = state_write && (write_burstcounter == write_burstcount_latch - 1'd1);
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wire valid_non_burst_write = !state_write && write_slave && (burstcount_slave == 1) && !waitrequest_master;
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reg [BURSTCOUNT_WIDTH-1:0] write_burstcounter = 0;
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reg [BURSTCOUNT_WIDTH-1:0] write_burstcount_latch = 0;
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reg [ADDRESS_WITDH-1:0] write_address_latch = 0;
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always_ff @(posedge clk) begin
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state_write <= next_state_write;
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if (burst_write_start) begin
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write_burstcounter <= waitrequest_master ? 1'd0 : 1'd1;
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write_burstcount_latch <= burstcount_slave;
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write_address_latch <= address_slave;
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end
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else if (valid_write_data) begin
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write_burstcounter <= write_burstcounter + 1'd1;
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end
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end
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always_comb begin
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if (!state_write) begin
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if (valid_non_burst_write)
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next_state_write = 1'b0;
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else if (write_slave)
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next_state_write = 1'b1;
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else
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next_state_write = 1'b0;
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end
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else begin
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if (burst_write_end)
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next_state_write = 1'b0;
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else
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next_state_write = 1'b1;
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end
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end
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reg [BURSTCOUNT_WIDTH-1:0] write_terminate_counter = 0;
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reg [BURSTCOUNT_WIDTH-1:0] burstcount_latch = 0;
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reg [ADDRESS_WITDH-1:0] address_latch = 0;
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reg terminating = 0;
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reg read_terminating = 0;
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reg write_terminating = 0;
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wire on_write_transaction = state_write && next_state_write;
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wire on_start_write_transaction = !state_write && next_state_write;
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always_ff @(posedge clk) begin
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if (rst_req_sync) begin
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// Reset assert
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if (init_reset_deasserted) begin
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if (!lock_stage) begin
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// Even not knowing reading is in progress or not,
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// if it is in progress, it will finish at some point, and no need to do anything.
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// Assume that reading is in progress when we are not on write transaction.
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burstcount_latch <= burstcount_slave;
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address_latch <= address_slave;
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terminating <= 1;
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if (on_write_transaction) begin
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write_terminating <= 1;
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burstcount_latch <= write_burstcount_latch;
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address_latch <= write_address_latch;
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write_terminate_counter <= waitrequest_master ? write_burstcounter : write_burstcounter + 1'd1;
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end
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else if (on_start_write_transaction) begin
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if (!valid_non_burst_write) begin
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write_terminating <= 1;
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write_terminate_counter <= waitrequest_master ? 1'd0 : 1'd1;
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end
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end
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else if (read_slave && waitrequest_master) begin
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// Need to keep read signal, burstcount and address until waitrequest_master deasserted
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read_terminating <= 1;
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end
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end
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else if (!waitrequest_master) begin
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read_terminating <= 0;
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end
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end
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end
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else begin
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// Reset deassert
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if (!write_terminating) terminating <= 0;
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read_terminating <= 0;
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end
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if (write_terminating) begin
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// Continue write transaction until the end
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if (!waitrequest_master) write_terminate_counter <= write_terminate_counter + 1'd1;
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if (write_terminate_counter == burstcount_latch - 1'd1) write_terminating <= 0;
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end
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end
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/*
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* Bus mux depending on the stage.
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*/
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always_comb begin
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if (terminating) begin
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burstcount_master = burstcount_latch;
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address_master = address_latch;
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read_master = read_terminating;
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write_master = write_terminating;
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byteenable_master = 0;
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end
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else begin
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burstcount_master = burstcount_slave;
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address_master = address_slave;
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read_master = read_slave;
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byteenable_master = byteenable_slave;
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write_master = write_slave;
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end
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end
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// Just passing master <-> slave
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assign writedata_master = writedata_slave;
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assign readdata_slave = readdata_master;
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assign readdatavalid_slave = readdatavalid_master;
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assign waitrequest_slave = waitrequest_master;
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endmodule
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