125 lines
3.1 KiB
Systemverilog
125 lines
3.1 KiB
Systemverilog
module gamma_corr
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(
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input clk_sys,
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input clk_vid,
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input ce_pix,
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input gamma_en,
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input gamma_wr,
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input [9:0] gamma_wr_addr,
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input [7:0] gamma_value,
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input HSync,
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input VSync,
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input HBlank,
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input VBlank,
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input [23:0] RGB_in,
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output reg HSync_out,
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output reg VSync_out,
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output reg HBlank_out,
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output reg VBlank_out,
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output reg [23:0] RGB_out
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);
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(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve[768];
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always @(posedge clk_sys) if (gamma_wr) gamma_curve[gamma_wr_addr] <= gamma_value;
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always @(posedge clk_vid) gamma <= gamma_curve[gamma_index];
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reg [9:0] gamma_index;
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reg [7:0] gamma;
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always @(posedge clk_vid) begin
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reg [7:0] R_in, G_in, B_in;
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reg [7:0] R_gamma, G_gamma;
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reg hs,vs,hb,vb;
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reg [1:0] ctr = 0;
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reg old_ce;
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old_ce <= ce_pix;
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if(~old_ce & ce_pix) begin
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{R_in,G_in,B_in} <= RGB_in;
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hs <= HSync; vs <= VSync;
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hb <= HBlank; vb <= VBlank;
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RGB_out <= gamma_en ? {R_gamma,G_gamma,gamma} : {R_in,G_in,B_in};
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HSync_out <= hs; VSync_out <= vs;
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HBlank_out <= hb; VBlank_out <= vb;
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ctr <= 1;
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gamma_index <= {2'b00,RGB_in[23:16]};
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end
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if (|ctr) ctr <= ctr + 1'd1;
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case(ctr)
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1: begin gamma_index <= {2'b01,G_in}; end
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2: begin R_gamma <= gamma; gamma_index <= {2'b10,B_in}; end
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3: begin G_gamma <= gamma; end
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endcase
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end
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endmodule
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module gamma_fast
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(
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input clk_vid,
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input ce_pix,
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inout [21:0] gamma_bus,
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input HSync,
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input VSync,
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input HBlank,
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input VBlank,
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input DE,
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input [23:0] RGB_in,
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output reg HSync_out,
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output reg VSync_out,
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output reg HBlank_out,
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output reg VBlank_out,
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output reg DE_out,
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output reg [23:0] RGB_out
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);
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(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_r[256];
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(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_g[256];
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(* ramstyle="no_rw_check" *) reg [7:0] gamma_curve_b[256];
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assign gamma_bus[21] = 1;
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wire clk_sys = gamma_bus[20];
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wire gamma_en = gamma_bus[19];
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wire gamma_wr = gamma_bus[18];
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wire [9:0] gamma_wr_addr = gamma_bus[17:8];
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wire [7:0] gamma_value = gamma_bus[7:0];
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always @(posedge clk_sys) if (gamma_wr) begin
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case(gamma_wr_addr[9:8])
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0: gamma_curve_r[gamma_wr_addr[7:0]] <= gamma_value;
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1: gamma_curve_g[gamma_wr_addr[7:0]] <= gamma_value;
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2: gamma_curve_b[gamma_wr_addr[7:0]] <= gamma_value;
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endcase
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end
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reg [7:0] gamma_index_r,gamma_index_g,gamma_index_b;
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always @(posedge clk_vid) begin
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reg [7:0] R_in, G_in, B_in;
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reg [7:0] R_gamma, G_gamma;
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reg hs,vs,hb,vb,de;
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if(ce_pix) begin
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{gamma_index_r,gamma_index_g,gamma_index_b} <= RGB_in;
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hs <= HSync; vs <= VSync;
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hb <= HBlank; vb <= VBlank;
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de <= DE;
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RGB_out <= gamma_en ? {gamma_curve_r[gamma_index_r],gamma_curve_g[gamma_index_g],gamma_curve_b[gamma_index_b]}
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: {gamma_index_r,gamma_index_g,gamma_index_b};
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HSync_out <= hs; VSync_out <= vs;
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HBlank_out <= hb; VBlank_out <= vb;
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DE_out <= de;
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end
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end
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endmodule
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