372 lines
10 KiB
Systemverilog
372 lines
10 KiB
Systemverilog
//
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//
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// Copyright (c) 2012-2013 Ludvig Strigeus
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// Copyright (c) 2017,2018 Sorgelig
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//
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// This program is GPL Licensed. See COPYING for the full license.
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//
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//
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////////////////////////////////////////////////////////////////////////////////////////////////////////
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// altera message_off 10030
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module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
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(
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input clk,
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input ce_in,
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input [DWIDTH:0] inputpixel,
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input mono,
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input disable_hq2x,
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input reset_frame,
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input reset_line,
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input ce_out,
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input [1:0] read_y,
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input hblank,
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output [DWIDTH:0] outpixel
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);
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localparam AWIDTH = $clog2(LENGTH)-1;
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localparam DWIDTH = HALF_DEPTH ? 11 : 23;
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localparam DWIDTH1 = DWIDTH+1;
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(* romstyle = "MLAB" *) reg [5:0] hqTable[256];
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initial begin
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hqTable = '{
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
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19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
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19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
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19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
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};
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end
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wire [5:0] hqrule = hqTable[nextpatt];
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reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
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reg [23:0] A, B, D, F, G, H;
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reg [7:0] pattern, nextpatt;
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reg [1:0] cyc;
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reg curbuf;
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reg prevbuf = 0;
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wire iobuf = !curbuf;
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wire diff0, diff1;
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DiffCheck diffcheck0(Curr1, (cyc == 0) ? Prev0 : (cyc == 1) ? Curr0 : (cyc == 2) ? Prev2 : Next1, diff0);
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DiffCheck diffcheck1(Curr1, (cyc == 0) ? Prev1 : (cyc == 1) ? Next0 : (cyc == 2) ? Curr2 : Next2, diff1);
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wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
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wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
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wire [23:0] blend_result_pre;
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Blend blender(clk, ce_in, disable_hq2x ? 6'd0 : hqrule, Curr0, X, B, D, F, H, blend_result_pre);
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wire [DWIDTH:0] Curr20tmp;
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wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
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wire [DWIDTH:0] Curr21tmp;
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wire [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp;
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reg [AWIDTH:0] wrin_addr2;
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reg [DWIDTH:0] wrpix;
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reg wrin_en;
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function [23:0] h2rgb;
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input [11:0] v;
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begin
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h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]};
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end
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endfunction
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function [11:0] rgb2h;
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input [23:0] v;
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begin
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rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]};
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end
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endfunction
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hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
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(
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.clk(clk),
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.rdaddr(offs),
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.rdbuf0(prevbuf),
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.rdbuf1(curbuf),
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.q0(Curr20tmp),
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.q1(Curr21tmp),
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.wraddr(wrin_addr2),
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.wrbuf(iobuf),
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.data(wrpix),
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.wren(wrin_en)
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);
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reg [AWIDTH+1:0] read_x;
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reg [AWIDTH+1:0] wrout_addr;
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reg wrout_en;
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reg [DWIDTH1*4-1:0] wrdata, wrdata_pre;
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wire [DWIDTH1*4-1:0] outpixel_x4;
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reg [DWIDTH1*2-1:0] outpixel_x2;
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assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0];
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hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out
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(
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.clock(clk),
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.rdaddress({read_x[AWIDTH+1:1],read_y[1]}),
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.q(outpixel_x4),
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.data(wrdata),
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.wraddress(wrout_addr),
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.wren(wrout_en)
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);
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always @(posedge clk) begin
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if(ce_out) begin
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if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
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if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
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if(hblank) read_x <= 0;
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end
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end
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wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
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reg [AWIDTH:0] offs;
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always @(posedge clk) begin
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reg old_reset_line;
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reg old_reset_frame;
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reg [3:0] wrdata_finished;
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reg [AWIDTH+1:0] waddr;
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wrout_en <= 0;
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wrin_en <= 0;
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if(ce_in) begin
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// blend_result has been delayed by 4 cycles
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case(cyc)
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0: wrdata[DWIDTH:0] <= blend_result;
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1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
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2: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
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3: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
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endcase
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wrdata_finished <= wrdata_finished << 1;
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if(wrdata_finished[3]) begin
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wrout_en <= 1;
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wrout_addr <= waddr;
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end
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if(~&offs) begin
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if (cyc == 1) begin
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Prev2 <= Curr20;
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Curr2 <= Curr21;
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Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
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wrpix <= inputpixel;
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wrin_addr2 <= offs;
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wrin_en <= 1;
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end
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if(cyc==3) begin
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offs <= offs + 1'd1;
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waddr <= {offs, curbuf};
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wrdata_finished[0] <= 1;
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end
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end
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pattern <= new_pattern;
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if(cyc==3) begin
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nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
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{A, G} <= {Prev0, Next0};
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{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
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{Prev0, Prev1} <= {Prev1, Prev2};
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{Curr0, Curr1} <= {Curr1, Curr2};
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{Next0, Next1} <= {Next1, Next2};
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end else begin
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nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
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{B, F, H, D} <= {F, H, D, B};
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end
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cyc <= cyc + 1'b1;
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if(old_reset_line && ~reset_line) begin
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old_reset_frame <= reset_frame;
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offs <= 0;
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cyc <= 0;
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curbuf <= ~curbuf;
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prevbuf <= curbuf;
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{Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0;
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if(old_reset_frame & ~reset_frame) begin
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curbuf <= 0;
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prevbuf <= 0;
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end
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end
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old_reset_line <= reset_line;
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end
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end
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endmodule
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////////////////////////////////////////////////////////////////////////////////////////////////////////
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module hq2x_in #(parameter LENGTH, parameter DWIDTH)
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(
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input clk,
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input [AWIDTH:0] rdaddr,
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input rdbuf0, rdbuf1,
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output[DWIDTH:0] q0,q1,
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input [AWIDTH:0] wraddr,
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input wrbuf,
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input [DWIDTH:0] data,
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input wren
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);
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localparam AWIDTH = $clog2(LENGTH)-1;
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wire [DWIDTH:0] out[2];
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assign q0 = out[rdbuf0];
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assign q1 = out[rdbuf1];
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hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
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hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
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endmodule
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module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
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(
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input clock,
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input [DWIDTH:0] data,
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input [AWIDTH:0] rdaddress,
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input [AWIDTH:0] wraddress,
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input wren,
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output reg [DWIDTH:0] q
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);
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reg [DWIDTH:0] ram[0:NUMWORDS-1];
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always_ff@(posedge clock) begin
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if(wren) ram[wraddress] <= data;
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q <= ram[rdaddress];
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end
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endmodule
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////////////////////////////////////////////////////////////////////////////////////////////////////////
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module DiffCheck
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(
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input [23:0] rgb1,
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input [23:0] rgb2,
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output result
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);
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wire [7:0] r = rgb1[7:1] - rgb2[7:1];
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wire [7:0] g = rgb1[15:9] - rgb2[15:9];
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wire [7:0] b = rgb1[23:17] - rgb2[23:17];
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wire [8:0] t = $signed(r) + $signed(b);
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wire [9:0] y = $signed(t) + $signed({g[7], g});
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wire [8:0] u = $signed(r) - $signed(b);
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wire [9:0] v = $signed({g, 1'b0}) - $signed(t);
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// if y is inside (-96..96)
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wire y_inside = (y < 10'h60 || y >= 10'h3a0);
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// if u is inside (-16, 16)
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wire u_inside = (!u[8:4] || &u[8:4]); //(u < 9'h10 || u >= 9'h1f0);
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// if v is inside (-24, 24)
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wire v_inside = (v < 10'h18 || v >= 10'h3e8);
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assign result = !(y_inside && u_inside && v_inside);
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endmodule
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module Blend
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(
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input clk,
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input clk_en,
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input [5:0] rule,
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input [23:0] E,
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input [23:0] A,
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input [23:0] B,
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input [23:0] D,
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input [23:0] F,
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input [23:0] H,
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output [23:0] Result
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);
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localparam BLEND1 = 7'b110_10_00; // (A * 12 + B * 4 ) >> 4
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localparam BLEND2 = 7'b100_10_10; // (A * 8 + B * 4 + C * 4) >> 4
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localparam BLEND3 = 7'b101_10_01; // (A * 10 + B * 4 + C * 2) >> 4
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localparam BLEND4 = 7'b110_01_01; // (A * 12 + B * 2 + C * 2) >> 4
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localparam BLEND5 = 7'b010_11_11; // (A * 4 + B * 6 + C * 6) >> 4
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localparam BLEND6 = 7'b111_00_00; // (A * 14 + B * 1 + C * 1) >> 4
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reg [23:0] a,b,d,e,h,f;
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reg [3:0] bl_rule;
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reg [1:0] df_rule;
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always @(posedge clk) if (clk_en) begin
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{bl_rule,df_rule} <= rule;
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a <= A; b <= B; d <= D; e <= E; f <= F; h <= H;
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end
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wire is_diff;
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DiffCheck diff_checker(df_rule[1] ? b : h, df_rule[0] ? d : f, is_diff);
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reg [23:0] i10,i20,i30;
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reg [6:0] op0;
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always @(posedge clk) if (clk_en) begin
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i10 <= e;
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case({!is_diff, bl_rule})
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1,11,12,13,17: {op0, i20, i30} <= {BLEND1, a, 24'd0};
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2,14,18: {op0, i20, i30} <= {BLEND1, d, 24'd0};
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3,15,19: {op0, i20, i30} <= {BLEND1, b, 24'd0};
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4,20,24,27: {op0, i20, i30} <= {BLEND2, d, b};
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5,21: {op0, i20, i30} <= {BLEND2, a, b};
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6,22: {op0, i20, i30} <= {BLEND2, a, d};
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25,29: {op0, i20, i30} <= {BLEND5, d, b};
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26: {op0, i20, i30} <= {BLEND6, d, b};
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28: {op0, i20, i30} <= {BLEND4, d, b};
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30: {op0, i20, i30} <= {BLEND3, b, d};
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31: {op0, i20, i30} <= {BLEND3, d, b};
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default: {op0, i20, i30} <= {BLEND1, e, 24'd0};
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endcase
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end
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reg [23:0] i1,i2,i3;
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reg [6:0] op;
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always @(posedge clk) if (clk_en) begin
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op <= op0; i1 <= i10; i2 <= i20; i3 <= i30;
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end
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function [34:0] mul24x3;
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input [23:0] op1;
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input [2:0] op2;
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begin
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mul24x3 = 0;
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if(op2[0]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0]};
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if(op2[1]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 1'b0};
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if(op2[2]) mul24x3 = mul24x3 + {op1[23:16], 4'b0000, op1[15:8], 4'b0000, op1[7:0], 2'b00};
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end
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endfunction
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wire [35:0] res = {mul24x3(i1, op[6:4]), 1'b0} + mul24x3(i2, {op[3:2], !op[3:2]}) + mul24x3(i3, {op[1:0], !op[3:2]});
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always @(posedge clk) if (clk_en) Result <= {res[35:28],res[23:16],res[11:4]};
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endmodule
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