104 lines
2.2 KiB
Verilog
104 lines
2.2 KiB
Verilog
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module i2c
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(
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input CLK,
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input START,
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input READ,
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input [6:0] I2C_ADDR,
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input I2C_WLEN, // 0 - one byte, 1 - two bytes
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input [7:0] I2C_WDATA1,
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input [7:0] I2C_WDATA2,
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output [7:0] I2C_RDATA,
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output reg END = 1,
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output reg ACK = 0,
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//I2C bus
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output I2C_SCL,
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inout I2C_SDA
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);
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// Clock Setting
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parameter CLK_Freq = 50_000_000; // 50 MHz
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parameter I2C_Freq = 400_000; // 400 KHz
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localparam I2C_FreqX2 = I2C_Freq*2;
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reg I2C_CLOCK;
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reg [31:0] cnt;
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wire [31:0] cnt_next = cnt + I2C_FreqX2;
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always @(posedge CLK) begin
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cnt <= cnt_next;
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if(cnt_next >= CLK_Freq) begin
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cnt <= cnt_next - CLK_Freq;
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I2C_CLOCK <= ~I2C_CLOCK;
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end
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end
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assign I2C_SCL = (SCLK | I2C_CLOCK) ? 1'bZ : 1'b0;
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assign I2C_SDA = SDO[3] ? 1'bz : 1'b0;
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reg SCLK;
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reg [3:0] SDO;
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reg [0:7] rdata;
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reg [5:0] SD_COUNTER;
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reg [0:31] SD;
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initial begin
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SD_COUNTER = 'b111111;
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SD = 'hFFFF;
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SCLK = 1;
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SDO = 4'b1111;
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end
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assign I2C_RDATA = rdata;
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always @(posedge CLK) begin
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reg old_clk;
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reg old_st;
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reg rd,len;
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old_clk <= I2C_CLOCK;
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old_st <= START;
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// delay to make sure SDA changed while SCL is stabilized at low
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if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO[0] <= SD[SD_COUNTER[4:0]];
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SDO[3:1] <= SDO[2:0];
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if(~old_st && START) begin
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SCLK <= 1;
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SDO <= 4'b1111;
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ACK <= 0;
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END <= 0;
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rd <= READ;
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len <= I2C_WLEN;
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if(READ) SD <= {2'b10, I2C_ADDR, 1'b1, 1'b1, 8'b11111111, 1'b0, 3'b011, 9'b111111111};
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else SD <= {2'b10, I2C_ADDR, 1'b0, 1'b1, I2C_WDATA1, 1'b1, I2C_WDATA2, 4'b1011};
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SD_COUNTER <= 0;
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end else begin
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if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin
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SD_COUNTER <= SD_COUNTER + 6'd1;
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case(SD_COUNTER)
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01: SCLK <= 0;
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10: ACK <= ACK | I2C_SDA;
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19: if(~rd) begin
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ACK <= ACK | I2C_SDA;
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if(~len) SD_COUNTER <= 29;
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end
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20: if(rd) SCLK <= 1;
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23: if(rd) END <= 1;
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28: if(~rd) ACK <= ACK | I2C_SDA;
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29: if(~rd) SCLK <= 1;
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32: if(~rd) END <= 1;
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endcase
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if(SD_COUNTER >= 11 && SD_COUNTER <= 18) rdata[SD_COUNTER[4:0]-11] <= I2C_SDA;
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end
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end
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end
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endmodule
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