55 lines
839 B
Verilog
55 lines
839 B
Verilog
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module i2s
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#(
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parameter AUDIO_DW = 16
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)
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(
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input reset,
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input clk,
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input ce,
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output reg sclk,
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output reg lrclk,
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output reg sdata,
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input [AUDIO_DW-1:0] left_chan,
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input [AUDIO_DW-1:0] right_chan
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);
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always @(posedge clk) begin
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reg [7:0] bit_cnt;
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reg msclk;
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reg [AUDIO_DW-1:0] left;
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reg [AUDIO_DW-1:0] right;
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if (reset) begin
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bit_cnt <= 1;
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lrclk <= 1;
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sclk <= 1;
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msclk <= 1;
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end
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else begin
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sclk <= msclk;
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if(ce) begin
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msclk <= ~msclk;
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if(msclk) begin
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if(bit_cnt >= AUDIO_DW) begin
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bit_cnt <= 1;
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lrclk <= ~lrclk;
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if(lrclk) begin
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left <= left_chan;
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right <= right_chan;
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end
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end
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else begin
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bit_cnt <= bit_cnt + 1'd1;
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end
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sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
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end
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end
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end
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end
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endmodule
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