110 lines
2.0 KiB
Systemverilog
110 lines
2.0 KiB
Systemverilog
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// result = num/div
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module sys_udiv
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#(
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parameter NB_NUM,
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parameter NB_DIV
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)
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(
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input clk,
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input start,
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output busy,
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input [NB_NUM-1:0] num,
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input [NB_DIV-1:0] div,
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output reg [NB_NUM-1:0] result,
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output reg [NB_DIV-1:0] remainder
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);
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reg run;
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assign busy = run;
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always @(posedge clk) begin
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reg [5:0] cpt;
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reg [NB_NUM+NB_DIV+1:0] rem;
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if (start) begin
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cpt <= 0;
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run <= 1;
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rem <= num;
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end
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else if (run) begin
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cpt <= cpt + 1'd1;
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run <= (cpt != NB_NUM + 1'd1);
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remainder <= rem[NB_NUM+NB_DIV:NB_NUM+1];
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if (!rem[NB_DIV + NB_NUM + 1'd1])
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rem <= {rem[NB_DIV+NB_NUM:0] - (div << NB_NUM),1'b0};
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else
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rem <= {rem[NB_DIV+NB_NUM:0] + (div << NB_NUM),1'b0};
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result <= {result[NB_NUM-2:0], !rem[NB_DIV + NB_NUM + 1'd1]};
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end
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end
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endmodule
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// result = mul1*mul2
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module sys_umul
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#(
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parameter NB_MUL1,
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parameter NB_MUL2
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)
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(
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input clk,
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input start,
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output busy,
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input [NB_MUL1-1:0] mul1,
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input [NB_MUL2-1:0] mul2,
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output reg [NB_MUL1+NB_MUL2-1:0] result
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);
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reg run;
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assign busy = run;
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always @(posedge clk) begin
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reg [NB_MUL1+NB_MUL2-1:0] add;
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reg [NB_MUL2-1:0] map;
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if (start) begin
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run <= 1;
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result <= 0;
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add <= mul1;
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map <= mul2;
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end
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else if (run) begin
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if(!map) run <= 0;
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if(map[0]) result <= result + add;
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add <= add << 1;
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map <= map >> 1;
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end
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end
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endmodule
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// result = (mul1*mul2)/div
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module sys_umuldiv
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#(
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parameter NB_MUL1,
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parameter NB_MUL2,
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parameter NB_DIV
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)
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(
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input clk,
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input start,
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output busy,
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input [NB_MUL1-1:0] mul1,
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input [NB_MUL2-1:0] mul2,
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input [NB_DIV-1:0] div,
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output [NB_MUL1+NB_MUL2-1:0] result,
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output [NB_DIV-1:0] remainder
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);
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wire mul_run;
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wire [NB_MUL1+NB_MUL2-1:0] mul_res;
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sys_umul #(NB_MUL1,NB_MUL2) umul(clk,start,mul_run,mul1,mul2,mul_res);
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sys_udiv #(NB_MUL1+NB_MUL2,NB_DIV) udiv(clk,start|mul_run,busy,mul_res,div,result,remainder);
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endmodule
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