121 lines
1.8 KiB
Systemverilog
121 lines
1.8 KiB
Systemverilog
//
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// MCP23009
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// (C) 2019 Alexey Melnikov
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//
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module mcp23009
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(
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input clk,
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output reg [2:0] btn,
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input [2:0] led,
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output reg flg_sd_cd,
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output reg flg_present,
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output reg flg_mode,
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output scl,
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inout sda
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);
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reg start = 0;
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wire ready;
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wire error;
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reg rw;
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wire [7:0] dout;
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reg [15:0] din;
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i2c #(50_000_000, 500_000) i2c
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(
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.CLK(clk),
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.START(start),
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.READ(rw),
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.I2C_ADDR('h20),
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.I2C_WLEN(1),
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.I2C_WDATA1(din[15:8]),
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.I2C_WDATA2(din[7:0]),
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.I2C_RDATA(dout),
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.END(ready),
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.ACK(error),
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.I2C_SCL(scl),
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.I2C_SDA(sda)
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);
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always@(posedge clk) begin
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reg [3:0] idx = 0;
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reg [1:0] state = 0;
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reg [15:0] timeout = 0;
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if(~&timeout) begin
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timeout <= timeout + 1'd1;
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start <= 0;
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state <= 0;
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idx <= 0;
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btn <= 0;
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rw <= 0;
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flg_sd_cd <= 1;
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flg_present <= 0;
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flg_mode <= 1;
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end
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else begin
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if(~&init_data[idx]) begin
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case(state)
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0: begin
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start <= 1;
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state <= 1;
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din <= init_data[idx];
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end
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1: if(~ready) state <= 2;
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2: begin
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start <= 0;
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if(ready) begin
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state <= 0;
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if(!error) idx <= idx + 1'd1;
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end
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end
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endcase
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end
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else begin
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case(state)
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0: begin
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start <= 1;
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state <= 1;
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din <= {8'h09,5'b00000,led};
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end
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1: if(~ready) state <= 2;
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2: begin
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start <= 0;
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if(ready) begin
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state <= 0;
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rw <= 0;
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if(!error) begin
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if(rw) begin
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{flg_sd_cd, flg_mode, btn} <= {dout[7:3]};
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flg_present <= 1;
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end
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rw <= ~rw;
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end
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end
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end
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endcase
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end
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end
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end
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wire [15:0] init_data[12] =
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'{
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16'h00F8,
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16'h0138,
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16'h0200,
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16'h0300,
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16'h0400,
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16'h0524,
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16'h06FF,
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16'h0700,
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16'h0800,
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16'h0900,
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16'h0A00,
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16'hFFFF
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};
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endmodule
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